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Cadence Sigrity, Together At Last

Cadence Sigrity, Together At Last
by Paul McLellan on 02-10-2013 at 9:00 pm

In July Cadence acquired Sigrity, one of the leaders in PCB and IC packaging analysis. Until a decade ago, signal integrity and power analysis was something that only IC designers needed to worry about. For all except the highest performance boards, relatively simple tools were sufficient. Provided you hooked up the pins on all… Read More


Cosmic Circuits acquisition by Cadence: IP battle with Synopsys has officially started!

Cosmic Circuits acquisition by Cadence: IP battle with Synopsys has officially started!
by Eric Esteve on 02-09-2013 at 6:18 am

If you have missed the announcement that Cosmic Circuits has been acquired by Cadence, dated February 7, you may want to read this PR. In any case, by reading this article you will understand why this acquisition is ringing the start of the “IP battle” between cadence and Synopsys. Let me remind you that I said in Semiwiki last September… Read More


Building Energy-Efficient ICs from the Ground Up

Building Energy-Efficient ICs from the Ground Up
by Daniel Payne on 01-31-2013 at 6:02 pm

My oldest son just upgraded Smart Phones from a 3″ display to a 4.5″ display and was shocked to discover that his battery barely lasted 8 hours, so I welcomed him to the reality of limited battery life in modern SoC-based mobile devices. There is some hope in increasing battery life for our consumer-oriented devices … Read More


Virtuoso is 20nm-ready

Virtuoso is 20nm-ready
by Paul McLellan on 01-30-2013 at 1:47 pm

I already talked about how Cadence is splitting Virtuoso into two. Anyway, it is now officially announced. The 6.1 version will continue to be developed as a sort of Virtuoso classic for people doing designs off the bleeding edge that don’t require the new features. And a new Virtuoso 12.1 intended for people doing 20nm and… Read More


Cadence, Synopsys, and Mentor on FinFETs

Cadence, Synopsys, and Mentor on FinFETs
by Daniel Nenni on 01-27-2013 at 7:00 pm

In my opinion, FinFETs will be the most significant piece of technology we, as semiconductor ecosystem people, will experience this decade. Seriously this is exciting stuff and one of the top search terms on SemiWiki for 6 months running. Here is a quick peek at what the top EDA companies will be talking about at the Common PlatformRead More


What did CES 2013 mean for #SemiEDA?

What did CES 2013 mean for #SemiEDA?
by Don Dingee on 01-18-2013 at 4:55 pm

CES is the preeminent gadget show, and in the LVCC South Hall a wave has been building for some time. It’s now the place where chipsets are introduced, and this year saw a wide range of introductions from Atmel, Bosch, Broadcom, Intel (OK, they’re still in Central Hall), InvenSense, Marvell, NVIDIA, Qualcomm, Samsung, ST-Ericsson,… Read More


Yawn… New EDA Leader Results Are Coming

Yawn… New EDA Leader Results Are Coming
by Randy Smith on 01-18-2013 at 4:00 pm

We will soon start to see the quarterly financial reporting installments of the “Big 3” public EDA companies. I predict they will be as boring as usual. I am not sure if I would want it any differently though.

Back in the 90s there were times when it was truly interesting to wait to see what Cadence, Mentor, or later Synopsys, might announce.… Read More


Buying DDRn Controller IP AND Memory Model to the same IP vendor gives real TTM advantage

Buying DDRn Controller IP AND Memory Model to the same IP vendor gives real TTM advantage
by Eric Esteve on 01-17-2013 at 10:52 am

We all know the concept of “one stop shop”, becoming popular in the Design IP market. The topic we will address today is NOT the “one stop shop”, even if it looks similar, but rather that we could call “consistent design flow”.

What does that means? Simply that, if your SoC design is integrating a DDRn (LPDDR2, DDR3 or even DDR4, let’s… Read More


Cadence 3D Methodology

Cadence 3D Methodology
by Paul McLellan on 12-28-2012 at 8:20 pm

A couple of weeks ago was the 3D Architectures for Semiconductor Integration and Packagingconference in Redwood City. Cadence presented the changes that they have been making to their tool flow to enabled 2.5D (interposer-based) and true 3D TSV-based designs. You know what TSV stands for by now right? Through-silicon-via, … Read More


Cortex-A9 speed limits and PPA optimization

Cortex-A9 speed limits and PPA optimization
by Don Dingee on 12-19-2012 at 3:01 pm

We know by now that clock speeds aren’t everything when it comes to measuring the goodness of a processor. Performance has direct ties to pipeline and interconnect details, power factors into considerations of usability, and the unspoken terms of yield drive cost.

My curiosity kicked in when I looked at the recent press release… Read More