Part 2 examines the transformation of the interface protocols industry from a fragmented market of numerous specialized vendors to a more consolidated one dominated by a few major solutions providers as driven by the increasing complexity of modern protocols. It highlights the importance of rigorous validation of interface… Read More
Author: Lauro Rizzatti
The Journey of Interface Protocols: Adoption and Validation of Interface Protocols – Part 2 of 2
The Journey of Interface Protocols: The Evolution of Interface Protocols – Part 1 of 2
Prolog – Interface Protocols: Achilles’ Heels in Today’s State-of-the-art SOCs
June 30 was only a week away when Varun had a sleepless night. The call from the datacenter manager the evening before alerted him on a potential problem with the training of a new Generative AI model. Six months earlier Varun’s employer installed… Read More
Beyond the Memory Wall: Unleashing Bandwidth and Crushing Latency
VSORA AI Processor Raises $46 Million to Fast-Track Silicon Development
We stand on the cusp of an era defined by ubiquitous intelligence—a stone’s throw from a tidal wave of AI-powered products underpinned by next-generation silicon. Realizing that future demands nothing less than a fundamental rethink of how we design semiconductors… Read More
SNUG 2025: A Watershed Moment for EDA – Part 2
At this year’s SNUG (Synopsys Users Group) conference, Richard Ho, Head of Hardware, OpenAI, delivered the second keynote, titled “Scaling Compute for the Age of Intelligence.” In his presentation, Richard guided the audience through the transformative trends and implications of the intelligence era now unfolding before… Read More
SNUG 2025: A Watershed Moment for EDA – Part 1
Hot on the heels of DVConUS 2025, the 35th annual Synopsys User Group (SNUG) Conference made its mark as a defining moment in the evolution of Synopsys—and the broader electronic design automation (EDA) industry. This year’s milestone event not only underscored Synopsys’ continued innovation but also affirmed the vision… Read More
DVCon 2025: AI and the Future of Verification Take Center Stage
The 2025 Design and Verification Conference (DVCon) was a four-day event packed with insightful discussions, cutting-edge technology showcases, and thought-provoking debates. The conference agenda included a rich mix of tutorial sessions, a keynote presentation, a panel discussion, and an exhibit hall with Electronic… Read More
The Double-Edged Sword of AI Processors: Batch Sizes, Token Rates, and the Hardware Hurdles in Large Language Model Processing
Unlike traditional software programming, AI software modeling represents a transformative paradigm shift, reshaping methodologies, redefining execution processes, and driving significant advancements in AI processors requirements.
Software Programming versus AI Modeling: A Fundamental Paradigm Shift
Traditional… Read More
A Deep Dive into SoC Performance Analysis: Optimizing SoC Design Performance Via Hardware-Assisted Verification Platforms
Part 2 of 2 – Performance Validation Across Hardware Blocks and Firmware in SoC Designs
Part 2 explores the performance validation process across hardware blocks and firmware in System-on-Chip (SoC) designs, emphasizing the critical role of Hardware-Assisted Verification (HAV) platforms. It outlines the validation workflow… Read More
A Deep Dive into SoC Performance Analysis: What, Why, and How
Part 1 of 2 – Essential Performance Metrics to Validate SoC Performance Analysis
Part 1 provides an overview of the key performance metrics across three foundational blocks of System-on-Chip (SoC) designs that are vital for success in the rapidly evolving semiconductor industry and presents a holistic approach to optimize… Read More
SystemReady Certified: Ensuring Effortless Out-of-the-Box Arm Processor Deployments
When contemplating the Lego-like hardware and software structure of a leading system-on-chip (SoC) design, a mathematically inclined mind might marvel at the tantalizing array of combinatorial possibilities among its hardware and software components. In contrast, the engineering team tasked with its validation may have… Read More
Relaxation-Aware Programming in ReRAM: Evaluating and Optimizing Write Termination