Intro
On Friday I talked with Srinath Anantharaman by phone to gain some perspective on Hardware Configuration Management (HCM) versus Software Configuration Management (SCM), especially as it applies to the IC design flows in use today. In the 1990’s we both worked at Viewlogic in Fremont, CA and in 1997 Srinath founded… Read More
Author: Daniel Payne
Getting Real Time Calibre DRC Results
Last week I met with Joseph Davis, Ph.D. at Mentor Graphics in Wilsonville, Oregon to learn about a new product designed for full-custom IC layout designers to improve productivity.
The traditional flow for full-custom IC layout designers has been nearly unchanged for decades:
- Read a schematic or use Schematic Driven Layout
Custom and AMS Design
For IC designers creating full-custom or AMS designs there are plenty of challenges to getting designs done right on the first spin of silicon. Let me give you a sneak peek into what’s being discussed at the EDA Tech Forum in Santa Clara, CA on March 10th that will be of special interest to you:
3D TSV (Through Silicon Vias) are… Read More
DRC+, DFM, CMP, Variablility
When I worked at Intel as a circuit design engineer I could talk directly with the technology development engineers to understand how to really push my DRAM designs and get the smallest possible memory cell layout that would still yield well, provide fast access time, and long refresh cycles.
(United States Patent 6661699. Inventor:… Read More
DesignCon 2011 Trip Reports!
Cadence at DesignCon 2011
I met with Rahul Deokar, Product Manager this morning to review 9 slides that tell the story of Giga-gates and GigaHz systems design at Cadence. Their updated P&R system now completes jobs 2X faster for 28nm designs.
Silicon Realization Trends and Challenges:
Silicon Realization – end to end digital… Read More
iPDK is the way to go for AMS designs
I just read the press release from TowerJazz and Tanner EDA about how an AMS designer can use schematic symbols and layout generators in Tanner EDA tools for the TowerJazz 0.18um node. This is made possible because of the growing iPDK (Interoperable Process Design Kits) movement.
In the old days each foundry would have to staff up… Read More
Getting to the 32nm/28nm Common Platform node with Mentor IC Tools
Last week I talked with two experts at Mentor about the challenges of getting IC designs into the 32nm/28nm node on the Common Platform (IBM, GLOBALFOUNDRIES and Samsung). Global Foundries issued a press release talking about how the four major EDA companies have worked together to qualify EDA tools for this node.
Sudhakar Jilla,… Read More
EDA Mergers and Acquisition
I met Ian Getreu in Oregon at a monthly EDA networking luncheon several years ago and have kept in touch with him. Ian co-founded Analogy which was later acquired by Avant! (now Synopsys). One thing that Ian noticed over the years was that smaller EDA companies were constantly getting acquired by the bigger and publicly traded EDA… Read More
The Ultimate SPICE Circuit Simulator
I love SPICE and Fast SPICE circuit simulators, so here’s my feature list for the ultimate SPICE circuit simulator:
[LIST=1]
Webinar on Accelerating Analog Layout Productivity
MONROVIA, California – December 7, 2010 – With pressure to reduce time to market and with resources increasingly constrained, tools that can enable maximum productivity for analog and mixed-signal design are mission-critical. Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal… Read More
Rethinking Multipatterning for 2nm Node