Circuit Analysis & Debugging

Circuit Analysis & Debugging
by Daniel Payne on 03-30-2013 at 3:18 pm

Spice Debugger

In EDA we often talk about how fast a SPICE circuit simulator is, or about capacity and accuracy compared to silicon measurements. Yes, speed, capacity and accuracy are important, however when talking to actual transistor-level circuit designers you discover something quite different, most of their time is spent doing debugging,… Read More


An Analog IC Router

An Analog IC Router
by Daniel Payne on 03-29-2013 at 8:10 pm

Earlier this week I wrote about a Goliath in EDA, Synopsys, and their new analog router, today it’s the David in EDA, Pulsic and their Unity Analog Router. I spoke with several people from Pulsic by phone:

  • Christopher Jost – San Jose
  • Dave Noble – San Jose
  • Fumiaki Sato – Tokyo, Japan
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Unlocking the Full Potential of Soft IP

Unlocking the Full Potential of Soft IP
by Daniel Payne on 03-22-2013 at 11:32 am

EDA vendors, IP suppliers and Foundries provide an eco-system for SoC designers to use in getting their new electronic products to market quicker and at a lower cost. An example of this eco-system are three companies (TSMC, Atrenta, Sonics) that teamed up to produce a webinar earlier in March called: Unlocking the Full PotentialRead More


View from the top: Brad Quinton

View from the top: Brad Quinton
by Daniel Payne on 03-20-2013 at 3:53 pm

Many engineers dream about starting their own company some day, and today I talked with an engineer that has gone beyond the dreaming stage to actually start an EDA company and then get that company acquired. His name is Brad Quinton and the start-up was called Veridae Systems, now part of Tektronix.


Brad QuintonRead More


Interconnect Optimization of an SoC Architecture

Interconnect Optimization of an SoC Architecture
by Daniel Payne on 03-20-2013 at 11:41 am

My last chip design at Intel was a GPU called the 82786and the architects of the chip wrote a virtual prototype using the MAINSAIL language. By using a virtual prototype they were able to:

  • Simulate bus traffic, video display and video RAM
  • Determine throughput
  • Measure latency
  • Verify that bus priorities were working
  • Optimize the
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Visual Debugging at Altera on Billion-Transistor Chips

Visual Debugging at Altera on Billion-Transistor Chips
by Daniel Payne on 03-15-2013 at 10:38 am

My first job out of college was doing transistor-level circuit design, so I’m always curious about how companies are doing billion-transistor chip design and debug these days at the FPGA companies.

I spoke with Yaron Kretchmer,he works at Altera and manages the engineering infrastructure group where they have a compute… Read More


ARM Cortex SoC Prototyping Platform for Industrial Applications

ARM Cortex SoC Prototyping Platform for Industrial Applications
by Daniel Payne on 03-14-2013 at 1:00 pm

If your next SoC uses an ARM Cortex-A9 and has an industrial application, then you can save much design and debug time by using a prototyping platform. The price to prototype is quite affordable, and the methodology has a short learning curve. Bill Tomasan Aldec Research Engineer conducted a webinar today on: ARM Cortex SoC PrototypingRead More


Standard Cell Library Characterization

Standard Cell Library Characterization
by Daniel Payne on 03-13-2013 at 1:01 pm

Standard cell library characterization has been around for decades, Synopsys has been offering Liberty NCXand Cadence has Virtuoso Foundation IP Characterization. What’s new is that Mentor Graphics acquired the Z Circuit technology for library characterization and has integrated it with the Eldo Classic circuit … Read More


Visually Debugging IC Designs for AMS and Mixed-Languages

Visually Debugging IC Designs for AMS and Mixed-Languages
by Daniel Payne on 03-12-2013 at 4:18 pm

With an HDL-based design methodology many IC engineers code in text languages like SystemVerilog and VHDL, so it’s only natural to use a text-based debug methodology. The expression that, “A picture is worth a thousand words” comes to my mind and in this case a visual debug approach is worth considering for … Read More