For those of you who don’t know, Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification… Read More
Author: Daniel Nenni
Synopsys Magma Acquisition Stock Trading Under Investigation?
An attorney from the Division of Enforcement at the U.S. Securities & Exchange Commission contacted me in regards to activity on SemiWiki. Not a great way to start a Monday! Given the parameters of the discussion and the type of questions it is undoubtedly (in my humble opinion) concerning the Synopsys acquisition of Magma.… Read More
RTL Clock Gating Analysis Cuts Power by 20% in AMD Chip!
Approximately 25% of SemiWiki traffic originates from search engines and the key search terms are telling. Since the beginning of SemiWiki, “low power design” has been one of the top searches. This is understandable since the mobile market has been leading us down the path to fame and fortune. Clearly lowering the… Read More
SemiWiki Hits Major Readership Milestone!
For those of you who follow SemiWiki and the fabless semiconductor ecosystem it has been a very interesting two years:
The Semiconductor Wiki Project, the premier semiconductor collaboration site, is a growing online community of professionals involved with the semiconductor design and manufacturing ecosystem. Since going… Read More
Common Platform Technology Forum February 5th 2013 Live or Online!
Can’t make it to Santa Clara? Join us online!
The detailed 2013 CPTF agenda is now up in preparation for the February 5th event at the Santa Clara Convention Center. This is one of the rare times that you can get a free lunch! Watch this quick video to see what is in store for us this year. Dr. Paul McLellan and I will be there so please… Read More
Dynamic/Leakage Power Reduction in Memories
Embedded memories have an important impact on power. SoCs that integrate multiple functions on a single silicon die are at the heart of many electronic devices. As process geometries have scaled, design teams have used more and more of the additional silicon real estate available to integrate embedded memories that serve as scratch-pads,… Read More
Advanced Technology-Design-Manufacturing Co-optimization
I spent some quality time with Subi Kengeri, Vice President, Technology Architecture, Office of the CTO, GLOBALFOUNDRIES in Las Vegas during CES. Great guy, he worked at Silicon Access, Virage and TSMC before GF. One thing you should know about embedded memory guys, SRAM is the first thing that goes through a new process so they … Read More
A Brief History of Tanner EDA
While founder John Tanner, PhD, got his initial exposure to the TTL Cookbook and CMOS Cookbook as an undergraduate, it was his experience as a Caltech graduate student that forged his early path in EDA. In 1979, while enrolled in a VLSI design course at Caltech, John and his classmates received a pre-print of Carver Mead’s seminal… Read More
Cadence, Synopsys, and Mentor on FinFETs
In my opinion, FinFETs will be the most significant piece of technology we, as semiconductor ecosystem people, will experience this decade. Seriously this is exciting stuff and one of the top search terms on SemiWiki for 6 months running. Here is a quick peek at what the top EDA companies will be talking about at the Common Platform… Read More
How GLOBALFOUNDRIES is Differentiating in 2013
GLOBALFOUNDRIES changed the landscape of the foundry business in 2009 with a simple but ambitious plan to become the world’s first truly global foundry. At the Common Platform Technology Forum February 5th in the Santa Clara Convention Center GF Executive Vice President Michael Noonen will give an update on how that is … Read More
Intel’s Path to Technological Leadership: Transforming Foundry Services and Embracing AI