Automated debugging – starting from an unexpected behavior to find a bug root-cause or a small set of possible root-causes – is a hot topic now that agentic systems are playing a bigger role in automation. Unsurprising since debug remains the most time and resource-consuming aspect of verification, in turn the most time/resource-consuming… Read More
Author: Bernard Murphy
The Other Side of Bug Localization
RISC-V Advantage in Accelerator Control Highlights System Verification Challenges
When considering best-fit applications for RISC-V, the appeal of extending the instruction set and competitive pricing for storage and edge applications has been pretty clear. But I have always struggled to understand the appeal in head-on competition with Arm in premium applications such as servers and infrastructure systems.… Read More
IP Lifecycle Management in the AI Era
Large design enterprises have multiple concurrent activities around IP of various types: software/firmware, blocks defined in RTL or HLS, verification IPs of multiple different types, physical implementations, scripts/files for timing, power management, etc., etc. Each of these continues to evolve and branch to serve … Read More
Applying QED to Hardware Accelerator Verification. Innovation in Verification
QED (Quick Error Detection) can be a powerful complementary addition to verification but can be subject to size constraints. This month’s paper looks at a fix for that limitation. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A)… Read More
All-Embracing Multiphysics Analysis for Chiplet-Based Systems
What systems can accomplish by combining semiconductors, AI, and software seems at times boundless. Chiplet-based semiconductors deliver this promise, allowing a myriad of complex digital, memory, analog and photonic functions to be condensed into a single semiconductor package for higher performance, lower power consumption… Read More
PowerArtist RTL Power Estimation Folds into Keysight
Back in the late 1990s, Sente launched a product called WattWatcher to estimate power from design RTL and simulation activity. This was revolutionary for its time since alternatives, while very accurate, only offered power analysis at the gate level. Gate-level analysis is great for fine-tuning power but is unhelpful for achieving… Read More
Disaggregating AI Compute to Break the Tokens Barrier
Among several topics dominating news streams these days, giant datacenters are a leading theme. They point to an AI-centric future while raising real concerns about sustainability and scalability. Certainly land, power and water demand are very present concerns for most of us, witness growing pushback against building new… Read More
An Update on IP Lifecycle Management (IPLM)
IPLM is not always prominent, nevertheless it is a very necessary aspect of semiconductor (and systems) design. Modern designs build on a wide range of IPs and subsystems, each evolving through multiple variants and versions, each with different PPA characteristics and recommended use-cases, many from different suppliers… Read More
Quantum Simulation Using Decision Diagrams. Innovation in Verification
Quantum gate simulation complexity explodes as qubit counts increase. One way to manage this complexity in simulation on classical computers is through use of decision diagrams in place of matrices. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer… Read More
Are You Ready for Spec-Driven Verification?
Quick recap: verification is checking that your implementation of a design matches the in-house design/test specification. In contrast, validation means checking that the implementation matches design intent as defined by a customer specification, use cases, etc. Let’s focus on verification; for simplicity I’ll use “design… Read More
TSMC CoWoS versus Intel EMIB Semiconductor Packaging