Everspin’s recent fireside chat, moderated by Robert Blum of Lithium Partners, offered a crisp look at how the company is carving out a durable niche in non-volatile memory. CEO Sanjeev Agrawal’s core message was simple: MRAM’s mix of speed, persistence, and robustness lets it masquerade as multiple memory classes, data-logging,… Read More
Author: Admin
Everspin CEO Sanjeev Agrawal on Why MRAM Is the Future of Memory
Gartner Top Strategic Technology Trends for 2025: Agentic AI
Agentic AI refers to goal-driven software entities—“digital coworkers”—that can plan, decide, and act on an organization’s behalf with minimal supervision. Unlike classic chatbots or coding assistants that respond only to prompts, agentic systems combine models (e.g., LLMs) with memory, planning, tools/APIs, sensing,… Read More
Breaking the Sorting Barrier for Directed Single-Source Shortest Paths
Problem & significance.
Single-source shortest paths (SSSP) on directed graphs with non-negative real weights is a pillar of graph algorithms. For decades, the textbook gold standard has been Dijkstra’s algorithm with good heaps, running in the comparison-addition model (only comparisons and additions on weights).… Read More
Samtec Practical Cable Management for High-Data-Rate Systems
According to a recent Samtec whitepaper, in high-data-rate (HDR) architectures, where signals traverse tens to hundreds of gigabits per second, “cable management” isn’t a housekeeping chore, it’s a first-order design variable. The mechanical path a cable takes directly influences channel loss, crosstalk, reliability,
XTCO: From Node Scaling to System Scaling
imec XTCO (Cross-Technology Co-Optimization) is the natural successor to DTCO and STCO in an era where no single layer of the stack can deliver scaling alone. Instead of optimizing devices, interconnect, packaging, architecture, and software in isolation, XTCO treats them as one tightly coupled system with a shared budget … Read More
From Two Dimensional Growth to Three Dimensional DRAM
Epitaxial stacks of silicon and silicon germanium are emerging as a key materials platform for three dimensional dynamic random access memory. Future DRAM will likely migrate from vertical channels to horizontally stacked channels that resemble the gate all around concept in logic. That shift demands a starter material made… Read More
CoPoS is a Bigger Canvas for Chiplets and HBM
Chip on Panel on Substrate, often shortened to CoPoS, extends the familiar idea of chip on carrier packaging by moving the redistribution and interposer style structures from circular wafers to large rectangular panels. The finished panel assembly is then mounted on an organic or glass package substrate. This shift from round
AI’s Transformative Role in Semiconductor Design and Sustainability
On July 18, 2025, Serge Nicoleau from STMicroelectronics delivered a compelling presentation at DACtv, as seen in the YouTube video exploring how artificial intelligence (AI) is revolutionizing semiconductor design, edge computing, and sustainability. Addressing a diverse audience, Serge highlighted AI’s pervasive … Read More
Google Cloud: Optimizing EDA for the Semiconductor Future
On July 9, 2025, a DACtv session featured a Google product manager discussing the strategic importance of electronic design automation (EDA) and how Google Cloud is optimizing it for the semiconductor industry, as presented in the YouTube video. The talk highlighted Google Cloud’s role in addressing the escalating complexity… Read More
Synopsys FlexEDA: Revolutionizing Chip Design with Cloud and Pay-Per-Use
On July 9, 2025, Vikram Bhatia, head of product management for Synopsys’ cloud platform, and Sashi Obilisetty, his R&D engineering counterpart, presented a DACtv session on Synopsys FlexEDA, as seen in the YouTube video. Drawing from three and a half years of data, the session showcased how this cloud-based, pay-per-use… Read More
From Prompts to Prompt Engineering to Knowing Ourselves