Revolution EDA: A New EDA Mindset for a New Era

Revolution EDA: A New EDA Mindset for a New Era
by Admin on 11-17-2025 at 6:00 am

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Murat Eskiyerli, PhD, is the founder of Revolution EDA  

Modern software development environments have evolved dramatically. A developer can download Visual Studio Code, install a few plugins, and be productive within minutes. The cost? Perhaps a few hundred dollars per month for cloud development resources. Compare that toRead More


Hierarchically defining bump and pin regions overcomes 3D IC complexity

Hierarchically defining bump and pin regions overcomes 3D IC complexity
by Admin on 11-13-2025 at 8:00 am

connectivity in a hierarchical IC package floorplan

By Todd Burkholder and Per Viklund, Siemens EDA

The landscape of advanced IC packaging is rapidly evolving, driven by the imperative to support innovation on increasingly complex and high-capacity products. The broad industry trend toward heterogeneous integration of diverse die and chiplets into advanced semiconductor… Read More


EDA Has a Value Capture Problem — An Outsider’s View

EDA Has a Value Capture Problem — An Outsider’s View
by Admin on 11-11-2025 at 10:00 am

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By Liyue Yan (lyan1@bu.edu)

Fact 1: In the Computer History Museum, how many artifacts are about Electronic Design Automation (EDA)? Zero.

Fact 2: The average starting base salary for a software engineer at Netflix is $219K, and that number is $125K for Cadence; the starting base salary for a hardware engineer at Cadence is $119K… Read More


5 Lessons the Semiconductor Industry Can Learn from Gaming

5 Lessons the Semiconductor Industry Can Learn from Gaming
by Admin on 11-05-2025 at 10:00 am

Perforce 1

By Kamal Khan
The semiconductor world has always been the beating heart of tech innovation, powering everything from our smartphones to the latest AI breakthroughs. However, as chip complexity increases and market demands accelerate, adherence to traditional development cycles may be stagnating design teams and slowing … Read More


Why IP Quality and Governance Are Essential in Modern Chip Design

Why IP Quality and Governance Are Essential in Modern Chip Design
by Admin on 10-30-2025 at 6:00 am

Why IP Quality and Governance are Essential in Modern Chip Design

By Kamal Khan

In today’s semiconductor industry, success hinges not only on innovation but also on discipline in managing complexity. Every system-on-chip (SoC) is built from hundreds of reusable IP blocks—standard cells, memories, interfaces, and analog components. These IPs are the foundation of the design. But if the foundation… Read More


Visualizing hidden parasitic effects in advanced IC design 

Visualizing hidden parasitic effects in advanced IC design 
by Admin on 10-15-2025 at 10:00 am

[white paper] Parasitic Analysis Figures

By Omar Elabd

As semiconductor designs move below 7 nm, parasitic effects—resistance, capacitance and inductance—become major threats to IC performance and reliability, often hiding where netlist reviews cannot reach. Design teams need advanced visualization tools like heat maps, layer-based analysis and direct layout… Read More


Protect against ESD by ensuring latch-up guard rings

Protect against ESD by ensuring latch-up guard rings
by Admin on 10-13-2025 at 10:00 am

fig1 latchup event

By Mark Tawfik

Overview: Protecting ICs from costly ESD and latch-up failures

Electrostatic discharge (ESD) events cost the semiconductor industry an estimated $8 billion annually in lost productivity, warranty claims and product failures [1].

Ensuring the robust protection of integrated circuits (ICs) against various… Read More


MIN PULSE WIDTH (MPW) TIMING CHECK The Silent Timing Trap Lurking in Every Sub-5nm Design

MIN PULSE WIDTH (MPW) TIMING CHECK The Silent Timing Trap Lurking in Every Sub-5nm Design
by Admin on 10-05-2025 at 10:00 am

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By Zameer Mohammed

This article claims to provide clear key insights of Min Pulse Width (MPW) timing signoff check, proactive closure strategies for faster time-to-market, and effective methods to prevent silicon failures.

Min Pulse Width (MPW) check for timing signoff has become an important design constraint at the sub-5nmRead More


Thermal Sensing Headache Finally Over for 2nm and Beyond

Thermal Sensing Headache Finally Over for 2nm and Beyond
by Admin on 10-02-2025 at 6:00 am

PNPBJT in a diode connected configuration

By Nir Sever, Senior Director Business Development, proteanTecs

Silicon-proven LVTS for 2nm: a new era of accuracy and integration in thermal monitoring

Effective thermal management is crucial to prevent overheating and optimize performance in modern SoCs. Inadequate temperature control due to inaccurate thermal sensing… Read More


Global Semiconductor Industry Outlook 2026

Global Semiconductor Industry Outlook 2026
by Admin on 09-18-2025 at 6:00 am

Semiconductor and Beyond 2026 PWC

PwC’s comprehensive report, “Semiconductor and Beyond,” released in 2026, provides a strategic outlook on the global semiconductor industry amid rapid transformations driven by AI, geopolitical tensions, and supply chain shifts. Structured into four sections—Foreword, Demand Analysis, Supply Analysis,… Read More