Samsung’s Hot Chips 2026 presentation, “HBM Base Die: How HBM Will Evolve Using Advanced Logic Processes,” argues that the base die beneath a High Bandwidth Memory stack is about to become far more than a communications layer. Traditionally, an HBM base die mainly connects stacked DRAM dies to a GPU, TPU, or other processor and … Read More
Author: Admin
HBM’s Second Act: When Memory Starts Thinking
NVIDIA Vera: Rebuilding the CPU for Agentic AI
Source: Jonathon Evans and Polychronis Xekalakis, “NVIDIA Vera CPU,” Hot Chips 2026. Performance figures are NVIDIA claims, and several results were based on preproduction or unofficial testing.
NVIDIA’s Vera CPU is a server processor designed specifically for agentic AI, where language models repeatedly observe, reason,… Read More
Fail-Safe Frames: Why Chips&Media’s ASIL-B Video IP Matters
As vehicles evolve into software-defined, increasingly autonomous platforms, video processing is becoming part of the safety-critical computing chain. Camera feeds support functions ranging from surround-view monitoring and driver assistance to object detection and automated driving. If the hardware processing those… Read More
HBM’s Vertical Ascent: Why Packaging Is Becoming the Heart of AI Memory
SK hynix’s Hot Chips 2026 presentation explains how High Bandwidth Memory (HBM) is evolving to meet the extraordinary memory requirements of artificial intelligence. Its central message is that future progress will depend not only on better DRAM circuits but also on advanced packaging, denser vertical integration, improved… Read More
Five Billion Pulses Later: What DUV Optics Testing Reveals About Semiconductor Tool Uptime
By Dr. Sabina Kuprėnaitė
Deep-ultraviolet optics used in semiconductor lithography may be exposed to billions of pulses over their service life. That creates a qualification challenge that initial reflectance specifications or laser-induced damage thresholds alone cannot answer.
A mirror may meet its optical specification… Read More
Crescent Island: Turning Memory Capacity into Agentic AI Throughput
Intel’s Crescent Island is a discrete data-center GPU designed for agentic AI inference, where performance is constrained by more than matrix arithmetic. Multi-step agents impose latency through repeated model calls and tool interactions, consume large memory capacity for weights and long-context key-value caches, and… Read More
Intel Diamond Rapids: Building Xeon Up, Out, and Through Silicon
Akhilesh Kumar & Krishnakanth Sistla, Intel
Diamond Rapids is Intel’s next-generation Xeon processor, designed around the proposition that hyperscale performance increasingly depends on moving, processing, and protecting data as efficiently as executing instructions. The architecture replaces the conventional… Read More
Intel Wildcat Lake: Right-Sizing Silicon Without Sinking Performance
Lance Hacking, Intel
Intel Core Series 3, code-named Wildcat Lake, is a mainstream client system-on-chip derived from the Panther Lake-based Core Ultra Series 3 architecture. Its design objective is not maximum feature density, but broad deployment of current-generation CPU, graphics, AI, memory, security, and connectivity… Read More
RISC-V at Sixteen: From Modular ISA to Standardized Platforms at Hot Chips 2026
RISC-V has evolved from a Berkeley research architecture into a global instruction-set standard spanning embedded controllers, application processors, accelerators, and emerging servers. Its defining technical characteristic is not merely openness, but disciplined modularity. Four ratified base ISAs—RV32I, RV64I,… Read More
Hot Chips: Evolving Memory Architectures for Artificial Intelligence
Artificial intelligence performance is increasingly constrained by memory rather than arithmetic throughput. Scaling laws show that model quality improves when parameter count, training data, and compute grow together, but this balance fails when processors cannot obtain operands quickly enough. Contemporary accelerators… Read More
ASML and TSMC’s 12-Inch Photomask Initiative: Technical Significance