Why IP Quality and Governance Are Essential in Modern Chip Design

Why IP Quality and Governance Are Essential in Modern Chip Design
by Admin on 10-30-2025 at 6:00 am

IP Governance Graphic

By Kamal Khan

In today’s semiconductor industry, success hinges not only on innovation but also on discipline in managing complexity. Every system-on-chip (SoC) is built from hundreds of reusable IP blocks—standard cells, memories, interfaces, and analog components. These IPs are the foundation of the design. But if the foundation… Read More


Visualizing hidden parasitic effects in advanced IC design 

Visualizing hidden parasitic effects in advanced IC design 
by Admin on 10-15-2025 at 10:00 am

[white paper] Parasitic Analysis Figures

By Omar Elabd

As semiconductor designs move below 7 nm, parasitic effects—resistance, capacitance and inductance—become major threats to IC performance and reliability, often hiding where netlist reviews cannot reach. Design teams need advanced visualization tools like heat maps, layer-based analysis and direct layout… Read More


Protect against ESD by ensuring latch-up guard rings

Protect against ESD by ensuring latch-up guard rings
by Admin on 10-13-2025 at 10:00 am

fig1 latchup event

By Mark Tawfik

Overview: Protecting ICs from costly ESD and latch-up failures

Electrostatic discharge (ESD) events cost the semiconductor industry an estimated $8 billion annually in lost productivity, warranty claims and product failures [1].

Ensuring the robust protection of integrated circuits (ICs) against various… Read More


MIN PULSE WIDTH (MPW) TIMING CHECK The Silent Timing Trap Lurking in Every Sub-5nm Design

MIN PULSE WIDTH (MPW) TIMING CHECK The Silent Timing Trap Lurking in Every Sub-5nm Design
by Admin on 10-05-2025 at 10:00 am

pic1

By Zameer Mohammed

This article claims to provide clear key insights of Min Pulse Width (MPW) timing signoff check, proactive closure strategies for faster time-to-market, and effective methods to prevent silicon failures.

Min Pulse Width (MPW) check for timing signoff has become an important design constraint at the sub-5nmRead More


Thermal Sensing Headache Finally Over for 2nm and Beyond

Thermal Sensing Headache Finally Over for 2nm and Beyond
by Admin on 10-02-2025 at 6:00 am

PNPBJT in a diode connected configuration

By Nir Sever, Senior Director Business Development, proteanTecs

Silicon-proven LVTS for 2nm: a new era of accuracy and integration in thermal monitoring

Effective thermal management is crucial to prevent overheating and optimize performance in modern SoCs. Inadequate temperature control due to inaccurate thermal sensing… Read More


Global Semiconductor Industry Outlook 2026

Global Semiconductor Industry Outlook 2026
by Admin on 09-18-2025 at 6:00 am

Semiconductor and Beyond 2026 PWC

PwC’s comprehensive report, “Semiconductor and Beyond,” released in 2026, provides a strategic outlook on the global semiconductor industry amid rapid transformations driven by AI, geopolitical tensions, and supply chain shifts. Structured into four sections—Foreword, Demand Analysis, Supply Analysis,… Read More


Advancing Semiconductor Design: Intel’s Foveros 2.5D Packaging Technology

Advancing Semiconductor Design: Intel’s Foveros 2.5D Packaging Technology
by Admin on 09-15-2025 at 10:00 am

Intel Foundry Packaging Evolution 2025

In the rapidly evolving landscape of semiconductor manufacturing, the demand for processors that handle increasing workloads while maintaining power efficiency and compact form factors has never been higher. Intel’s Foveros 2.5D packaging technology emerges as a pivotal innovation, enabling denser die integration… Read More


Smart Verification for Complex UCIe Multi-Die Architectures

Smart Verification for Complex UCIe Multi-Die Architectures
by Admin on 09-08-2025 at 10:00 am

Figure 1

By Ujjwal Negi – Siemens EDA

Multi-die architectures are redefining the limits of chip performance and scalability through the integration of multiple dies into a single package to deliver unprecedented computing power, flexibility, and efficiency. At the heart of this transformation is the Universal Chiplet Interconnect… Read More


Revolutionizing Processor Design: Intel’s Software Defined Super Cores

Revolutionizing Processor Design: Intel’s Software Defined Super Cores
by Admin on 09-07-2025 at 2:00 pm

Intel European CPU Patent Application

In the ever-evolving landscape of computing, Intel’s patent application for “Software Defined Super Cores” (EP 4 579 444 A1) represents a groundbreaking approach to enhancing processor performance without relying solely on hardware scaling. Filed in November 2024 with priority from a U.S. application… Read More


TSMC’s 2024 Sustainability Report: Pioneering a Greener Semiconductor Future

TSMC’s 2024 Sustainability Report: Pioneering a Greener Semiconductor Future
by Admin on 09-07-2025 at 8:00 am

TSMC Substainability Report 2024 2025

TSMC, the world’s most trusted semiconductor foundry, released its 2024 Sustainability Report, underscoring its commitment to embedding environmental, social, and governance principles into its operations. Founded in 1987 and headquartered in Hsinchu Science Park, TSMC employs 84,512 people globally and operates… Read More