The silent killer of analog reliability: Why SPICE misses floating net

The silent killer of analog reliability: Why SPICE misses floating net
by Admin on 10-08-2026 at 6:00 am

87450 fig1 top level odo schematic

By Bhanu Pandey

The semiconductor industry is currently facing a significant challenge in functional verification. According to the most recent Wilson Research Group / Siemens EDA Functional Verification Study, first-silicon success rates have hit a historic low, with nearly 68% of designs requiring two or more spins. While… Read More


The Pivotal Moments That Gave Rise to Silicon Valley

The Pivotal Moments That Gave Rise to Silicon Valley
by Admin on 09-30-2026 at 10:00 am

IMAGE 1 Robert Noyce with microscope

The little-known decisions and breakthroughs—and the remarkable role of Robert Noyce—that helped shape the modern semiconductor industry

by Sunil Mehta

When people tell the story of how Silicon Valley came into being, they usually begin with a familiar sequence of events.

The transistor was invented at Bell Labs. William Shockley… Read More


LLM-assisted schematic test-report analysis and root-cause investigation

LLM-assisted schematic test-report analysis and root-cause investigation
by Admin on 09-28-2026 at 10:00 am

schematic report workflow white (1)

By Piyush Bag

Intro: In this AI era, building data centers has become crucial not just for hyperscalers, but for many companies as well, as they build the infrastructure for AI. At a high level, a data center includes compute, storage, networking, and other infrastructure. This article is about the design lifecycle of network hardware.… Read More


SEMICON West’s “Bridging design and Manufacturing with AI” Design Session Explores AI as Practical Lever Across Entire Lifecycle

SEMICON West’s “Bridging design and Manufacturing with AI” Design Session Explores AI as Practical Lever Across Entire Lifecycle
by Admin on 09-23-2026 at 10:00 am

Bridging sign and Manufacturing with AI

By Julie Rogers, Executive Director, Electronic System Design Alliance

SEMICON® West 2026 is “Bridging Design and Manufacturing with AI” during a day-long session Tuesday, October 13, from 10:30 a.m. to 4:30 p.m. at San Francisco’s Moscone Center, North Hall, Lower Level, Room 20.

The Design Session hosted and organized by … Read More


The Technical Problem Is Often Not the Business Problem

The Technical Problem Is Often Not the Business Problem
by Admin on 09-20-2026 at 10:00 am

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By Prof. Dr. S. Filo Ambrosini

On a semiconductor line, a rising defect rate can trigger a familiar debate. Do we need a new inspection system? More sensors? An additional engineer?

Those may all be valid responses. But before making the decision, someone needs to establish when the change began, where it first appears, and whether… Read More


A Study of Photoresist Bake Influence on Stochastics for DUV Immersion Lithography

A Study of Photoresist Bake Influence on Stochastics for DUV Immersion Lithography
by Admin on 09-15-2026 at 10:00 am

Photoresist Bake Influence on DUV Stochastics

Deep-ultraviolet (DUV) immersion lithography remains a critical patterning technology for advanced semiconductor manufacturing. Using a 193 nm ArF exposure system with water between the projection lens and wafer, immersion lithography increases numerical aperture and enables smaller features than dry exposure. However,… Read More


PCIe 7 Switch IP with Time Division Multiplexing: Powering the Next Generation of AI Connectivity

PCIe 7 Switch IP with Time Division Multiplexing: Powering the Next Generation of AI Connectivity
by Admin on 09-15-2026 at 6:00 am

PCIe 7 Switch IP with Time Division Multiplexing

By Tim Messegee, Senior Director of Solutions Marketing at Rambus

PCI Express (PCIe), PCIe switches, Time Division Multiplexing (TDM), Network Interface Cards (NICs), and SmartNICs are all well-established technologies that have formed the backbone of computing and networking systems for years. More recently, SuperNICs… Read More


HBM’s Second Act: When Memory Starts Thinking

HBM’s Second Act: When Memory Starts Thinking
by Admin on 09-08-2026 at 2:00 pm

HBM Base Die Revolution

Samsung’s Hot Chips 2026 presentation, “HBM Base Die: How HBM Will Evolve Using Advanced Logic Processes,” argues that the base die beneath a High Bandwidth Memory stack is about to become far more than a communications layer. Traditionally, an HBM base die mainly connects stacked DRAM dies to a GPU, TPU, or other processor and … Read More


NVIDIA Vera: Rebuilding the CPU for Agentic AI

NVIDIA Vera: Rebuilding the CPU for Agentic AI
by Admin on 09-08-2026 at 10:00 am

No Agent Left Waiting

Source: Jonathon Evans and Polychronis Xekalakis, “NVIDIA Vera CPU,” Hot Chips 2026. Performance figures are NVIDIA claims, and several results were based on preproduction or unofficial testing.

NVIDIA’s Vera CPU is a server processor designed specifically for agentic AI, where language models repeatedly observe, reason,… Read More


Fail-Safe Frames: Why Chips&Media’s ASIL-B Video IP Matters

Fail-Safe Frames: Why Chips&Media’s ASIL-B Video IP Matters
by Admin on 09-08-2026 at 6:00 am

Fail Safe Frames and Why Chips&Media’s ASIL B Video IP Matters

As vehicles evolve into software-defined, increasingly autonomous platforms, video processing is becoming part of the safety-critical computing chain. Camera feeds support functions ranging from surround-view monitoring and driver assistance to object detection and automated driving. If the hardware processing those… Read More