Front-end SoC design has always been a balancing act between speed, accuracy, and the large amount of manual work required to get RTL, IPs, and collaterals to be aligned. In a recent webinar, Defacto CEO and founder Chouki Aktouf joined by product manager Valentin Boyer, walked through how the company is bringing AI directly into… Read More
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Boost Front-End SoC Design With Defacto’s AI-Powered Tool
How early symmetry validation eliminates costly late-stage respins
By Mauli Shah, Product Engineer, Siemens
Analog and mixed-signal design teams face a persistent challenge that directly impacts tape-out schedules and project predictability: symmetry violations discovered at signoff trigger expensive respins, delay schedules and create unpredictable iteration cycles. Despite symmetry… Read More
Rethinking Formal Verification in the AI Era
By Kanav Arora, ML Researcher at ChipAgents
Most hardware teams already understand why formal verification matters. It can expose corner cases that simulation may never reach and establish critical behaviors across the modeled state space.
The unresolved question is not whether formal works. It is why formal remains a specialist… Read More
How Fast Can a Performance Model Actually Be Built?
By Thang Tran, CEO of Simplex Micro and Umesh Sisodia, CEO of CircuitSutra
Performance models have a reputation problem. They’re often treated as a long-lead, high-effort undertaking — something a design team commits to early and then waits on for months before it’s useful. The development of SimplEx Micro’s… Read More
Enhancing Multi-Domain System Simulation with FMI Co-Simulation
As systems become increasingly complex across every field of science and engineering, the importance of computer simulation in design, analysis, and verification continues to increase over time. The traditional process in which a system is modeled and simulated in a single tool is called monolithic simulation. On the other… Read More
GPU-native mask rule checking eliminates the curvilinear mask rule check bottleneck
As semiconductor manufacturing pushes toward advanced nodes with tighter feature sizes, the optical proximity correction (OPC) workflow is adopting curvilinear masks to achieve the larger process windows that traditional Manhattan geometries cannot deliver.
Traditional Manhattan masks constrain shapes to vertical … Read More
John Barr: The EDA Veteran and Award-Winning Needham Funds Portfolio Manager
John Barr, Portfolio Manager of the top-ranked Needham Aggressive Growth Fund, has built a career with skills honed not just on Wall Street, but in the trenches of the early EDA industry.
Before becoming a respected sell-side analyst and later a buy-side portfolio manager, Barr spent 15 years in the EDA industry, working through… Read More
SoC PLANNER: A New Generation of SoC Design Exploration Solution Managing Cost-effectiveness and Sustainability
With over a trillion chips manufactured every year and application requirements evolving faster than ever (across automotive, HPC, and AI), the pressure on SoC design teams has never been higher with design space keeps growing and schedules keep shrinking.
Indeed, for a complex SoC project, the number of possible configurations… Read More
Crossing the Yield Cliff: IDP V6 and the Future of Manufacturing Forecasting
The paper, Industrial Defectivity Prediction (IDP) V6: A Two-Layer Yield Cliff Framework for Cross-Industry Mass-Production Forecasting, presents a generalized industrial yield-modeling architecture that extends the classical Negative Binomial framework through a two-layer phenomenological structure designed … Read More
Solving the EDA tool fragmentation crisis
By Samar Abd El-Hady and Wael ElManhawy
Design teams today face an uncomfortable truth: the specialized tools they need to verify modern ICs can’t reliably share the same design data. As geometries shrink below five nanometers and designs incorporate billions of transistors across multiple dies, no single Electronic… Read More
ASML’s Path to Lithography Dominance—and the Coming Maskless Revolution