How Customized Foundation IP Is Redefining Power Efficiency and Semiconductor ROI

As computing expands from data centers to edge devices, semiconductor designers face increasing pressure to optimize both performance and energy efficiency. Advanced process nodes continue to provide transistor-level improvements, but scaling alone cannot meet the demands of hyperscale AI infrastructure or ultra-low-power edge systems.

Synopsys Foundation IP enables SoC designers to customize their designs for specific application requirements, combining IP optimization with advanced EDA flows. Real customer engagements demonstrate how this approach improves power efficiency, reduces energy consumption, and unlocks system-level performance gains beyond standard scaling benefits.

Hyperscale Compute: Power-Efficient 2nm SoCs

One customer develops SoCs for hyperscale AI and cloud infrastructure, where compute density and power efficiency directly impact operational costs. Even at 2nm nodes, transistor scaling alone could not deliver the needed performance-per-watt improvements.

Synopsys collaborated with the customer to customize Foundation IP and integrate it with advanced EDA optimization flows. Standard cells were refined for transistor sizing and threshold voltages, while layouts were adjusted to reduce routing parasitics. These changes improved both energy efficiency and performance in dense compute blocks.

The result was meaningful reductions in power consumption and higher silicon utilization, demonstrating how hyperscale customers can extend the value of advanced-node technology while lowering system-level operational costs.

• 34% reduced power consumption over baseline (using baseline EDA flow)
• 51% reduced power consumption over baseline (using an optimized EDA flow)
• 5% silicon area advantage over baseline

Edge AI Devices: Ultra-Low-Voltage Operation

Another customer develops Edge AI devices that require always-on functionality and strict energy efficiency. Battery life, standby power, and thermal constraints are critical, and standard IP could not reliably operate at ultra-low voltages.

Synopsys helped redesign memory bit cells and peripheral circuits to maintain read/write stability under low supply voltage. Assist circuitry improved access reliability, while memory compiler updates reduced standby power without sacrificing performance.

Logic libraries were optimized using low-leakage transistor configurations, and multi-rail voltage strategies allowed memory and logic to operate at independently optimized voltages. Variation-aware modeling and silicon correlation analysis reduced conservative guard-bands, enabling further voltage scaling and energy reduction.

These optimizations enabled every part of the chip to consume less power and occupy less space,  delivering longer battery life, improved thermal performance, and reliable always-on operation. The approach provides a repeatable framework for other Edge AI device manufacturers pursuing aggressive power efficiency goals.

Cross-Domain Engineering: A New Implementation Model

Both customer engagements highlight the value of cross-domain engineering, where IP design, EDA flows, and system-level architecture are optimized together. Coordinated optimization allows teams to evaluate performance and power across multiple layers of design and operating conditions.

This methodology helps uncover efficiency opportunities that traditional sequential design approaches often miss. It also reduces design risk, improves first-silicon success, and accelerates time-to-market. Customized IP can be reused across future designs, amplifying long-term return on engineering investment.

Delivering System-Level ROI

These customer engagements illustrate a broader industry trend: semiconductor return on investment increasingly depends on extracting value across the entire design stack, rather than relying solely on transistor scaling. For hyperscale infrastructure, customized IP helps reduce energy consumption, increase compute density, and lower operational costs, while for Edge AI devices, it enables ultra-low-voltage operation, extends battery life, and improves overall device functionality. In addition, reducing guard-bands and optimizing design margins further enhance manufacturing efficiency and strengthen product competitiveness. The techniques demonstrated through these engagements are transferable across similar market segments, providing a practical framework that allows both hyperscale and Edge AI customers to accelerate innovation and maximize performance-per-watt.

Summary

As AI workloads grow and edge intelligence proliferates, customized Foundation IP coupled with advanced EDA optimization will continue to be a key enabler of power-efficient, high-performance semiconductor design.

By combining cross-domain engineering with application-specific IP customization, Synopsys helps customers extend the benefits of scaling into system-level performance, energy efficiency, and economic gains across hyperscale infrastructure, Edge AI devices, and emerging intelligent computing platforms.

Visit Synopsys Foundation IP page.