On July 18, 2025, a DACtv session titled “From Atoms to Tokens” explored the semiconductor supply chain’s transformation, as presented in the YouTube video. The speaker tackled the challenges and innovations from the atomic level of chip fabrication to the tokenized ecosystems of AI-driven data centers, emphasizing the critical role of interconnect scaling, advanced packaging, and fault-tolerant computing in meeting the demands of modern AI and high-performance chips.

At the atomic level, interconnect scaling remains a bottleneck. Since the shift from aluminum to copper in 1998, progress has stalled, with Intel’s failed cobalt experiment at 10nm underscoring the difficulty. Emerging materials like tungsten (already used in contacts and vias), molybdenum, and ruthenium are being explored for 1.6nm nodes, necessitating new subtractive manufacturing processes that overhaul traditional dual damascene methods. These changes significantly alter design rules, impacting AI chips where interconnect performance is critical, unlike mobile chips with less stringent requirements. Backside power delivery, set to enter high-volume production within years, further complicates design-for-test strategies, as metal layers on both wafer sides hinder metrology, demanding new EDA tools to ensure reliability.

Lithography advancements, once expected to simplify design rules, have disappointed. High-NA EUV, anticipated to streamline processes, is being delayed, with TSMC opting against adoption due to cost-effectiveness of multi-patterning EUV over single-patterning. Scaling boosters like pattern shaping (ion beam manipulation) and directed self-assembly (DSA), adopted by Intel at 14A, introduce further design rule complexity but promise cost savings. These shifts challenge EDA workflows, requiring tools to adapt to rapidly evolving fabrication techniques.

Packaging innovations are driving transistor density. While Moore’s Law cost-per-transistor trends have plateaued, advanced packaging like 2.5D (silicon interposers) and 3D (RDL interposers, local silicon bridges) has skyrocketed transistor counts per package. Techniques like TSMC’s SoIC and hybrid bonding achieve finer pitches (down to 9 microns), critical for chiplet-based AI accelerators. However, these require sophisticated thermal and stress modeling, as chiplets strain EDA tools for signal integrity and power delivery. The speaker highlighted the need for new design flows to handle these complexities, especially for AI chips where performance is paramount.

At the system level, AI data centers demand unprecedented scale. Clusters with millions of GPUs, like Meta’s 2-gigawatt Louisiana facility, consume power rivaling major cities. Optical interconnects, with a five-year mean time between failure, pose reliability issues; a 500,000-GPU cluster could fail every five minutes. Co-packaged optics (CPO) exacerbate this, despite improved reliability, necessitating fault-tolerant strategies like Meta’s open-sourced training library. Inter-data-center connectivity, with Microsoft’s $10 billion fiber deals and Corning’s massive orders, underscores the infrastructure challenge. Projects like Stargate, with $50-100 billion investments, aim for multi-gigawatt clusters, pushing EDA to model reliability and power at unprecedented scales.

The China market, addressed in Q&A, presents unique challenges. Huawei’s subsidiary SMIC is ramping production, but reliance on foreign EDA tools and materials (e.g., Japanese photoresists and etchants) persists. China’s open-source contributions, like ByteDance’s Triton library, contrast with restricted GPU access, complicating analysis. The speaker noted that tracking China’s semiconductor progress via WeChat and forums is fraught with noise, similar to Reddit or Twitter, highlighting the difficulty of accurate market assessment.

This session underscored the semiconductor industry’s pivot toward AI-driven design, from atomic-level material innovations to tokenized, fault-tolerant data center ecosystems. EDA tools must evolve to handle new design rules, packaging complexities, and massive-scale reliability, ensuring the industry meets the soaring demand for AI and high-performance computing.

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