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CEO Interview with Dr. Noah Strucken of Ferric

CEO Interview with Dr. Noah Strucken of Ferric
by Daniel Nenni on 06-30-2025 at 10:00 am

Noah Sturcken headshot

Noah Sturcken is a Founder and CEO of Ferric with over 40 patents issued and 15 publications on Integrated Voltage Regulators. Noah leads Ferric with focus on business development, marketing and new technology development. Noah previously worked at AMD R&D Lab where he developed Integrated Voltage Regulator (IVR) technology.… Read More


Jitter: The Overlooked PDN Quality Metric

Jitter: The Overlooked PDN Quality Metric
by Admin on 06-30-2025 at 6:00 am

Figure 1 – Accumulated jitter

The most common way to evaluate a power distribution network is to look at its impedance over the effective frequency range. A lower impedance will produce less noise when transient current is demanded by the IC output buffers. However, this transient current needs to be provided at the same time for each transition or jitter will… Read More


Facing the Quantum Nature of EUV Lithography

Facing the Quantum Nature of EUV Lithography
by Fred Chen on 06-29-2025 at 8:00 am

Absorbed Photons Exposing EUV

The topics of stochastics and blur in EUV lithography has been examined by myself for quite some time now [1,2], but I am happy to see that others are pursuing this direction seriously as well [3]. As advanced node half-pitch dimensions approach 10 nm and smaller, the size of molecules in the resist become impossible to ignore for … Read More


Podcast EP294: An Overview of the Momentum and Breadth of the RISC-V Movement with Andrea Gallo

Podcast EP294: An Overview of the Momentum and Breadth of the RISC-V Movement with Andrea Gallo
by Daniel Nenni on 06-27-2025 at 10:00 am

Dan is joined by Andrea Gallo, CEO of RISC-V International, the non-profit home of the RISC-V instruction set architecture standard, related specifications, and stakeholder community. Prior to joining RISC-V International, Gallo worked in leadership roles at Linaro for over a decade. He built Linaro’s server engineering… Read More


CEO Interview with Vamshi Kothur, of Tuple Technologies

CEO Interview with Vamshi Kothur, of Tuple Technologies
by Daniel Nenni on 06-27-2025 at 6:00 am

vamshi profile (1)


It was my pleasure to meet with Vamshi Kothur and the Tuple team at #62DAC for a briefing on their Tropos platform and Omni, a new multi-cloud optimizer. The conferences this year have been AI infused with exciting new technologies but one of the lingering questions is: How will the existing semiconductor design IT infrastructure… Read More


Webinar – Power is the New Performance: Scaling Power & Performance for Next Generation SoCs

Webinar – Power is the New Performance: Scaling Power & Performance for Next Generation SoCs
by Mike Gianfagna on 06-26-2025 at 10:00 am

Webinar Scaling Power Performance for Next Generation SoCs

What if you could reduce power and extend chip lifetime, without compromising performance? We all know the importance of power optimization for advanced SoCs. Thanks to the massive build out of AI workloads, power consumption has gone from a cost or cooling headache to an existential threat to the planet, if current power consumptions… Read More


Reachability in Analog and AMS. Innovation in Verification

Reachability in Analog and AMS. Innovation in Verification
by Bernard Murphy on 06-26-2025 at 6:00 am

Innovation New

Can a combination of learning-based surrogate models plus reachability analysis provide first pass insight into extrema in circuit behavior more quickly than would be practical through Monte-Carlo analysis? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys… Read More


CEO Interview with Yannick Bedin of Eumetrys

CEO Interview with Yannick Bedin of Eumetrys
by Daniel Nenni on 06-25-2025 at 10:00 am

Yannick Bedin CEO Eumetrys

Yannick founded EUMETRYS in 2012. He began his engineering career for Schlumberger in 1998 in West Africa and then became an applications engineer for the company from 2000 to 2004 in the semiconductor sector. In 2004, he joined Soluris as a field service engineer until 2006, then Nanometrics as a technical product support specialist.… Read More


Visualizing System Design with Samtec’s Picture Search

Visualizing System Design with Samtec’s Picture Search
by Mike Gianfagna on 06-25-2025 at 6:00 am

Visualizing System Design with Samtec’s Picture Search

If you’ve spent a lot of time in the chip or EDA business, “design” typically means chip design. These days it means heterogeneous multi-chip design. If you’ve spent time developing end products, “design” has a much broader meaning. Chips, subsystems, chassis and product packaging are in focus. This is just a short list if you consider… Read More


Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot

Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot
by Jonah McLeod on 06-24-2025 at 10:00 am

Table 1

In 2003, legendary computer architect Michael J. Flynn issued a warning that most of the industry wasn’t ready to hear. The relentless march toward more complex CPUs—with speculative execution, deep pipelines, and bloated instruction handling—was becoming unsustainable. In a paper titled “Computer Architecture … Read More