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Shaping Tomorrow’s Semiconductor Technology IEDM 2024

Shaping Tomorrow’s Semiconductor Technology IEDM 2024
by Scotten Jones on 10-23-2024 at 6:00 am

IEDM 2024 SFO

Anyone who has read my articles about IEDM in the past know I consider it a premiere conference covering developments of leading-edge semiconductor process technology. The 2024 conference will take place in San Francisco from December 7th through 11th.

Some highlight of this year’s technical program are:

AI  – Lots of artificial… Read More


SI and PI Update from Cadence on Sigrity X

SI and PI Update from Cadence on Sigrity X
by Daniel Payne on 10-22-2024 at 10:00 am

Sigrity X

Signal Integrity (SI) and Power Integrity (PI) issues are critical to analyze, ensuring the proper operation of PCB systems and IC packages, yet the computational demands from EDA tools can cause engineers to only analyze what they deem are critical signals, instead of the entire system. Cadence has managed to overcome this SI/PI… Read More


Advanced Audio Tightens Integration to Implementation

Advanced Audio Tightens Integration to Implementation
by Bernard Murphy on 10-22-2024 at 6:00 am

girl wearing wireless earbuds on noisy street min

You might think that in the sensing world all the action is in imaging and audio is a backwater. While imaging features continue to evolve, audio innovations may be accelerating even faster to serve multiple emerging demands: active noise cancellation, projecting a sound stage from multiple speakers, 3D audio and ambisonics,… Read More


Unlocking SoC Debugging Challenges: Paving the Way for Efficient Prototyping

Unlocking SoC Debugging Challenges: Paving the Way for Efficient Prototyping
by Daniel Nenni on 10-21-2024 at 10:00 am

3D rendering of cyberpunk AI. Circuit board. Technology background. Central Computer Processors CPU and GPU concept. Motherboard digital chip. Tech science background.

As chip design complexity increases, integration scales expand, and time-to-market pressures grow, design verification has become increasingly challenging. In multi-FPGA environments, the complexity of design debugging and verification further escalates, making it difficult for traditional debugging methods to meet… Read More


Analog Bits Builds a Road to the Future at TSMC OIP

Analog Bits Builds a Road to the Future at TSMC OIP
by Mike Gianfagna on 10-21-2024 at 6:00 am

Analog Bits Builds a Road to the Future at TSMC OIP

The TSMC Open Innovation Platform (OIP) Ecosystem Forum has become the industry benchmark when it comes to showcasing industry-wide collaboration. The extreme design, integration and packaging demands presented by multi-die, chiplet-based design have raised the bar in terms of required collaboration across the entire … Read More


Podcast EP254: How Genealogy Correlation Can Uncover New Design Insights and improvements with yieldHUB’s Kevin Robinson

Podcast EP254: How Genealogy Correlation Can Uncover New Design Insights and improvements with yieldHUB’s Kevin Robinson
by Daniel Nenni on 10-18-2024 at 10:00 am

Dan is joined by Kevin Robinson, yieldHUB’s Vice President of operations and sales. With over 23 years of experience as a test engineer in the semiconductor industry, Kevin brings a wealth of knowledge and dedication to his dual role. At yieldHUB, Kevin leads both sales and operations teams, playing a crucial role in delivering… Read More


CEO Interview: Dr. Mehdi Asghari of SiLC Technologies

CEO Interview: Dr. Mehdi Asghari of SiLC Technologies
by Daniel Nenni on 10-18-2024 at 6:00 am

Dr. Mehdi Asghari

Mehdi is a serial entrepreneur with a track record of success. He is currently CEO and co-founder of SiLC. SiLC is his third Silicon Photonics start up focusing on advanced imaging solutions that enable machines to see like humans. His previous start up, Kotura where he was CTO and SVP of Engineering, developed communication solutions… Read More


Prioritize Short Isolation for Faster SoC Verification

Prioritize Short Isolation for Faster SoC Verification
by Ritu Walia on 10-17-2024 at 10:00 am

Fig1 shorts analysis conf data

Improve productivity by shifting left LVS
In modern semiconductor design, technology nodes continue to shrink and the complexity and size of circuits increase, making layout versus schematic (LVS) verification more challenging. One of the most critical errors designers encounter during LVS runs are shorted nets. Identifying… Read More


The Perils of Aging, From a Semiconductor Device Perspective

The Perils of Aging, From a Semiconductor Device Perspective
by Mike Gianfagna on 10-17-2024 at 6:00 am

The Perils of Aging, From a Semiconductor Device Perspective

We‘re all aware of the challenges aging brings. I find the older I get, the more in touch I feel with those challenges.  I still find it to be true that aging beats the alternative. I think most would agree. Human factors aside, I’d like to discuss the aging process as applied to the realm of semiconductor device physics. Here, as with… Read More


ASML surprise not a surprise (to us)- Bifurcation- Stocks reset- China headfake

ASML surprise not a surprise (to us)- Bifurcation- Stocks reset- China headfake
by Robert Maire on 10-16-2024 at 10:00 am

ASML 2024 Downturn
  • Investors finally realize the upcycle isn’t as strong as stocks indicated
  • Industry Bifurcation between AI & rest of industry continues
  • China spending risk/overhang finally kicks in
  • AI is super strong, majority of chips remain weak- Invest accordingly
ASML simply states chip industry reality that investors have
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