Semiwiki 400x100 1 final

Senior RTL Designer

Senior RTL Designer
by Admin on 01-26-2024 at 2:51 pm

Education

  • BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication)

Key Responsibilities

  • Able to understand block guides, create FSM from the description.
  • Should be able to understand micro level architecture
  • Develop RTL blocks from scratch and reach a point of synthesis clearance.
  • Develop and execution of system use case scenarios
  • Work on clock domain crossing will add more in skill-set
  • Excellent team player & can guide juniors also

Knowledge/Skills

  • Excellent digital skill set
  • Logic development
  • Good experience in Verilog & RTL coding
  • Synthesys, lintin & CDC tools
  • Working on NoC will add more in skills
  • Protocol knowledge – AXI/ AHB/ APB/ Tilelink
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