Statistically speaking you probably care about On-chip Variation

There are some metaphorical similarities between reaching timing signoff and driving a car to your destination. Most of us get in the car, turn the key and push the gas pedal to make it go. While we might have a cursory understanding of what makes it go, there are actually a lot of “moving part” under the hood in each instance. For most car drivers it is not an issue if they don’t really understand the workings of their automobile. However, in the case of timing signoff, it’s pretty important that designers and engineering managers understand how things work.

Silvaco is in an interesting position when it comes to understanding timing signoff. They develop tools across the spectrum, from TCAD to SPICE, library characterization and timing tools. This is why their recent webinar about “On-Chip Variation and the Sign-off Timing Flow: An Industry Perspective” was so interesting. With larger designs, smaller process nodes and higher volumes, timing signoff has become much more challenging over the years. On-chip variation has become a huge factor in determining silicon success and yield.

The webinar covered the various factors that lead to variation and how timing signoff methodologies have had to adapt to consider these new factors. When signoff methodology changes, the models that are used to drive the tools also need to change, to offer the information needed by the tools that use them. As a result, library characterization has been an area that has seen active development and significant advances.

The webinar presenter, Bernardo Culau, Director of Library Characterization at Silvaco, did an excellent job of reviewing how the needs and methods for timing signoff have evolved, from the early days of OCV modeling to the latest statistical methods. He provided an concise overview of the sources of variation and how each generation of sign off tools has progressed to reduce pessimism and increase efficiency to keep up with growing complexity.

Variation is caused by just about anything that can fluctuate during chip fabrication and later on during operation. On-chip variation specifically addresses difference in fabrication parameters, and operational temperature and voltage within a given die. This includes such things as channel width, dopant fluctuations, dishing, lithography issues, etc.

Bernardo untangled the alphabet soup of library formats and techniques. Among there were: OCV, SBOCV, AOCV, POCV and finally LVF. The variation modeling techniques needed vary with process node. Older nodes such as 90nm can get by with simpler models. By the time we get to 7nm, only the most advanced statistical methods can be relied on.

An important point he touched on was that statistical methods need to move from relying on Gaussian distributions and move to Moment Based LVF. More information needs to be included in the model files for the true distribution to be properly represented.

Bernardo concluded with an overview of the suite of Silvaco tools for library characterization. Their Viola tool uses parallel processing to complete cell characterization and is compatible with all the leading SPICE simulators, including Silvaco’s own SmartSpice. Cello is used for library migration, and they also offer a Liberty Library Analyzer. Their Jivaro tool can help improve efficiency by performing parasitic reduction with minimal impact on accuracy.  VarMan is their flagship solution for exploring the yield impacts on a design caused by variation.

If you want to improve your understanding of what is happening under the hood in timing signoff, this webinar provides a wealth of information. I for one like to know about the specifics, because the additional knowledge could make the difference between being stranded on the road or safely getting to your destination. The full replay of this webinar can be found through the Silvaco website.