A Brief History of CLKDA: Every Picosecond Counts Below 28nm

One thing to point out is that the CLK of CLKDA are the initials of the founders, they are not focused on clocks! I’m sure you can guess what DA stands for, although it is also the last two letters of the fourth founder’s name.

They have been in existence since 2005, backed by Atlas Ventures and Morgenthaler. They are headquartered in Littleton, MA just outside Boston. The CEO is Isadore Katz.

In the early days they did some other stuff (STA) but they have since pivoted and now CLKDA is the market and technology leader in timing variance analysis. FX is the first transistor model and simulator specifically engineered for digital variance and delay analysis. FX is in production at the most advanced IC geometries at 20nm, 16nm and 14nm, with all of the leading foundries. CLKDA drove the creation of Liberty Variance Format (LVF), the open standard for modeling timing variance.

Starting at 40nm, manufacturing variance became a serious issue that had to be addressed during timing sign-off. Traditional manufacturing corners were no longer sufficient. If designers ignored manufacturing variance, yield would suffer when it bit them. But over-compensating didn’t work either: the center of the distribution of timing (typical) moved from the previous node, but excessive pessimism meant that worst case was almost unchanged, making timing closure next to impossible, and wasting power. To make things worse, the tails were also getting longer.

CLKDA brought together a team of EDA and semiconductor veterans with expertise in timing, circuit design, and simulation, as well as applied mathematics and distributed computing. The result was a very efficient, fully distributed static timing framework combined with a radical new circuit simulator and model called FX—the first transistor level model specifically designed for timing delay and variance. What makes FX special is its ability to model timing variance without using sampling—variance is solved mathematically. FX can literally be tens of thousand of times faster than MC SPICE, and stay within 2% of SPICE results.

CLKDA began development of FX in collaboration with TSMC in 2008. The first targeted application was the efficient generation of stage-based on-chip variation tables (SBOCV aka AOCV) for use during sign-off timing. Generating these tables consumed literally months of Monte Carlo SPICE simulations, and a much better solution was required.

The result was AOCV FX. Introduced at DAC 2010, and included in TSMC Reference Flow 11, AOCV FX was the first commercial solution for generating SBOCV and AOCV tables. Using the FX model, AOCV FX is thousands of times faster than using Monte Carlo SPICE for generating derate tables with the same compute resources. AOCV FX made SBOCV and AOCV table generation a practical reality.

Since 2010, FX has evolved into family of products that address high accuracy timing and variance. Each of the FX Applications solves mission critical problems for chip frequency, yield, and time to market. They complement existing sign-off flows by adding variance information (e.g. derates) or addressing critical gaps in the flow (critical path timing waivers).

In 2013, Variance FX was introduced to extend CLKDA’s derate analysis. In addition to AOCV, Variance FX supports POCV, SOCV, and Liberty Variance Format. It generates delay and slew variance information, as well as variance models for timing constraints (set up and hold uncertainty). Macro FX was introduced in 2014. Macro FX extends Variance FX for complex functions such as flop trays, retention flops and other large custom cells.

Path FX was introduced along with AOCV FX. Path FX delivers Monte Carlo SPICE accurate timing with the ease of use and performance of a general purpose, static timing analyzer. Path FX can run tens of thousands of paths in minutes with MC SPICE accuracy. In 2013, Clock FX was introduced to address the specific requirements of high analysis clock trees.

CLKDA is extending its product capabilities to address any part of an SoC where digital circuitry could fail due to variance; at the cell, path or full chip level. So if you are designing a chip (or some IP) in an advanced node then you need to worry about variance and preemptively address it.

CLKDA’s website is here.