UCIe (Universal Chiplet Interconnect Express) Wiki

UCIe (Universal Chiplet Interconnect Express) is an open industry standard for die-to-die interconnects that enables high-bandwidth, low-latency, power-efficient communication between chiplets in advanced package architectures. The UCIe specification was launched in March 2022 by the UCIe Consortium, with founding members including Intel, AMD, TSMC, Samsung, Arm, ASE, Google Cloud, Microsoft, and others.

UCIe aims to establish a universal, interoperable ecosystem for chiplet-based designs—similar to how PCIe transformed board-level device communication. By standardizing the physical layer (PHY), protocol stack, software model, and compliance requirements, UCIe allows chiplets designed by different vendors and process nodes to interoperate within a common package.

Why UCIe Matters

As Moore’s Law slows and monolithic SoCs become more costly and complex, the semiconductor industry is shifting toward chiplet architectures—modular silicon blocks that can be manufactured separately, optimized independently, and assembled into a system-in-package (SiP).

Before UCIe, most chiplet integrations relied on proprietary or custom interconnects (e.g., AMD Infinity Fabric, Intel AIB, Nvidia NVLink). These limited interoperability, increased cost, and required tight coordination between die teams.

UCIe addresses these challenges by:

Enabling multi-vendor chiplet ecosystems
Allowing reuse across nodes, fabs, IP, and design houses
Reducing design time, risk, and cost
Supporting integration across heterogeneous compute, memory, I/O, and acceleration

Key Features of UCIe

Feature	Description
Open Standard	Managed by the UCIe Consortium; royalty-free
Die-to-Die Interconnect	High-speed links for short-range intra-package communication
PHY Layer	Support for advanced package integration: organic substrate, silicon interposer, or hybrid bonding
Protocol Layer	Defined transport, flow control, and error handling mechanisms
Software Layer	Compatible with existing PCIe and CXL software stacks
Power Efficiency	Energy-optimized interconnect for mobile, AI, and HPC
Scalability	Supports thousands of interconnect lanes and multi-terabit throughput

UCIe Architecture

UCIe defines a full-stack framework for chiplet communication:

1. Physical Layer (PHY)

Supports multiple integration modes:
- Organic substrate (lower bandwidth, lower cost)
- Silicon interposer (CoWoS®, EMIB)
- Advanced hybrid bonding (e.g., SoIC™)
Supports single-ended and differential signaling
Link widths scale from x4 to x256+ lanes

2. Protocol Layer

Based on a lightweight protocol stack
Includes flow control, lane bonding, error correction
Can transport:
- PCI Express (PCIe)
- Compute Express Link (CXL)
- Custom protocols

3. Software Layer

Designed to be transparent to software
Compatible with existing driver stacks
Enables plug-and-play chiplet interoperability

UCIe Integration Modes

Mode	Packaging Type	Data Rate	Use Cases
Standard UCIe	Organic substrate	~16-32 Gbps/lane	Cost-effective integration
Advanced UCIe	Interposer or hybrid bonding	Up to 64+ Gbps/lane	High-performance chiplets

Each mode trades off performance, cost, and complexity depending on application needs.

UCIe Use Cases

AI and Machine Learning Accelerators
HPC processors with chiplet-based architectures
Heterogeneous compute: CPU + GPU + NPU
Disaggregated memory systems
CXL-based memory expansion
Modular SoCs for automotive and edge

UCIe vs. Other Technologies

Interconnect	Type	Vendor	Open Standard	Interop
UCIe	Die-to-die	Consortium	✅ Yes	✅ Yes
AIB	Die-to-die	Intel	❌ No	❌ No
Infinity Fabric	Die-to-die	AMD	❌ No	❌ No
NVLink	Board-level & package	Nvidia	❌ No	❌ No
PCIe	Board-level	PCI-SIG	✅ Yes	✅ Yes
CXL	Board-level	CXL Consortium	✅ Yes	✅ Yes

UCIe is the first open standard to enable true chiplet interoperability across vendors and ecosystems.

UCIe Consortium

Formed in 2022, the UCIe Consortium oversees the evolution, adoption, and compliance of the standard. Its membership spans across:

Foundries: TSMC, Intel, Samsung
IP providers: Arm, Synopsys
System integrators: AMD, Nvidia, MediaTek
Cloud/AI players: Microsoft, Google Cloud, Meta
Packaging houses: ASE, Amkor
EDA vendors: Cadence, Synopsys, Siemens

The consortium released:

UCIe 1.0 in March 2022
UCIe 1.1 in 2023, with enhanced support for multiple protocol tunnels
Future versions will support chiplet discovery, security, and energy-aware routing