AMBA is a set of interconnect protocols for communication among various blocks or IPs in a SoC (System on Chip). ARM introduced AMBA in 1996. The specifications are freely available from ARM that sets standard for on chip communication. The communications are based on Master-Slave protocol.
A typical SoC that goes into mobile phones contains several components like CPU, GPU, Memories, Power Management, Audio, Video, DSP and Controllers integrated into a single chip. AMBA standard enables efficient communication among these components. It facilitates right-first-time design development, modular design, reusability, compatibility and scalability of an IP. This reduces time-to-market and costly re-designs. Comprehensive set of ready to use synthesizable AMBA IP solutions are available from various IP vendors like Synopsys and ARM. Flexible and configurable Verification IP (VIP) solutions are effective and efficient for comprehensive functional verification. The Synopsys VC AutoTestbench solution enables easy and quick integration and configuration of hundreds of coherent and non-coherent AMBA ports and corresponding VIP instances.
AMBA has evolved since 1996 and is currently in its 5th generation. APB (Advanced Peripheral Bus) and ASB (Advanced System Bus) were the first of AMBA bus protocols. AMBA 2 version in 1999 introduced AHB (Advanced High-Performance Bus). AMBA 3 was introduced in 2003 that included AXI (Advanced eXtensible Interface). AMBA 4 introduced ACE (AXI Coherency Extensions) protocol in 2010 and AMBA 5 introduced CHI (Coherent Hub Interface) in 2013.
APB is low bandwidth protocol optimized for low power and low complexity to support peripherals. It is used as low-cost interface to peripherals, which do not require high-performance of pipelined bus interface. Any transfer takes at least 2 cycles. A typical APB system has APB bridge which interfaces with the AHB, AXI or ASB and peripherals which are the slaves. It can be used to access programmable registers of the peripheral devices.
ASB supports features for high-performance systems like burst transfers, pipelined transfer operation and multiple bus masters. It supports connection of many processors and memories. ASB bus consists of Master, Slave, Arbiter and Decoder. Only one master can access the bus at any time with the help of arbiter. Master initiates the read and write operations and slave responds to the read and write requests. Address and appropriate slave are selected using decoder.
AHB is the specifically designed for high-performance designs. It supports multiple bus masters and supports high bandwidth operations. A typical AMBA system design contains AHB master, AHB slave, AHB arbiter and AHB decoder. It is used to connect components like DMA, DSP and Memory that require high bandwidth on a shared bus.
AMBA AHB supports features required by high bandwidth and high frequency designs:
- Burst transfers
- Split Transactions
- Wider data bus configurations (64/128 bits)
- Single-clock edge operation
- Single-cycle bus master handover
AXI is a point-to-point interconnect protocol that overcomes limitations of shared bus protocols. It targets high-performance and high-frequency systems with key features as:
- Multiple outstanding transactions
- Out-of-order data completion
- Burst-based transactions with only start address issued
- Support for unaligned data transfers using strobes
- Simultaneous read and write transactions
- Pipelined interconnects for high speed operation
ACE protocol extends the AXI4 protocol along with hardware-coherent caches. ACE coherency protocol ensures all the masters see correct data for any address location. This avoids software cache maintenance to main coherency between caches. ACE also provides barrier transactions that guarantee ordering of multiple transactions within a system and Distributed Virtual Memory (DVM) functionality to manage virtual memory.
CHI protocol defines interfaces for connection of fully coherent processors. It is a packet based layered communication protocol with Protocol, Link and Network layer. It is topology independent and provides Quality of Service (QoS) based mechanism to control resources in the system. It supports high-frequency and non-blocking coherent data transfers between processors that provides performance and scale for applications like data center.
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