RISC-V Wiki

RISC-V (pronounced “risk-five”) is an open standard instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles. Unlike proprietary ISAs such as x86 or Arm, RISC-V is openly specified and freely available, allowing anyone to design, manufacture, and commercialize RISC-V processors without licensing fees or royalties.

RISC-V is rapidly emerging as a major force in the semiconductor industry, with adoption across AI, automotive, edge, embedded systems, consumer electronics, and even supercomputers. It has become a strategic alternative in a market traditionally dominated by Intel (x86) and Arm.

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Overview

• ISA Type: Load-store, RISC

• Word Sizes: 32-bit, 64-bit, 128-bit

• License: Open and royalty-free

• Standardized by: RISC-V International (nonprofit governing body)

• First released: 2010 (University of California, Berkeley)

RISC-V provides a modular ISA, allowing users to implement only the functionality they need—such as integer-only cores for embedded systems or vector processors for HPC.

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History and Development

Origins at UC Berkeley

RISC-V was developed in 2010 by researchers at the University of California, Berkeley, including Krste Asanović, David Patterson, and others. It was designed as a teaching ISA that could be implemented in academic and industry settings without legal encumbrances.

Key motivations included:

• Avoiding proprietary ISAs (x86, Arm, MIPS) that were closed or expensive

• Creating a clean, modular RISC ISA for modern design needs

• Promoting open innovation and reproducible research

Open-Source Philosophy

Unlike past ISAs, RISC-V is fully open-source in its specification. Anyone can:

• Build their own RISC-V core

• Contribute to the evolving standard

• Use and modify implementations without IP restrictions

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Key Features

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ISA Architecture

Base ISAs

• RV32I – 32-bit base ISA

• RV64I – 64-bit base ISA

• RV128I – 128-bit base (less commonly implemented)

Standard Extensions

• M – Integer multiplication and division

• A – Atomic instructions

• F/D – Single/Double-precision floating point

• C – Compressed instructions (16-bit)

• V – Vector extension (for SIMD, AI, HPC)

• H – Hypervisor support

• S/U – Supervisor and User privilege levels

• Zk – Cryptographic extensions (Zk*, Zkn, Zks, etc.)

Custom Extensions

• Designers can add custom instructions (X-extension) without conflict with standard ISA rules.

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Governance: RISC-V International

Formed in 2020, RISC-V International is a nonprofit organization based in Switzerland, responsible for managing the ISA and ensuring open development.

Members include:

• Founding and Premier Members: Google, Intel, Qualcomm, NVIDIA, SiFive, Andes, Alibaba, Huawei, Samsung, and more

• Over 3,000 members globally

• Technical Working Groups (TWGs) oversee specific ISA extensions and specs

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Hardware Implementations

RISC-V processors are available from commercial vendors, startups, and open-source projects:

Notable Cores

Open-Source Cores

• Rocket (Berkeley)

• BOOM (Out-of-order)

• CV32E40P (formerly PULP RI5CY)

• OpenHW Group projects (CORE-V)

• Shakti (India)

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Software Ecosystem

RISC-V benefits from a rapidly growing open-source software stack:

• Toolchains: GCC, LLVM/Clang, Binutils

• Operating Systems:

  • Linux (including Debian, Fedora, OpenSUSE)

  • RTOSes: Zephyr, FreeRTOS, RIOT

• Virtualization: QEMU, KVM

• Debugging: GDB, OpenOCD

• Security: Trusted Firmware, Keystone (TEE), OpenTitan

• Compilers and Runtimes: Rust, Go, Java, Python (Micropython)

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Use Cases and Applications

RISC-V is being adopted across a wide range of industries:

Embedded and IoT

• Microcontrollers, sensors, smart home, wearables

• Ultra-low power and cost-efficient cores

Automotive

• ADAS, ECUs, in-cabin systems, safety MCUs

• Functional safety (ASIL-D), real-time control

AI and Machine Learning

• AI accelerators and dataflow architectures using RISC-V control cores and vector extensions

Data Centers and HPC

• RISC-V-based servers and accelerators (Esperanto, Ventana, Tenstorrent)

• Custom chiplets for AI and cloud

Consumer Electronics

• Smart TVs, audio, media processors

• Often used for real-time subsystems or control cores

National Sovereignty / Strategic Computing

• Countries like India, China, Russia, and the EU promote RISC-V for technology independence

• Open architecture reduces reliance on foreign IP and export restrictions

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Challenges and Limitations

Despite rapid growth, RISC-V still faces key challenges:

• Software Maturity: While improving, still behind Arm/x86 for commercial-grade SDKs, drivers, and middleware

• Ecosystem Fragmentation: Multiple vendors with diverse implementations and extensions

• Performance Leadership: Lags behind Apple, AMD, Intel in peak performance cores

• Toolchain Optimization: Needs more investment in compilers, debuggers, and profiling tools

However, these are actively being addressed through community and corporate investment.

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Strategic Impact

RISC-V is increasingly viewed as a strategic asset in the global technology landscape:

• Supports innovation at all levels (academia, startups, national labs)

• Enables chiplet-based design, custom SoCs, and heterogeneous compute

• Undermines closed ISA monopolies, encouraging competition and choice

Governments and large corporations are embracing RISC-V as part of industrial policy and supply chain resilience strategies.

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Future Outlook

RISC-V is expected to:

• Achieve performance parity with leading proprietary cores in the next 3–5 years

• Become the de facto standard for embedded and configurable processors

• Enable democratized hardware innovation via open-source silicon

Emerging areas include:

• High-performance compute clusters

• Secure enclaves and TEE

• High-NA EUV-ready chiplets

• AI/ML accelerators

• Quantum control systems

 

Company Website

RISC-V on SemiWiki

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