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Semiconductor Expert Forum

Podcast EP188: The New Demands for Memory Design and the Synopsys Approach with Anand Thiruvengadam

Podcast EP188: The New Demands for Memory Design and the Synopsys Approach with Anand Thiruvengadam
by Daniel Nenni on 10-20-2023 at 10:00 am

Dan is joined by Anand Thiruvengadam, director of product and business management and head of the Solutions and Go-to-Market functions for the memory market segment at Synopsys.

Anand discusses the substantial demands experienced by memory designers due to trends such as big data analytics. He describes how these demands impact the design flow both during the design phase as well as after tapeout, creating a full silicon lifecycle management requirement, New effects that must be modeled such as aging and radiation are also discussed.

Against this backdrop Anand outlines the full-stack approach Synopsys has taken to address these design challenges. The company-wide focus on memory design as well as the addition of new AI techniques are presented.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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ASML- Longer Deeper Downcycle finally hits lithography – Flat 2024 – Weak Memory – Bottom?

ASML- Longer Deeper Downcycle finally hits lithography – Flat 2024 – Weak Memory – Bottom?
by Robert Maire on 10-20-2023 at 8:00 am
Categories: Lithography, Semiconductor Advisors, Semiconductor Services
1 Comment

ASML Monopoly
  • ASML reports in-line QTR but future looks flat for 2024
  • Downcycle finally hits litho leader- ASML monopoly solid as ever
  • Memory remains bleak – New China sanctions unclear
  • Recovery timing is unclear but planning for an up 2025
In Line Quarter and year as expected

Overall revenues came in at Euro6.7B with EPS at Euro4.81, more or less in line with guidance and expectations. The company appears on track for its previously guided 30% growth in 2023 over 2022.

The obvious issue was that orders were down (-42%) significantly to Euro 2.6B with only Euro0.5B in EUV bookings which suggest weakness at leading edge and sustaining business at trailing technology.

Overall the company is looking at a flat 2024 over 2023……..

Length & Depth of downturn confirmed as it finally hits ASML

In the many years we have followed the semiconductor industry, it has always been the case that lithography tools were the last to be canceled/slowed while most other tools saw an immediate impact.

If the current downcycle were a year or less or limited to just the memory sector, its likely that ASML would have skated over the downcycle without impact while others got hit.

The length and depth of the current downturn is much deeper and longer than most previous cycles and thus has finally caught up with ASML. Customers are obviously less concerned about canceling and delaying orders as they are getting off the order queue that usually lasts well over a year. They are likely more confident that they will be able to get the tools whenever the recovery actually recovers.

This also seems to suggest that the recovery cycle will be longer and slower than prior recoveries otherwise customers would want to have equipment to be ready, and wouldn’t slow ASML orders.

A three or four year downcycle?

The downcycle started in the spring of 2022. If we assume that we are coming close to a bottom at the end of 2023 (as ASML suggests) we have spent the last year and nine months on the way down to the bottom.

If we assume a slow recovery (which already seems indicated) we won’t see a recovery back to prior levels until some time in 2025 (at best).

That would peg the current downcycle at 3 to 4 years making it one of the worst overall.

We were more negative than most every analyst going into the downturn and unfortunately we have been proven correct at the length and depth even though we had hoped to be wrong.

Monopoly remains solid

Despite recent hysteria and bad information there is no threat to ASML’s position on the horizon whatsoever.

The primary threat remains market health and demand. Sanctions are a secondary threat but less impactful than demand related issues.

China sanctions initially sound less impactful

Although ASML is still reading recently released sanctions from the US to figure out the impact, it appears at first blush that the impact is less than what could have otherwise been.

It looks like enough ARFi tools will be shipped into China to help out ASML’s revenues while “bad actors” in China will still be on the “verboten” list.

Final export licenses and approvals remain to be seen but so far “draconian” sanctions appear to be off the table.

Looks like Gina took the slap in the face and didn’t respond as much as could have been, showing restraint. Maybe Biden wants to have a better meeting with Xi.

High NA likely to be a bright spot in 2024

The roll out of High NA tools at the end of 2023 and going into 2024 is likely to be a significant portion of business and new orders when the industry does actually start to recover probably in 2025.

Importantly the company has not cut back on R&D or leading technology efforts as it represents the future of the company.

We think orders and revenues on High NA tools will be one of the things that elevates ASML out of the downturn faster than others in the industry.

At $400M or so a pop, it doesn’t take a lot of orders to add up to real money.

Timing of CHIPS Act & fab construction just sucks

Unfortunately the last thing you want to do in an oversupply based downcycle is build more capacity……

The CHIPS act aims to do just that…..All the new fabs announced in the US, if brought on line in the previously expected timeline would tank the industry again.

Its quite clear that delays TSMC Arizona, Intel and others are more due to the current oversupply/downcycle than any other issue.

We would expect at least a 2-3 year delay if not more, of many of these projects. Chip companies are simply not stupid enough to spend money on new capacity when they are already swimming in it.

This is obviously unfortunate as it delays the US reshoring effort and dependence on Asia remains without a reasonable solution…..

The Stock

As expected, a longer cycle that has impacted ASML’s 2024 will weigh down the stock as no growth in 2024 over 2023 is clearly disappointing.

However, the longer term remains strong. ASML’s position remains strong. Not much has changed about the overall dynamics of the semiconductor industry.

We do see collateral damage to other chip equipment stocks as the length of the downcycle impacts others more so than ASML.

We will likely hear more of that through the rest of earnings season….

Most other chip equipment makers will likely try to put a good face on it but the reality is that this is a longer than expected and worse downturn.

When even ASML catches a cold the rest of the equipment makers catch pneumonia….

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specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies.
We have been covering the space longer and been involved with more transactions than any other financial professional in the space.
We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors.
We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

ASML- Absolutely Solid Monopoly in Lithography- Ignoring hysteria & stupidity

SPIE- EUV & Photomask conference- Anticipating high NA- Mask Size Matters- China

Micron Chip & Memory Down Cycle – It Ain’t Over Til it’s Over Maybe Longer and Deeper

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CEO Interview: Pat Brockett of Celera

CEO Interview: Pat Brockett of Celera
by Daniel Nenni on 10-20-2023 at 6:00 am
Categories: CEO Interviews

Pat Brockett

Pat Brockett is a veteran of the global semiconductor industry. He began his career in sales and marketing at Texas Instruments. After that, he was senior vice president of worldwide sales and marketing at National Semiconductor. Subsequently, he headed the analog division and is credited with turning it around.

Later, he was CEO of the venture-backed programmable analog startup, Summit Microelectronics. The company led the mobile industry for ultra-fast battery charging and was purchased by Qualcomm for $350M.

Pat has been a board member and advisor to companies such as SureCall and Moonshot Antibodies.  For the past four years he was also an advisor to Celera. Pat recently stepped into the CEO role at the company and hired Alberto Viviani, another analog semiconductor veteran as COO.

Tell us about your company
Celera is disrupting the analog IC business. Analog design automation really doesn’t exist. For example, it takes at least a year to get a custom analog chip to market. Celera combines proprietary AI algorithms with decades of analog design experience to deliver custom chips in four months or less. Celera also has a world-class supply chain ensuring our customers are delivered the highest quality, cost-competitive product.

What problems are you solving?
Digital chip design has seen an incredible improvement in automation and overall design productivity over the past 20 years. Sophisticated automation takes care of a lot of chip implementation. AI is accelerating the process even further, with generative AI approaches promising to take digital chip design to new levels of automation.

Analog chip design, on the other hand, is done today about the same way it was done 20 years ago. It’s a very manual process, requiring deep domain expertise at every step to ensure a successful result. This situation creates several significant hurdles. Systems are using many more sensors and high-speed communication networks than ever before. These additions drive up the analog content of the system. At the same time, the expert analog designers we have come to rely on are aging out and there are few newly minted analog design experts to backfill them.

It is against this “perfect storm” that Celera was born. Most of the members of the company worked together for decades doing analog chips. This team got tired of the labor-intensive nature of the process and decided to find a better way. That better way is Celera and its patented, AI-assisted algorithmic design flow. This is a fundamentally new approach to analog chip design that will finally break the log jam and make custom analog chips available to all.

What application areas are your strongest?
The Celera approach to analog and mixed signal design can be applied to many design problems. To kick off the process and introduce this revolutionary technology to the market, Celera is already delivering custom power management integrated circuits (PMICs).

What keeps your customers up at night?
It depends on the type of customer. For chip companies, the challenge is getting many products to market fast. Since the design process is manual and is dependent on scarce analog designer resources, the pace of product introduction is often slower than ideal.

Large OEMs have the resources to build their own custom analog chips, but these designs can take longer than the digital part of the system. So, analog design becomes the “long pole” in product development, and this can result in lost revenue due to a late product introduction.

Small to mid-size OEMs have a different problem. These companies simply don’t have the resources to build custom analog chips. Rather, they use off-the-shelf parts integrated on complex circuit boards. The result is a suboptimal form factor, power dissipation and cost.

What does the competitive landscape look like and how do you differentiate?
The existing landscape consists of captive analog design groups inside of large system OEMs and analog design teams at chip and ASIC suppliers.

Celera has a team that is at least equal to our competition. What differentiates Celera from every other analog chip company is our AI-driven technology which reduces design time from many months to a few weeks.

Celera’s approach will disrupt the analog chip industry.

What new features/technology are you working on?
The current Celera model is to use our patented technology with our experienced design team to deliver custom analog chips faster and more reliably than ever before.

The ultimate goal of the company is to release our patented design approach via the cloud to make custom analog chips available to all. Called ChipHUB, this technology will allow system designers to specify what kind of custom analog chip they need without the need to know how to design it. That task will be done by ChipHUB.

How do customers normally engage with your company?
You can reach out to us via our website here. We’ll take it from there.

Also Read:

CEO Interview: Islam Nashaat of Master Micro

CEO Interview: Sanjeev Kumar – Co-Founder & Mentor of Logic Fruit Technologies

CEO Interview: Stephen Rothrock of ATREG

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The Path to Chiplet Architecture

The Path to Chiplet Architecture
by Paul McLellan on 10-19-2023 at 10:00 am
Categories: Chiplet, EDA, Siemens EDA

The Path to Chiplet Architecture

If you have anything to do with the semiconductor industry, you already know that one of the hottest areas for both manufacturing and EDA are systems designed with advanced packaging, basically putting more than one die (aka chiplets) in the same package.

When 3D packaging was first introduced, there were not really any effective design tools. Obviously, each chiplet could be designed the same way as a chip would be, but it was not really possible to examine the entire design as a single system. But people managed to successfully product working designs.

Early in technology development, optimizing the pin layout for power, performance, and area take priority. High pin count ASICs/FPGAs get broken down into smaller blocks (IOs, Complex IPs, Cores, AMS blocks etc.) that are instanced many times and are integrated to form the complete floorplan of the ASIC/FPGA or chiplet. This is not only the case for ICs, but also for interposers and package substrates.

Xpedition Substrate Integrator

As designs get larger, doing all this by hand becomes less and less feasible. This is where Siemens EDA comes in with the Xpedition Substrate Integrator (xSI) IC package floor-planning and assembly tool for the design phase, and the Calibre 3DSTACK and nmDRC tools for verification.

The chiplets in a chiplet-based design have many constraints at this floorplan level. Obviously, the bumps on the chiplet need to align physically with the interposer (or interconnect bridge). Signals that leave one chiplet need to go somewhere, such as to another chiplet or out to the actual package pins, typically by way of solder balls. Clearly, this provides plenty of ways to potentially mess up.

Power Delivery Network

One specific challenge in a chiplet-based design is the power delivery network (PDN). Given that the voltage may be, say, 0.8V and the power of the system might be measured in hundreds of watts, the current involved can be hundreds of amps. Since there may be 100,000 bumps or more to carry this high current, the only practical approach is to parameterize things. Nobody is going to place 100,000 bumps by hand.

As a recent white paper from Siemens EDA, The smart path to chiplets using hierarchical device planning and pin regions, explains:

The primary power/ground domain is surprisingly simple. The region will have a specific pin pattern, pad stack definition, and a repeating signal assignment pattern (checkerboard or horizontal/vertical striped). A highly efficient way to represent this design structure is as a set of parameterized pin regions.

The white paper goes into a lot of detail on how this is accomplished, along with an example design.

Physical Design

Next is to take the soft design and rearchitect into actual chiplets. The design (shown above) is The Soft IP SoC bump interface generated using parameterized pin regions containing 112,029 pins with eight power/ground domains and supporting 4-HBM interfaces.

When a design is constructed using hierarchical building blocks to represent the die-to-die interfaces along with parameterized pins to represent power distribution networks and signal patterns, the path to rearchitecting the SoC into chiplets is clear. Starting with the soft IP SoC representation, after the pins are removed, the region geometries can be quickly modified into a chiplet configuration as shown below.

With a few more steps detailed in the white paper, here is the final design complete with the HBM (high-bandwidth memory) stacks:

Summary

Package designers need to employ all the available tools to address the significant device complexity and explosion in pin count in today’s IC packaging designs, especially when early design analysis clearly detects errors. While it may still be possible to generate an initial draft of an advanced IC package design using non-graphical IC package floor-planning flows, it simply would not be feasible to keep up with the changes required by early design analysis. Siemens EDA has a portfolio of design tools that work together to deliver a correct design.

Please download the full white paper, The smart path to chiplets using hierarchical device planning and pin regions, in which a real example of a multi-die HBM-based design is used to show how package designs of complex chiplet-based designs can be created quickly and efficiently, without errors. Perhaps more importantly, iterative updates can be done in mere minutes or even seconds because of effective use of hierarchy in the design.

Also Read:

Placement and Clocks for HPC

AI for the design of Custom, Analog Mixed-Signal ICs

Optimizing Shift-Left Physical Verification Flows with Calibre

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IEDM 2023 is Coming in December

IEDM 2023 is Coming in December
by Scotten Jones on 10-19-2023 at 6:00 am
Categories: Events

IEDM 2023

Anyone who has read my previous IEDM articles will know I view it as one of the best conferences on semiconductor process technology. From the tutorials, short courses and the conference papers there are so many great opportunities to keep up to date on the latest developments. The following are the conference organizers’ announcements on the conference.

The 69th annual edition of the IEEE International Electron Devices Meeting (IEDM) will be held in San Francisco on Dec. 9-13.  The news release below our names gives details of the conference program, and here’s a list of some of the anticipated technical highlights.

2023 IEEE International Electron Devices Meeting to Highlight Advances in Critical Semiconductor Technologies with the Theme, “Devices for a Smart World Built Upon 60 Years of CMOS”

  • Four Focus Sessions on topics of intense research interest:
  • 3D Stacking for Next-Generation Logic & Memory by Wafer Bonding and Related Technologies
  • Logic, Package and System Technologies for Future Generative AI
  • Neuromorphic Computing for Smart Sensors
  • Sustainability in Semiconductor Device Technology and Manufacturing

SAN FRANCISCO, CA (October 2, 2023) – Since it began in 1955, the IEEE International Electron Devices Meeting (IEDM) has been where the world’s best and brightest electronics technologists go to learn about the latest breakthroughs in semiconductor and related technologies. That tradition continues this year, when the 69th annual IEEE IEDM conference takes place in-person December 9-13, 2023 at the Hilton San Francisco Union Square hotel, with online access to recorded content available afterward.

The 2023 IEDM technical program, supporting the theme, “Devices for a Smart World Built Upon 60 Years of CMOS,” will consist of more than 225 presentations plus a full slate of panels, Focus Sessions, Tutorials, Short Courses, a career luncheon, supplier exhibit and IEEE/EDS award presentations.

“The IEDM offers valuable insights into where the industry is headed, because the leading-edge work presented at the conference showcases major trends and paradigm shifts in key semiconductor technologies,” said Jungwoo Joh, IEDM 2023 Publicity Chair and Process Development Manager at Texas Instruments. “For example, this year many papers discuss ways to stack devices in 3D configurations. This is of course not new, but two things are especially noteworthy about this work. One is that it isn’t just happening with conventional logic and memory devices, but with sensors, power, neuromorphic and other devices as well. Also, many papers don’t describe futuristic laboratory studies, but rather specific hardware demonstrations that have generated solid results, opening pathways to commercial feasibility.”

“Finding the right materials and device configurations to develop transistors that will perform well with acceptable levels of reliability remains a key challenge,” said Kang-ill Seo, IEDM 2023 Publicity Vice Chair and Vice President, Semiconductor R&D, Samsung Semiconductor. “This year’s program shows that electrothermal considerations remain a key focus, particularly with attempts to add functionality to a chip’s interconnect, or wiring, which is fabricated using low-temperature processes.”

Here are details of the 2023 IEEE International Electron Devices Meeting:

Tutorial Sessions – Saturday, Dec. 9

The Saturday tutorial sessions on emerging technologies are presented by experts in the field to bridge the gap between textbook-level knowledge and leading-edge current research, and to introduce attendees to new fields of interest. There are three time slots, each with two tutorials running in parallel:

1:30 p.m. – 2:50 p.m.

  • Innovative Technology for Beyond 2 nm, Matthew Metz, Intel
  • CMOS+X: Functional Augmentation of CMOS for Next-Generation Electronics, Sayeef Salahuddin, UC-Berkeley

3:05 p.m. – 4:25 p.m.

  • Reliability Challenges of Emerging FET Devices, Jacopo Franco, Imec
  • Advanced Packaging and Heterogeneous Integration – Past, Present & Future, Madhavan Swaminathan, Penn State

4:40 p.m. – 6:00 p.m.

  • Synapses, Circuits, and Architectures for Analog In-Memory Computing-Based Deep Neural Network Inference Hardware Acceleration, Irem Boybat, IBM
  • Tools for Device Modeling: From SPICE to Scientific Machine Learning, Keno Fischer, JuliaHub

Short Courses – Sunday, Dec. 10

In contrast to the Tutorials, the full-day Short Courses are focused on a single technical topic. They offer the opportunity to learn about important areas and developments, and to network with global experts.

  • Transistor, Interconnect, and Chiplets for Next-Generation Low-Power & High-Performance Computing, organized by Yuri Y. Masuoka, Samsung
  • Advanced Technology Requirement for Edge Computing, Jie Deng, Qualcomm
  • Process Technology toward 1nm and Beyond, Tomonari Yamamoto, Tokyo Electron
  • Empowering Platform Technology with Future Semiconductor Device Innovation, Jaehun Jeong, Samsung
  • Future Power Delivery Process Architectures and Their Capability and Impact on Interconnect Scaling, Kevin Fischer, Intel
  • DTCO/STCO in the Era of Vertical Integration, YK Chong, ARM
  • Low Power SOC Design Trends/3D Integration/Packaging for Mobile Applications, Milind Shah, Google

 

  • The Future of Memory Technologies for High-Performance Memory and Computing, organized by Ki Il Moon, SK Hynix
  • High-Density and High-Performance Technologies for Future Memory, Koji Sakui, Unisantis Electronics Singapore/Tokyo Institute of Technology
  • Advanced Packaging Solutions for High Performance Memory and Compute, Jaesik Lee, SK Hynix
  • Analog In-Memory Computing for Deep Learning Inference, Abu Sebastian, IBM
  • The Next Generation of AI Architectures: The Role of Advanced Packaging Technologies in Enabling Heterogeneous Chiplets, Raja Swaminathan, AMD
  • Key Challenges and Directional Path of Memory Technology for AI and High-Performance Computing, Keith Kim, NVIDIA
  • Charge-Trapping Memories: From the Fundamental Device Physics to 3D Memory Architectures (3D NAND, 3D NOR, 3D DRAM) and Computing in Memory (CIM), Hang-Ting (Oliver) Lue, Macronix

Plenary Presentations – Monday, Dec. 11

  • Redefining Innovation: A Journey forward in the New Dimension Era, Siyoung Choi, President & GM, Samsung Foundry Business, Device Solutions Division
  • The Next Big Thing: Making Memory Magic and the Economics Beyond Moore’s Law, Thy Tran, Vice President of Global Frontend Procurement, Micron
  • Semiconductor Challenges in the 5G and 6G Technology Platforms, Björn Ekelund, Corporate Research Director, Ericsson

Evening Panel Session – Tuesday evening, Dec. 12

The IEDM evening panel session is an interactive forum where experts give their views on important industry topics, and audience participation is encouraged to foster an open exchange of ideas. This year’s panel will be moderated by Dan Hutcheson, Vice Chair at Tech Insights.

  • AI: Semiconductor Catalyst? Or Disrupter? Artificial Intelligence (AI) has long been a hot topic. In 2023 it became super-heated when large language models became readily available to the public. This year’s IEDM will not rehash what’s been dragged through media. Instead, it will bring together industry experts to have a conversation about how AI is changing the semiconductor industry and to ask them how they are using AI to transform their efforts. The topics will be wide-ranging, from how AI will drive demand for semiconductors, to how it’s changing design and manufacturing, and even to how it will change the jobs and careers of those working in it.

Luncheon – Tuesday, Dec. 12

There will be a career-focused luncheon featuring industry and scientific leaders talking about their personal experiences in the context of career growth. The discussion will be moderated by Jennifer Zhao,

President/CEO, asm OSRAM USA Inc. The speakers will be:

  • Ilesanmi Adesida, University Provost and Acting President, Nazarbayev University, Kazakhstan — Professor Ilesanmi Adesida is a scientist/engineer and an experienced administrator in both scientific and educational circles, with more than 350 peer-reviewed articles/250 presentations at international conferences.
  • Isabelle Ferain, Vice-President of Technology Development, GlobalFoundries — Dr. Ferain oversees GF’s technology development mission in its 300mm fabs in the US and Europe.

Vendor Exhibition/MRAM Poster Session/MRAM Global Innovation Forum

  • A vendor exhibition will be held once again.
  • A special poster session dedicated to MRAM (magnetoresistive RAM memory) will take place during the IEDM on Tuesday, Dec. 12 from 2:20 pm to 5:30 p.m., sponsored by the IEEE Magnetics Society.
  • Also sponsored by the IEEE Magnetics Society, the 15th MRAM Global Innovation Forum will be held in the same venue after the IEDM conference concludes, on Thursday, Dec. 14.

For registration and other information, visit www.ieee-iedm.org.

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McKinsey & Company Shines a Light on Domain Specific Architectures

The True Power of the TSMC Ecosystem!

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An Update on IP-XACT standard 2022

An Update on IP-XACT standard 2022
by Daniel Payne on 10-18-2023 at 10:00 am
Categories: Agnisys, EDA

IP XACT 2022 min

Semiconductor IP design re-use has enabled the relentless growth in complexity of SoC and chiplet-based systems over the years, and with IP reuse comes many unique challenges.  Fabless design companies use IP provided by a vibrant ecosystem of IP suppliers and foundries, plus internal re-use in the quest to get to market more quickly than starting from a blank slate. Standards organizations Accellera and the IEEE have addressed the challenges of IP design re-use through the IP-XACT standard, dating all the way back to 2004 when IP-XACT 1.0 was released. The latest standard is IEEE 1685-2022, so that’s 18 years of progress and history for IP reuse.

There’s a webinar hosted by Agnisys on October 25th that brings us up to speed on IP-XACT 2022, and the presenter is Devender Pal Khari, a member of the Accellera IP-XACT Working Group. The IP-XACT standard defines how files in XML format describe an IP block so that EDA tools and automated flows can quickly understand essentials, like:

  • Ports
  • Bus Interfaces
  • Registers
  • Memory elements
  • Connections
  • Parameters
  • Hierarchy
    Source: IP-XACT Tutorial by Accellera at DV Con US 2023

    The benefits of using a standard like IP-XACT are that it represents a single specification for all IP information, a single way for registers to be defined, and all needed representations can be generated from a single source using an automated workflow.

    New for IP-XACT 2022

The webinar goes into technical detail of all the latest updates to the specification, along with reasons for the changes. The conditional element isPresent has been removed, yet for backward compatibility it is supported through Accellera Vendor Extensions.

Examples are presented on typeDefinitions for memory maps – memoryMapDefinition and memory MapDefinitionRef. They also show how the Tight Generator Interface (TGI) is used to communicate between the design environment and generators.

Power domains used in the Unified Power Format (UPF) are shown with the element componentInstances. Power constraints are support with elements named powerConstraint and powerDomainRef.

User-defined modes are now supported to allow for conditions in dynamic configurations. These modes are then referenced in memory elements, ports, power domains and interfaces. Examples are shown for modes defined on a port, and power domains linked based on modes.

Summary

Agnisys has been focused on EDA automation for HW/SW interfaces since 2007, and are active members of the IP-XACT working group, so they have the expertise to assist SoC designers in using methodologies that support IP reuse.

The webinar from Agnisys on IP-XACT 2022 is October 25th, from 9AM to 9:45AM PDT, and registration is online. Engineers using IP-XACT will benefit from the examples showing what has changed in the latest release, then begin to update their methodology. This is a technical webinar for engineers to further their skills and understanding.

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Analog Bits Leads the Way at TSMC OIP with High-Accuracy Sensors

Analog Bits Leads the Way at TSMC OIP with High-Accuracy Sensors
by Mike Gianfagna on 10-18-2023 at 6:00 am
Categories: Analog Bits, Events, Foundries, IP, TSMC

Analog Bits Leads the Way at TSMC OIP with High Accuracy Sensors

The 15th TSMC Open Innovation Platform® (OIP) event was held recently. This event is a focal point across the industry for cutting-edge development and industry-level collaboration. Appropriately, advanced packaging, paving the way for multi-die design was a focal point for the event. You can get a good overview of what was happening at OIP here. Beyond fab and packaging, there was a lot of talk about end markets, with automotive being a key growth area.  This is where I’d like to focus in this post – with another example of Analog Bits leadership in automotive grade sensors. Read on to see how Analog Bits leads the way at TSMC OIP with high-accuracy sensors.

Why It’s Important

According to recently published market research, the global automotive sensor market was worth $30.9 B in 2022, and is projected to grow at a CAGR of 7.3% to reach $ 61.4 B from 2023 to 2032. According to the research, “… substantial growth is due to the integration of sensors in vehicles to enhance safety, efficiency, and overall performance. Sensors are used in areas like advanced driver assistance systems (ADAS), engine management, and environmental monitoring. The market’s expansion is driven by regulatory mandates for vehicle safety, the rise of electric and autonomous vehicles, and consumer demand for innovative features.”

The report discussed the need for high-accuracy sensors in automotive designs. Everyone is getting into this market, including:

  • Robert Bosch GmbH
  • Continental AG
  • DENSO Corporation
  • Analog Devices, Inc.
  • Sensata Technologies, Inc.
  • Delphi Automotive PLC
  • Infineon Technologies AG
  • STMicroelectronics

The need for high-accuracy, automotive-grade sensors has become a white-hot item in vehicle design. It is against this backdrop that the work presented by Analog Bits is so important.

What Was Presented at OIP

Analog Bits has been at the forefront of precision analog IP for a long time. At OIP, the company showcased numerous IPs on TSMC’s industry-leading N5A process of its new high accuracy sensor and automotive grade, silicon proven designs at its booth. This development is part of Analog Bits’ broadening portfolio of mixed signal IP in advanced TSMC 3nm, 4nm, and 5nm processes. The company announced that design kits are available now.

Mahesh Tirupattur, executive vice president at Analog Bits weighed in with the following official comments:

“As we work with leading edge automotive customers on advanced FinFET processes, thermal issues continue to be a concern and need for multiple instances of sensors continues. Furthermore, many applications cannot have additional test costs associated with trimming for higher accuracy. We have been working on designs for improving un-trimmed accuracy in FinFETs and reducing the area of the sensors, and we are pleased to demonstrate working silicon of these higher accuracy sensors on N5A process at our booth at OIP.”

Mahesh is a force in this industry. You can review his incredible ride at Analog Bits here. Analog Bits has quite a deep technical bench. The president and CTO of Analog Bits, Alan Rogers gave a presentation at OIP about on-die power management IP’s, another very important topic. Let’s look at what Alan presented.

Alan’s Presentation at OIP

Alan Rogers

Alan Rogers has been at Analog Bits for over 25 years, and he’s been working with transistors for over 55 years. In his own words, he’s getting quite good at it. Alan began his presentation with the following introduction:

“In the last 40 years, since my first CMOS chip development in 5u SOS, I’ve watched the power density of silicon chips increase every generation, with higher switching frequencies and larger and larger currents making power integrity a serious design profession. For good reason, the two longest traces on opposite corners of a wire bonded DIP package just don’t seem like a good power delivery solution anymore. How can we help with that?  Glad you asked!”

Alan went on to discuss power management challenges in SoCs and chiplets. He covered topics such as the Analog Bits portfolio of on-die power management IP’s, the benefits of this IP, silicon results on TSMC N3E, and future work. He detailed several high-profile challenges being faced by many designers today. These include:

  • Power integrity and noise
  • Dynamic power management
  • Static voltage drop
  • Heterogeneous integration
  • Leakage power
  • Transient voltage spikes and voltage sags
  • Thermal hazards

He then detailed the various IPs available from Analog Bits to address the above challenges:

  • PVT Sensors – integrated and pin-less
  • Power On Reset and Over Current Detection Macro
  • Power Supply Glitch Detector
  • Power Supply Droop Detector
  • Low Dropout Regulator

The impact of a comprehensive library of IP like this can be substantial. Alan touched on some of that impact, including improved power efficiency, faster transient response and efficient regulation, enhanced reliability and improved yield, voltage scalability, integration and space savings, and noise reduction. Quite a list of improvements.

TSMC N3E Test Chip

He then went on to show several actual silicon results from TSMC’s N3E process. The response of the Droop Detector to a slow power slew was shown as well as the linearity of the system against a programmable input threshold. Results over temperature were presented that illustrated the stability and quality of the design. Performance of the PVT sensor was also shown over multiple conditions. The programmability of the Power On Reset macro was shown in detail as well.

Overall, an impressive portfolio of IP and an impressive set of results on an advanced process.

To Learn More

If you’d like to dig into the array of precision IPs offered by Analog Bits, you can do so here. And that’s how Analog Bits leads the way at TSMC OIP with high-accuracy sensors.

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ASML- Absolutely Solid Monopoly in Lithography- Ignoring hysteria & stupidity

ASML- Absolutely Solid Monopoly in Lithography- Ignoring hysteria & stupidity
by Robert Maire on 10-17-2023 at 8:00 am
Categories: Lithography, Semiconductor Advisors, Semiconductor Services
8 Comments

ASML Monopoly
  • This past weeks over-reaction to Canon echoes the Sculpta Scare
  • Nanoimprint has made huge strides but is still not at all competitive
  • Shows basic lack of understanding of technology by some pundits
  • Chip industry has been searching for alternatives that don’t exist
Much ado about nothing much…..

This past week we saw a huge negative knee jerk reaction in ASML due to the announcement by Canon of a nano imprint tool. Somehow the market and many so called “analysts” got hot and bothered suggesting this would be the end of ASML as we know them. Not many people seemed to do any serious fact checking even a brief analysis prior to writing ASML’s obituary.

Perhaps there is just a natural schadenfreude in the market over companies that have a monopoly along with the associated high valuation. Maybe everyone just wants to see the top dog knocked off their pedestal, just a little bit.

The problem is that its not the case and ASML is as rock solid as ever and Canon will have in essence, zero impact on ASML’s business.

Echoes of the AMAT “Sculpta Scare Stampede Stupidity”

The Canon news was just a carbon copy of the same overreaction to the Applied Sculpta tool which was inappropriately introduced at the SPIE lithography conference even though its nothing more than an etch tool. Applied called it an imaging tool even though it is clearly not at all. People with zero technical understanding suggested that it was the end of double patterning and ASML’s tool sales would be cut in half.

Obviously this is the furthest thing from the truth and Applied was clearly trying to steal some of ASML’s value in the lithography world.

Now more than 6 months after the Scuplta scare it seems most investors have finally figured out it will have zero impact on ASML. Scuplta has not taken the market by storm.

Back when Sculpta was announced many pundits said it was an “existential threat” to ASML….this past week we have heard the same over exaggerated “existential threat” to ASML….NOT!

Much like the Applied Sculpta technology, the Canon technology has also been around for decades and has been struggling as a developing technology.

Nanoimprint has make huge strides but has very basic limitations

Canon got into the nano imprint business by buying Molecular Imprints of Texas in 2014. Molecular Imprints had been struggling for quite a while and never really got any significant traction. There was some early direction of using nano imprint to do surface modification of disk drive platters with micro patterns. Use in the semiconductor industry back then was a far off fantasy limited to repetitive patterns of memory devices.

Defectivity and alignment have been perpetual problems and limitations of nano imprint. We do applaud Canon in making excellent progress, by relentless engineering that Japanese firms are known for, in these and other areas but basic technical limitations still remain.

There could be some potential applications in memory for nano imprint which is more tolerant of defectivity issues than logic and runs at lower resolution but still quite a ways off from being a “real world” HVM (high volume manufacturing) solution.

DSA & multibeam are other “boogeymen” to be aware of

If 6 months from now, some company announces a breakthrough in DSA (directed self assembly) or multiple beam electron beam direct write systems that is touted as an “existential threat” to ASML, just go out and buy ASML’s stock in the face of stupid herd mentality……

DSA has also been around for decades as a lithography alternative with its own set of limitations comparable to nano imprint, being the always wished for alternative to standard lithography.

There is also direct write electron beam technology which while much higher resolution than EUV is millions of times slower, like copying a newspaper with a pencil rather than a printing press of EUV. There are attempts to use massively parallel pencils but obviously its still incredibly slow.

Lots of litho ASML wanna bees exist but nothing is real

As lithography costs go exponential the hope for alternatives grows

Part of the overreaction to non viable litho alternatives is that the cost of litho is growing exponentially and so is ASML’s monopoly.

We attend many industry conferences and keep up to date on the latest trends. We go out of our way and attend conferences that no industry analyst would ever attend let alone even know about such as the recent SPIE Photomask & EUV conference. DSA, nano imprint and other technologies are always discussed at such conferences but anyone serious in the industry knows that there are no viable alternatives anywhere near on the horizon that would impact ASML

There are still hopes and dreams of alternatives that intensify as current litho costs grow faster than any other semiconductor equipment segment.

We are also sure that China is trying harder than anyone else to come up with an alternative to current sanctioned litho tools. If DSA, nano imprint or direct write were viable, they would be doing it.

The Stock

Despite all the uneducated, hysterical, overreaction this past week over a “nothing burger” product announcement, nothing has changed at all for ASML due to the Canon announcement

Far bigger, real and more relevant issues are the global macro economic outlook, over supply in chips, the China sanctions etc; etc.

ASML’s monopoly and market position haven’t changed, the only significant variable remains the market itself.

ASML remains the most dominant player in the semiconductor equipment space by far and is appropriately valued as such.

Canon’s imprint threat is no more real than the monster under the bed….

About Semiconductor Advisors LLC

Semiconductor Advisors is an RIA (a Registered Investment Advisor), specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

SPIE- EUV & Photomask conference- Anticipating high NA- Mask Size Matters- China

Micron Chip & Memory Down Cycle – It Ain’t Over Til it’s Over Maybe Longer and Deeper

Has U.S. already lost Chip war to China? Is Taiwan’s silicon shield a liability?

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Qualcomm Insights into Unreachability Analysis

Qualcomm Insights into Unreachability Analysis
by Bernard Murphy on 10-17-2023 at 6:00 am
Categories: EDA, Synopsys

Unreachability

Unreachability (UNR) analysis, finding and definitively proving that certain states in a design cannot possibly be covered in testing, should be a wildly popular component in all verification plans. When the coverage needle stubbornly refuses to move, where should you focus testing creativity while avoiding provably untestable logic? Seems like a no-brainer to figure this out if you want to reduce effort and schedule, yet UNR still is not as mainstream as you might imagine. A talk by Luv Sampat (Senior Engineer at Qualcomm) showed where the simple UNR premise falls short and shared a path forward at a recent Synopsys VC Formal SIG event.

Context

Unreachability analysis is based on formal technologies, as usual best applied to IP-level tasks in this case to Qualcomm Hexagon DSP cores. In different configurations these cores are used in products from Bluetooth earbuds all the way up to datacenter AI platforms. Coverage analysis requires UNR application in setup, run, and evaluation to scale effectively across that range.

Qualcomm assesses progress to closure through toggle, line, condition, and FSM coverage. Luv said that on one of their larger configurations they have over 200 million coverage goals. That is important not only because checking that many goals is a huge task but also because the number of claimed unreachable goals determined in analysis may also run to millions. Any given claim may result from an over-constraint or an unsupported use-case; only a designer can decide between these options and a true unreachable state.

Bounded proofs compound the problem. If a state was unreachable within proof bounds, can the bounds be increased to increase confidence? Taken together, these challenges are familiar enough in formal property checking but here potentially millions of claims may need manual review by design experts, an impractical expectation only manageable through engineer-defined blanket exceptions which undermine the integrity of the analysis. Worse yet, exceptions may not be portable to other configurations, or even between successive RTL drops for one configuration.

What about divide-and-conquer?

If you know your way around property checking this may still not seem like a real problem. There are multiple techniques to divide a big problem into smaller sub-problems – black-boxing, case analysis, assume-guarantee, etc. Why not use one or more of those methods?

The first and most obvious problem is that UNR is supposed to be a transparent complement to simulation coverage analysis. It should just automatically adjust simulation coverage metrics, so you don’t have to worry about what is not reachable. Requiring partitioning, setup, run and reconciliation through divide-and-conquer analyses is hardly transparent. Second it is unclear how you would divide and then recombine results for say a toggle coverage analysis without understanding if coverage for the sum of the parts really adds up to coverage for the whole. Third, even if such a method could be automated, would it be easily portable to other design configurations? Probably not.

Divide-and-conquer must be a part of a practical solution to conquer scaling, but not through standard methods. Luv/Qualcomm have been working together with the Synopsys VC Formal group to drive a better solution in their FCA (unreachability analysis) app.

Auto-Scale

The method is called Auto-Scale. Consider toggle coverage where you really need to look at the whole design, but the formal model for a large IP is too big. Instead of building this full model, break each coverage metric into sub-tasks and for each build a formal model only around the cone of influence for that sub-task, dramatically reducing the size of a proof without sacrificing integrity. In effect this method handles sub-task partitioning automatically but in a way that preserves proof integrity.

To optimize throughput with completeness, Luv talked about flexibility in a grid spec per metric, also a “memory ladder” allowing you to specify a starting memory requirement per sub-task while allowing that allocation to progressively ramp up in retries for a task which hits a bound before completing the proof. Contrast that with the standard approach where you would need to reserve the maximum memory available at the outset, wasting much of that allocation on quick proofs and maybe still limiting bounds on tough proofs.

Results are impressive. In one example (5-10 million goals), a standard approach to UNR required 6 partitions, 256GB of memory, and left 800k goals uncovered. The Auto-Scale version required no partitioning, ran in under 100GB and left only 500k goals uncovered. Further, line coverage improved from 96% to 99%, condition coverage from 77% to 78%, toggle coverage from 88% to 89% and FSM coverage from 55% to 99%. This last improvement Luv attributes to being able to see all the FSM logic in one-shot rather than needing to split the FSM into multiple runs.

In a larger test with over 50 million goals, the standard approach required 26 partitions, many hundreds of child processes and terabytes of memory. Even though they were able to complete the task in principle, the engineering team rejected these results which they considered too noisy. The Auto-Scale approach required only 4 partitions, ran between 100-500GB of memory and left only 900k uncovered goals (versus 2.4 million for the traditional analysis). Line coverage for both approaches came out at 94%, condition coverage climbed a little from 62% to 65% and toggle coverage jumped from 70% to 93%. The engineering team were happy to use these results 😊

Auto-Scale coverage improvements and significant reduction of uncovered items make a big difference to the effort required of the dynamic verification team to close coverage: net 12% reduction in coverage goals in the first example and 9% reduction in coverage goals in the second. This looks like a real step forward to extend the value of unreachability analysis to larger IPs.

You can watch the presentation yourself HERE.

 

 

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Silicon Catalyst Welcomes You to Our “AI Wonderland”

Silicon Catalyst Welcomes You to Our “AI Wonderland”
by Mike Gianfagna on 10-16-2023 at 10:00 am
Categories: AI, Events, Semiconductor Services, Silicon Catalyst

Silicon Catalyst Welcomes You to Our “AI Wonderland”

Regardless of where you grew up you probably know the story of Alice in Wonderland. The story is over 100 years old, but holds up to the present day, thanks in part to some magic from Disney. It evokes visions of a place that elicits admiration and wonder, to create a place of magical charm. In the context of AI, it takes on a more relevant meaning as a place of great opportunity and potentially serious concerns. This year’s Silicon Catalyst Semiconductor Industry Forum used this theme to illuminate the impact AI will have on our world. It was a very popular event. The venue was even been moved to a larger space to accommodate the anticipated interest. The live, in-person event was Thursday, November 9, 2023 from 5pm – 8pm Pacific Time in Menlo Park, CA. The event sold out and a replay link will be coming. Let’s examine what was discussed and who was there to fully understand how Silicon Catalyst welcomes you to our AI wonderland.

About the Event

The Silicon Catalyst Semiconductor Industry Forum was launched in 2018 with a charter to enable a town-hall like event to discuss the broad impact of semiconductors on our world, beyond the traditional focus on technology, financial reviews and industry business forecasts.

Silicon Catalyst has delivered some memorable Semiconductor Industry Forum events since 2018. You can read about last year’s event, Welcome to the Danger Zone here.

I spoke with Richard Curtin, Managing Partner at Silicon Catalyst recently about the latest event – why the topic, and where he expected the discussion to go. What follows are some of his thoughts.

“The past few decades of semiconductor innovation have spanned many links in the value chain, covering manufacturing, design automation, global supply chain development and scaling. These breakthroughs have resulted in unprecedented growth areas for semiconductor applications, further enabling new business creation and delivering great economic returns for stakeholders and societal benefits for the world’s population. The impact of these innovations on our society is truly remarkable, especially now with the widespread application of AI to all aspects of our daily life and the world’s industries.

But as we’ve seen and experienced in 2023, in the context of AI, it takes on a more relevant meaning as a place of great opportunity, but also potentially serious concerns. To this point, check out the coverage of the developing AI-angst, as documented in the recent broadcasts: 60 Minutes episode and also Real Time with Bill Mahr .

In my personal opinion, the real question to be addressed: are we the proverbial frog in the pot of water?”

Event Details

This year, the topic was AI – its impact on industry, our world and overall innovation. The potential risks of AI deployment and government intervention are relevant to the discussion as well.  Here is a summary of the items that were discussed. This is just a start, there will be more.

  • What are the AI technologies that will create new business models and industries?
  • What are the implications to semiconductor industry success for incumbents & startups?
  • How do we address the power-hungry AI hyper-scalers’ impact on our energy resources?
  • What impact will potential government and industry regulations have on innovation?

Who Presented?

The main event was a spirited panel discussion on the topics above with a group of high-profile executives. The panelists shared their thoughts on how best to address some key questions that arise as we look to navigate the years ahead in our new AI wonderland. There was also a live Q&A with the audience.

The panel was moderated by David French – CEO of SigmaSense and a Silicon Catalyst Board Member. Mr. French’s career spans a broad set of experiences in virtually all aspects of research, design, manufacturing, marketing, and business management within the semiconductor industry. He has recently become CEO of SigmaSense,  a company developing breakthrough software-defined sensing technology.

The panelists were:

Deirdre Hanford – Chief Security Officer, Corp Staff, Synopsys; CHIPS Act Department of Commerce Industrial Advisory Committee. Deirdre leads efforts to drive industry awareness and enablement for secure design from software to silicon to support business in EDA, IP, and Software Integrity. Ms. Hanford previously served as co-general manager of Synopsys’ Design Group. She has held a number of positions at Synopsys since joining the company in 1987, including leadership roles in general management, customer engagement, applications engineering, sales, and marketing.

Moshe Gavrielov – Former CEO of Xilinx; Board member of TSMC and NXP. Mr. Gavrielov served as President and CEO of Xilinx, Inc. from January 2008 to January 2018. Prior to that, he served at Cadence Design Systems as Executive Vice President and General Manager of the verification division. He also held a variety of executive management positions at LSI Logic and engineering management positions in National Semiconductor and Digital Equipment Corporation. Since 2019, Mr. Gavrielov has served on the board of TSMC, and as of May 2023 he joined the NXP board of directors.

Ivo Bolsens – Senior Vice President, Head Corporate Research and Advanced Development, AMD. Previously he was Senior Vice President and Chief Technology Officer (CTO) at Xilinx. The research of his team led to the industry-leading adoption of 2.5D advanced packaging technology in Xilinx products. Bolsens came to Xilinx in June 2001 from the Belgium-based research center IMEC, where he was Vice President of information and communication systems. His research included the development of knowledge-based verification for VLSI circuits, design of digital signal processing applications, and wireless communication terminals.

To Learn More

The live event was held at the SRI Conference Center in Menlo Park, CA on Thursday, November 9, 2023, from 5pm – 8pm Pacific Time.  The agenda included a reception, networking, and Q&A with the panelists. If you missed the event, a replay link is available here. And that’s how Silicon Catalyst welcomes you to our AI wonderland.