SILVACO 073125 Webinar 800x100

Do you have Time to Pull in your Tapeout Schedule?

Do you have Time to Pull in your Tapeout Schedule?
by Ronen Laviv on 12-06-2023 at 10:00 am

schedule pullin

So… , we’re 4 months before tapeout. You were assigned to close place & route on three complex key blocks. You have 15 machines for the job, 5 per block.

You send your first batch, 5 runs per block. You’re not very surprised that your first batch fails. You modify the scripts, and run another batch. And… (Surprise 🙂 the runs do not converge. You have lots of ideas to improve the scripts, you make some changes and, …another run… and another…. and another…. and here we are, two months before tapeout. Still negative slacks.

What do you do?
Compromise on PPA (Power, Performance, Area)?
Delay the tapeout?

Similar questions are also relevant for verification. Think about the RTL freeze and your coverage. Think about formal verification and the properties you have proved so far.

Same with Analog, Characterizations, …

In one of the EDA vendor’s events, there was a presentation about AI for backend, how it saved few weeks of work and resulted better PPA for the tested blocks. It required 900+ CPUs. One of the engineers in the audience said… hmm… 900 CPUs!? I don’t have that compute capacity, all I have is 32CPUs or 96CPUs if I’m lucky.

Well…

Nowadays it has become easy to get as many CPUs as needed for a specific run utilizing AWS cloud.

You may rightfully say… “but I don’t have 150 (or 900) licenses just for my job”

There are two things you could do about your licenses:

  • Run faster and make sure you never wait in queue for machines (I’ll talk about it in one of the next articles). This will allow better utilization of the licenses you already have.
  • The 2nd thing you may want to do is go talk to your EDA vendors as they each have ways to address cloud flexibility licenses.

If the process of verification, place & route or any other run happens to be on your project’s critical path to tapeout, wouldn’t it make sense to pull in the schedule by utilizing resources you can use when needed most?

Back to the backend example (or verification regression), Assuming each run/regression takes ~5 days, and you happen to have only 5 machines at your disposal on premise. You could take 25 machines or more and finish your runs in 5 days instead of 25.

We should be seeing more and more usage of AI tools as Cerebrus and DSO-AI.  Those tools usually require more compute than you might have available on-premise. Whoever utilize those, may cut his time to tapeout / time to market as well as improve PPA compared to manual runs.

The more adoption of AI tools, the more competitive the market would become.

With compute and AI same engineering teams could do more projects, faster, with better PPA.

Here are some public references.

Disclaimer: My name is Ronen, and I’ve been working in the semiconductor industry for the past ~25 years. In the early days of my career I was a chip designer, then moved to the vendor side (Cadence) and now spending my days in the cloud with AWS. Looking at our industry along the years, examining the pain points of our industry as a customer and a service provider I am planning to write a few articles to shed some light on how chip design could benefit from the cloud revolution that is taking place these days.

In the coming articles I’ll cover more aspects of performance & cost for chip design in the cloud.

C U soon.

Also Read:

Generative AI for Silicon Design – Article 4 (Hunt for Bugs)

SystemVerilog Has Some Changes Coming Up

ML-Guided Model Abstraction. Innovation in Verification


Webinar: “Navigating our AI Wonderland” … with humans-in-the-Loop?

Webinar: “Navigating our AI Wonderland” … with humans-in-the-Loop?
by Richard Curtin on 12-06-2023 at 8:00 am

AIeverywhere EETimes

AI is here, there, and absolutely everywhere – now and forever.

The electronics industry, and the world at-large, have experienced an overwhelming amount of AI coverage this year, with no letup in store for 2024. Both EE Times and Silicon Catalyst have recently staged events around artificial intelligence:

  • AI Everywhere” delivered via a series of web sessions

Video Replay

  • “Welcome to our AI Wonderland” – The 6th Annual Semiconductor Industry Forum:
(l to r) David French, Moshe Gavrielov, Dierdre Hanford, Ivo Bolsens

Video Replay

Article write-up:

https://spectrum.ieee.org/how-will-ai-change-semiconductors

Although these events covered the fundamental technical and business aspects of AI, the critical societal impacts of AI were only briefly mentioned. As a result, EE Times and Silicon Catalyst decided to team up and host a follow-on event that was held last week, to delve into the “bigger picture” aspects of how AI will shape our lives. Or as Geoffrey Hinton, cited as the godfather of AI stated,  Humanity is at a turning point with AI”.

You can appreciate that today’s coverage of the AI segment is an interesting and rapidly changing storyline and balancing act:

  • Looking at the safety aspects of AI, and all the issues that come up in terms of the AI-angst generated. Clearly the recent AI-related events are extremely relevant, starting with the pedestrian incident associated with Cruise, the autonomous vehicle company, and also the palace intrigue that took place at OpenAI. What impact will regulatory oversight have on innovation?
  • On the other side of the scale, one needs to understand the financial impact of AI, in both the private and public markets, for electronics industry investment opportunities. Needless to say, I don’t have to remind everyone about the envy that a lot of organizations and investors (private and institutional) now have about Nvidia’s position in the market; with their tremendous YoY sales growth, > 80% AI processor market share and almost 250% YTD stock price increase.

We encourage you to view the joint EE Times and Silicon Catalyst webinar, to get a sense of our rapidly evolving AI landscape, to understand the current state of our industry and how regulatory oversight and investment decisions need to take into account the impact on humanity. The webinar panel was moderated by Nitin Dahad of EE Times, joined by:

  • Jama Adams, COO, Responsible Innovation Labs rilabs.org
  • Navin Chaddha, Managing Partner, Mayfield mayfield.com
  • Rohit Israni, Chair AI Standards, US (INCITS/ANSI) incits.org

Quoting Navin Chaddha from Mayfield, in his closing webinar remarks:

“I think it’s great time to start a company and do it in a balanced way.

So that you do well financially, but also do good for the world.”

Video Replay

About Silicon Catalyst

Silicon Catalyst is the world’s only incubator focused exclusively on accelerating semiconductor solutions, built on a comprehensive coalition of in-kind and strategic partners to dramatically reduce the cost and complexity of development. More than 1000 startup companies worldwide have engaged with Silicon Catalyst and the company has admitted 100 exciting companies. With a world-class network of mentors to advise startups, Silicon Catalyst is helping new semiconductor companies address the challenges in moving from idea to realization. The incubator + accelerator supplies startups with access to design tools, silicon devices, networking, and a path to funding, banking and marketing acumen to successfully launch and grow their companies’ novel technology solutions.

Also Read:

Silicon Catalyst Welcomes You to Our “AI Wonderland”

McKinsey & Company Shines a Light on Domain Specific Architectures

A Look at the Winners of the Silicon Catalyst/Arm Silicon Startups Contest


BEOL Mask Reduction Using Spacer-Defined Vias and Cuts

BEOL Mask Reduction Using Spacer-Defined Vias and Cuts
by Fred Chen on 12-06-2023 at 6:00 am

BEOL Mask Reduction Using Spacer Defined Vias and Cuts

In recent advanced nodes, via and cut patterning have constituted a larger and larger portion of the overall BEOL mask count. The advent of SALELE [1,2] caused mask count to increase for EUV as well, resulting in costs no longer being competitive with DUV down to 3nm [3]. Further development by TEL [4] has shown the possibility for further mask reduction, which will be considered in this article.

With the BEOL metal pitch approaching 20 nm, several patterning scenarios can be envisaged. The first case would be EUV SALELE (Figure 1, left). This would entail the use of 2 masks for trenches, 2 masks for blocks (cuts), and 2 masks for vias. The factor of two comes from the two etch “colors” (mutual selectivity) needed to help relax overlay requirements. If this were done by DUV (Figure 1, right), the number of block and via masks would have to double to achieve the same pitch per line or track [3]. Two masks can still be used to define (through an LELE (Litho-Etch-Litho-Etch) sequence) a core pattern upon which spacer-based SADP (self-aligned double patterning) is executed [5]. This leads to 10 masks being used for DUV vs. 6 for EUV, to pattern one metal and one via layer. While there are more steps, the cost still favors DUV [3]. Still, we can check if there is any opportunity to reduce the masking steps.

Figure 1. (Left) EUV SALELE. (Right) DUV LELE + SADP, followed by 2x LELE blocks and 2x LELE vias.

The number of DUV masks for blocking/cutting can be halved by applying SADP instead of LELE. Figure 2 is an abbreviated sketch of the expected flow.

Figure 2. Replacing LELE block with SADP halves the number of required block masks.

The number of DUV masks for the trench layer (line + block/cut) is now the same as for the EUV case. While we now have extra SADP process sequences that need to be designed, the benefit is that energy consumption for DUV SADP is still ~30% less than that for an EUV single exposure [6], while not being expected to be more expensive [7].

Focusing now on via mask reduction, we can apply the SADP replacement of LELE there as well. With SADP being applied to the trench, via, and block layers successively, the etch selectivity of the materials being processed must be considered very carefully. The resulting process step sequence (Figure 3) becomes much more complicated of course, but the end result would be a halving of the via masks (Figure 4).

Figure 3. Example of a process step sequence expected for full replacement of via and block LELE with SADP [8-17].
Figure 4. Replacing LELE via with SADP halves the number of required via masks.

Thus, the mask reduction is carried to its extreme, by greatly increasing the etch complexity. Yet, even without going so far, having extra DUV masks should not be prohibitive in any way.

References

[1] R. Venkatesan et al., Proc. SPIE 12292, 1229202 (2022).

[2] Y. Drissi et al., Proc. SPIE 10962, 109620V (2019).

[3] F. Chen, https://www.linkedin.com/pulse/extension-duv-multipatterning-toward-3nm-frederick-chen

[4] A. J. deVilliers, US9240329; H. Kang, A. J. deVilliers, US10115726.

[5] S. Sakhare et al., Proc. SPIE 9427, 94270O (2015).

[6] L-A. Ragnarsson et al., “The Environmental Impact of CMOS Logic Technologies,” 2022 EDTM.

[7] L. Liebmann et al., Proc. SPIE 9427, 942702 (2015).

[8] Y. Zhang et al., JVST A14, 2127 (1996).

[9] A. Sankaran and M. Kushner, JAP 97, 023307 (2005).

[10] S. A. Vitale et al., JVST B 27, 2472 (2009).

[11] B. S. Kwon et al., J. Electrochem. Soc. 157, D135 (2010).

[12] J. S. Kim et al., JVST A28, 65 (2010).

[13] F. Weilnboeck et al., JVST B 30, 041811 (2012).

[14] S. Dhungana et al., JVST A34, 061302 (2016).

[15] D. Radisic et al., Proc. SPIE 10963, 109630P (2019).

[16] K-C. Chien and C-H. Chang, JVST B 40, 062802 (2022).

[17] N. Miyoshi et al., JVST A 40, 032601 (2022).

This article first appeared in LinkedIn Pulse: BEOL Mask Reduction Using Spacer-Defined Vias and Cuts

Also Read:

Predicting Stochastic Defectivity from Intel’s EUV Resist Electron Scattering Model

The Significance of Point Spread Functions with Stochastic Behavior in Electron-Beam Lithography

Extension of DUV Multipatterning Toward 3nm


Prototyping Chiplets from the Desktop!

Prototyping Chiplets from the Desktop!
by Daniel Nenni on 12-05-2023 at 10:00 am

S2C PLM Mini

S2C has been successfully delivering rapid SoC prototyping solutions since 2003 with over 600 customers, including 6 of the world’s top 10 semiconductor companies. I personally have been involved with the prototyping market for a good part of my career and know S2C intimately.

S2C is the leading independent global supplier of FPGA prototyping solutions for today’s innovative SoC and ASIC designs, now with the second largest share of the global prototyping market. We all know the benefits of working with an independent company that can focus on the specific needs of prototyping customers so I will skip forward to the technology part of this article.

For prototyping we all read about the scalability of the systems and how many gates are supported. Today hyperscale designs that are in the billions of gates can be prototyped using the latest FPGAs from Xilinx. These high-end prototyping systems are generally housed in a dedicated facility or a cloud.

Not all designs are in the billions of gates however and now that we are entering the chiplet era smaller designs are a focus and that brings us to the new S2C Prodigy Logic Matrix LX2 Mini, an enterprise-class FPGA prototyping solution designed for lab or desktop use.

S2C LX2-M2 Mini and the LX2-P4
Prodigy Logic Matrix Configuration Table

Despite its smaller form factor relative to LX2, LX2 Mini also delivers the same high bandwidth and scalability. Both LX2 and LX2 Mini can leverage S2C Chiplink AXI IP, enhancing partition interconnectivity at up to 100MHz.

Here is a quick video on the S2C Prodigy Logic Matrix LX2 Mini:

Brining the full power of S2C Prodigy Logic Matrix Prototyping to the desktop with the mini series of enterprise-class prototyping will further enable the chiplet market.

Chiplets are like the building blocks of a computer chip. Instead of creating a single, monolithic integrated circuit, chiplets are smaller, individual semiconductor components that can be designed and manufactured separately. These chiplets can then be combined or stacked together to form a more complex and powerful integrated circuit.

The idea is to take advantage of specialized manufacturing processes for different components of a chip. For example, one chiplet might be optimized for high-performance computing, while another might be designed for energy efficiency. By combining these chiplets, you can create a more flexible and efficient overall system.

Think of it like assembling a puzzle where each piece is a specialized chiplet, and when they come together, they create a powerful and cohesive unit.

Verification is a crucial step in the design and manufacturing process of chips, especially in the context of chiplets. Since chiplets are separate components that come together to form a single integrated circuit, verifying their functionality individually and as a collective unit is essential.

Clearly FPGA prototyping chiplets will dramatically speed the verification process and if you are delivering a chiplet to a customer the new S2C Prodigy Logic Matrix LX2 Mini can be sent to your customer’s desktop for close collaboration, absolutely.

Also Read:

S2C’s FPGA Prototyping Accelerates the Iteration of XiangShan RISC-V Processor

ViShare’s Rapid Market Entry with FPGA-Based Prototyping Solution from S2C

Systematic RISC-V architecture analysis and optimization


Building Reliability into Advanced Automotive Electronics

Building Reliability into Advanced Automotive Electronics
by Bernard Murphy on 12-05-2023 at 6:00 am

Automotive reliability min

Those of you who have been in the industry for a little while will remember that the recipe for reliable electronics in cars (and other vehicles) used to be simple. Stick to old (like 10 years old) and well-proven processes and tweak rather than tear up and restart well-proven designs to the greatest extent possible. Because incrementing from a well-characterized base should ensure that reliability and other KPIs will not drift too far from expectations.

That recipe went out the window when we demanded that our vehicles turn into phones on wheels, offering ADAS, autonomy, advanced infotainment, requiring state of the art processes and architectures. Throwing out the rulebook gets us all the functionality; however, we don’t expect our phones to be ultra-safe or work reliably for 20 years or more. How do we bridge the gap between all the technology goodies we want and our safety and durability expectations?

proteanTecs recently hosted a webinar I rate a must-watch on this and related topics. Packed with information and informed opinion, it measurably increased my understanding of challenges and directions towards bringing high reliability to advanced technologies. More generally it helps build greater understanding of the need for electronics lifetime monitoring and adaptation. Participants were Heinz Wagensonner (Senior SoC designer at Cariad, the automotive software branch of Volkswagen), Jens Rosenbusch (Senior Principal Engineer, SoC safety architecture at Infineon), Robert Jin (Automotive safety architect at NXP), Gal Carmel (Senior VP/GM for automotive at proteanTecs), and moderator Ellen Carey (Chief External Affairs Officer at Circulor).

What Auto Reliability Means Today

One aspect of enhanced reliability is in fail-safe or fail-degraded systems. Real systems can and will fail. Acknowledging this reality, when a system is failing or expected to fail, a redundant system can take over or the system can fall back to reduced functionality, still safe enough to allow the car to limp home or perhaps to the side of the freeway. This reasoning is already well understood, though is expected to be applied more widely in future designs.

Another aspect – the subject of this webinar – recognizes that high reliability cannot be assured in a system which fails to evolve over time. Devices age, use-cases change, the environment changes, and feature capabilities will be upgraded. Few of these changes can be accounted for in the t=0 (product release) system. Systems must become intelligently self-monitoring, responding in part through locally determined adaptation but also through a feedback loop to a central resource which can synthesize broader learning for dissemination back to vehicles.

In short, for continued high reliability in these advanced systems, closing the spec for t=0 is only the start. You move to Arizona (hot) and your daily commute doubles. You are now pulling a trailer and have downloaded a software upgrade to your vehicle (now 10 years old) which promises to improve your range (ICE or EV). The “spec” keeps changing yet reliability plus safety must continue to measure up to the highest standards. This demands in-system and in-circuit monitoring through embedded sensors for workload, temperature, voltage, interconnect, and delay monitoring (for example) together with on-board ML-driven intelligence to interpret that data. This should capture not only immediate problems but also anomalous signatures which might indicate the beginning of a future problem. Allowing us to supplement now routine safety mitigations with the beginnings of predictive maintenance.

What constitutes a problem or a suspicious signature depends on mission profiles. One size does not fit all, for example a robotaxi, a city business vehicle, a personal car in the city or in rural use, will have different profiles. An important aspect of profiles will be factors affecting power: voltages and frequencies for example. Lowering power improves thermal reliability of course but will also extend range in an EV, also a positive for reliability.

Profiles can’t be programmed into a product at release, not least because we have no idea (yet) what those profiles should be. The t=0 spec must somehow accommodate the full range of possibilities, which designers accomplish through margins, margins everywhere which is expensive. In use, it will become clear for a certain profile that some margins can be tightened, whereas others perhaps should be loosened. Intelligent systems can learn their way to profile optimization, even better if they can share data with other cars.

From Theory to Practice

Naturally proteanTecs plays an important part in this solution. During chip design, they build and insert low impact agents, guided by detailed analysis, into the design to assure high coverage data in use. Working in partnership with proteanTecs, NXP have written a paper which became a driver for the ISO/TR:9839 standard on predictive maintenance. This is expected to fold into or alongside the next rev of the ISO 26262 standard.

This method for capturing and utilizing in-use behaviors is a starting point, however all participants agree that the next interesting/challenging step to derive full value is to collaboratively share this data, certainly within a brand, even across brands for common subsystems, say for engine and braking. Complementary value could be found in considering reliability of total system (the car) rather just individual component or subsystems. In both cases there is rich potential for AI to detect signature patterns in this collective data, patterns which perhaps appear only in multi-factor correlations that we would find hard to detect ourselves.

Sharing data is always a tricky topic these days. Since the types of data discussed here is relatively low-level, I would think so privacy concerns may not be as big an issue as brand competitive concerns. All panelists agreed on the need to build an ecosystem together with regulatory bodies to develop and support standards in this area.

There were several other interesting points raised. Will Tier1s disappear as OEMs build their own silicon? (no). How will this approach simplify analysis for field failures? (massively). Can chiplets help with reliability? (Maybe in the next decade after multi-die system reliability has been proven to automotive expectations for temperature, vibration and humidity).

Watch the replay for more detail on all points.

 


Improving Wafer Quality and Yield with UPW Resistivity and TOC Measurements

Improving Wafer Quality and Yield with UPW Resistivity and TOC Measurements
by Kalar Rajendiran on 12-04-2023 at 10:00 am

MT Group Stock Photo

An earlier SemiWiki post discussed water sustainability in semiconductor manufacturing, related challenges and solutions. Whether first time use or recycled use, water purity needs to meet certain stringent criteria for the processing task on hand. This article will look at it from a wafer quality and yield perspective and is based on a recently published whitepaper by Mettler Toledo.

The Significance of Water Purity in Semiconductor Manufacturing

Water serves as a cleaning agent, a heat transfer medium, and a crucial ingredient in the chemical processes used to etch and deposit materials onto wafers. Any impurities in the water can lead to defects on the wafer, reducing yield and affecting the overall product quality. Minute amounts of ionic impurities and organic contamination even at the sub-parts per billion (ppb) level, can negatively impact the yield and quality of wafers. Therefore, it is essential to monitor and control the purity of the water used in semiconductor manufacturing.

Ensuring Water Purity

Two key parameters that must be monitored in real-time to ensure ultrapure water (UPW) are Total Organic Carbon (TOC) and resistivity. TOC refers to the measurement of organic carbon compounds present in the water, which can be indicative of contamination. Resistivity, on the other hand, measures the water’s ability to conduct electrical current and can highlight any ionic impurities. As such, real-time, continuous monitoring of resistivity and Total Organic Carbon (TOC) has long been a standard practice in the industry. Strict control of these parameters is crucial for semiconductor manufacturers to enhance wafer quality and maximize yield in this highly competitive industry.

Challenges Faced

UPW is produced through a complex and costly multistage purification process. This process involves various techniques, such as reverse osmosis, micro-filtration, electrodeionization, ion exchange, adsorption, and UV photo-oxidation. However, one challenge associated with UPW is that any water used for Total Organic Carbon (TOC) measurement, a key indicator of water purity, cannot be returned to the process water stream and is instead directed to drain. UPW has a very high resistivity of 18.18 Megohm-cm, making it crucial for resistivity instruments used in semiconductor manufacturing to accurately detect even the smallest resistivity changes on a non-zero background.

While UPW is extremely important, being overly tight in measuring the purity level could lead to potentially throwing away a significant quantity of water as wastewater. On the other hand, a more relaxed approach could impact product quality and yield. To meet the industry’s stringent expectations for water purity, resistivity instrumentation must provide stable, precise measurements with effective noise reduction techniques in place.

Consequently, semiconductor manufacturing facilities seek solutions that are reliable, easy to integrate into existing systems, and operator-friendly.

UPW Monitoring For Stable and Precise Measurements

Advanced sensor technology such as Mettler Toledo’s UniCond sensors can simplify monitoring processes in several ways. These sensors are equipped with onboard memory that stores their unique identity and calibration data, and this information is automatically transmitted to the connected transmitter. Mettler Toledo’s M800, is a multi-parameter transmitter that offers installation flexibility and simplified process control measurements. It can simultaneously monitor one, two, or four in-line sensors, making it a versatile and cost-effective solution for UPW monitoring. This “plug and measure” approach simplifies installation and ensures the sensor’s performance integrity, even if it’s relocated to another process location.

The 6000TOCi sensor from Mettler Toledo provides additional features to streamline routine system maintenance. Users benefit from local storage of calibration data, allowing them to access historical calibration records, which ensures compliance with water system requirements.

Mettler Toledo’s Intelligent Sensor Management (ISM®) technology not only facilitates the communication of calibration data but also offers sensor diagnostics. These diagnostics can identify out-of-range resistivity measurements and temperature variations, contributing to improved process control. ISM also supports calibration planning and provides advance warnings of potential sensor failures through Dynamic Lifetime Indicators (DLI) for components like the UV lamp, filter, and ballast. This proactive approach helps reduce downtime and increase yield in industrial processes.

Summary

Repeatable and precise measurements are essential to maintain a consistent supply of UPW to wafer tools and wet benches. Mettler Toledo offers the most advanced tools for on-line continuous measurement and process control required for UPW systems. Its suite of plug-and-measure sensors, including UniCond and 6000TOCi sensors, can be easily integrated into existing water systems via a user-friendly M800 transmitter interface. These solutions ensure that TOC and resistivity are monitored at sub-ppb levels, reducing risks and improving yield.

For more details, download Mettler Toledo’s whitepaper here.

Also Read:

Podcast EP194: The Impact of Joining TSMC’s OIP From the Perspective of Agile Analog

CEO Interview: Dr. J Provine of Aligned Carbon

RISC-V Summit Buzz – Ron Black Unveils Codasip’s Paradigm Shift for Secured Innovation


RISC-V Summit Buzz – Axiomise Accelerates RISC-V Designs with Next Generation formalISA®

RISC-V Summit Buzz – Axiomise Accelerates RISC-V Designs with Next Generation formalISA®
by Mike Gianfagna on 12-04-2023 at 6:00 am

RISC V Summit Buzz – Axiomise Accelerates RISC V Designs with Next Generation formalISA®

If the recent RISC-V Summit proved one thing it’s that open-source hardware design, and particularly the RISC-V instruction set architecture (ISA) has entered the mainstream. It is a design methodology and architecture to watch closely. Across a broad range of applications from data center, to automotive, to IoT, RISC-V processors are finding a fit to address the huge processing demands of embedded AI. As is the case with any complex system design, a primary care-about is a robust design that is bug-free. Given the complexity of these designs, getting a new RISC-V implementation to that fully verified state can be a daunting task. An effective approach to this problem is by deploying formal verification. Using this approach can be challenging due to the expertise needed but this is where Axiomise can help. The company’s mission to “make formal normal” and its approach, along with RISC-V specific enhancements was on display at the Summit. Read on to see how Axiomise accelerates RISC-V designs with next generation formalISA®.

About Axiomise and formalISA

Axiomise was founded in 2017 by Dr. Ashish Darbari, after spending over two decades in the industry and top research labs increasing formal verification adoption. The company enables formal verification adoption by simplifying jargon and showing design teams how complex problems are easily solved through Axiomise’s abstraction-driven methodologies. These methodologies are vendor neutral. Training and consulting services are also available to enable formal in any corporate setting. You can learn more about Axiomise and its technology on SemiWiki here.

Earlier this year, the company announced its next-generation app specifically targeted at RISC-V processors. This unique push-button solution simplifies everything necessary to make verification efficient and effective. From avoiding test generation (like simulation) by using architectural-specification-precise formal properties to exhaustive testing (via formal) to then saving debug time (70% of verification time spent here) using i-RADAR® to sign-off via scenario coverage and reporting via SURF.  Its debug tool is powered by an intelligent debugger called     i-RADAR and a reporting and coverage solution called SURF.

It was reported in this announcement that the formalISA App has been in use for more than four years to formally verify numerous open-source and commercial RISC-V processors, proving the absence of bugs in out-of-order and in-order cores and exposing bugs in previously verified processors.

The Buzz at RISC-V Summit

Adeel Liaquat

At the RISC-V Summit, I was able to speak with Adeel Liaquat, engineering manager at Axiomise. I began by asking Adeel if there was one consistent care-about being expressed at the show. His answer was “time to market.”

He went on to explain that everyone wants an efficient, bug-free RISC-V processor to power new designs. Getting to that goal can be quite time consuming, however. Conventional UVM and simulation technology approaches can fall short of attaining the required level of robustness. Stimulus must be developed to cover all cases, and that is an open-ended, huge undertaking.

Formal verification offers a faster path by verifying the design across all possible states without the need for exhaustive input vectors. Adeel pointed out that handling deadlock conditions is a good example of the benefits of formal verification. These conditions may manifest after years of deployment in the field. It is virtually impossible to run enough vectors to uncover these situations up-front. The exhaustive nature of formal verification will ensure these conditions do not occur.

With all these benefits, why isn’t formal more popular? Adeel explained it’s a combination of awareness of the approach and expertise to implement it. He added that without the right methodology one could wind up in a verification “loop,” using up all licenses and all available time without a concrete result. Axiomise is a company dedicated to address this problem for design teams of all sizes.

From a technology perspective, the formalISA App makes RISC-V ISA specific formal technology available. The i-RADAR debugger simplifies the unique requirements associated with formal verification debugging. And SURF makes it easier to coordinate all the verification runs and consolidate results. Adeel explained that Axiomise can also develop custom capabilities that may be needed as well. Beyond the technology layer, the company offers training and consulting to bring design teams to the required level of proficiency. If internal resources are scarce, Axiomise can create and implement the full formal verification strategy and process for the customer.

This was an insightful discussion – I began to see how the mission of making formal normal was within reach. And that’s how Axiomise accelerates RISC-V designs with next-generation formalISA.

 


Podcast EP196: A Look at the Upcoming IEDM Conference with the Publicity Chair and Vice Chair

Podcast EP196: A Look at the Upcoming IEDM Conference with the Publicity Chair and Vice Chair
by Daniel Nenni on 12-01-2023 at 10:00 am

Dan is joined by Jungwoo Joh, a Process Development Manager at Texas Instruments and Publicity Chair for IEDM 2023. He currently leads gallium nitride technology development for power applications, and has been working on reliability, device characterization & modeling, and process development for various GaN based technologies as well as for high voltage silicon BCD processes. Jungwoo received his Ph.D. in Electrical Engineering from MIT. He has published more than 60 papers and holds 20 patents. He is a Senior Member of IEEE, and has been serving on IEDM technical and executive committees since 2015.

Dan’s other guest is Kang-ill Seo, Vice President of Samsung Electronics and Publicity Vice Chair for IEDM 2023. He directs Samsung’s international joint project with IBM at Albany Nanotech in New York state.His current research focuses on development of leading-edge logic technologies, including 3D transistor architectures, Interconnect with novel materials, and associated design-technology-co-optimization for next-generation devices for low-power and high-performance computing. Kang-ill earlier participated in and led the development of several generations of logic technologies, from 20nm to 7nm, in Samsung’s Semiconductor R&D center. He received his MS and Ph. D in Electrical Engineering and Material Science & Engineering from Stanford University. His has been published in 25 peer-review journals and conferences, and has more than 60 issued patents. He has served on the IEDM executive committee since 2018.

Dan explores what will be the popular topics at the upcoming IEDM with Jungwoo and Kang-ill. Energy conservation, sustainability and reduced carbon footprint are just a few of the many topics to be addressed. The evolution from 2D to 3D CMOS scaling at the device, circuit and chip levels are also discussed. New areas in memory design are discussed as well, along with changes to the conference program to support many new AI-driven innovations.

IEDM 2023 will be held in San Francisco from Dec. 9 – 13. You can register for the conference here.


CEO Interview: David Moore of Pragmatic

CEO Interview: David Moore of Pragmatic
by Daniel Nenni on 12-01-2023 at 6:00 am

PIC BY STEWART TURKINGTON www.stphotos.co.uk

David has almost 25 years of leadership experience in the semiconductor industry. Prior to joining Pragmatic, he served as Chief Strategy Officer at Micron Technology, Inc. He also spent six years at Intel Corporation in various roles, including General Manager of the Programmable Solutions Group, where he led the multi-billion-dollar FPGA and Structured ASIC business on a global basis.

Tell us about your company?
Pragmatic is a UK-based leader in flexible integrated circuit technology and semiconductor manufacturing. We use thin-film semiconductors to create ultra-thin, flexible integrated circuits, known as FlexICs, that are significantly cheaper and faster to produce than silicon chips – we’re talking days, rather than months, and potentially sub-penny price points for certain applications.

As you can imagine, this makes FlexICs a compelling alternative to silicon for lots of mainstream electronics applications, as well as enabling new applications that may not have been possible previously, either because of cost or due to silicon’s rigid form factor.

We also offer a Fab-as-a-Service model that enables secure, dependable, localized semiconductor supply. The reduced complexity of our innovative manufacturing and process technology allows for compact fabs that are orders of magnitude lower in terms of cost, and physical and environmental footprint, compared to silicon.

We are headquartered in Cambridge, UK with production lines in Durham in the northeast of England.

What problems are you solving?
Many of the most impactful Internet of Things applications that seek to harness AI at scale will depend on item-level intelligence and ubiquitous connectivity. We’re talking billions – and, ultimately, trillions – of smart physical objects. For a number of reasons, silicon chips alone can’t achieve that, and we aim to plug the gap.

Recently, we’ve become all too familiar with the impact of brittle supply chains. Even if we assume that similar shocks won’t reoccur – while being cognizant that they likely will – there’s simply not enough fab capacity in the world pumping out the right kind of silicon chips to address the incoming tsunami of demand. And it wouldn’t be cost-effective to use silicon for many of these workloads even if there were. The long lead times and high costs associated with silicon chip design mean that it is best reserved for creating complex, higher-spec chips in applications that require that level of performance.

We operate at the other end of the scale. Our agile technology platform, which leverages industry standard EDA tools, and rapid production cycles allows you to target a specific application and customize to meet the performance required. This means you can accelerate time to market – and even make changes as your requirements shift, without incurring crazy re-spin costs or long turnaround times.

To be clear, we’re not trying to compete with leading-edge silicon, here. Today’s FlexICs deliver just enough performance for a very wide range of simple tasks. But that simplicity is their strength and, it’s what allows them to provide ubiquitous intelligence and connectivity, at a price point and low environmental impact that’s simply not achievable with silicon.

What application areas are your strongest?
One of our largest, near-term opportunities is in Radio Frequency Identification (RFID) and Near-Field Communication (NFC) applications that use smart and reusable packaging to dramatically enhance supply chain optimization and consumer engagement.

There’s huge consumer demand, and increasing regulatory requirements, for brands to improve supply chain traceability and reduce waste. However, that can be challenging for high-volume, lower-value goods and packaging – often, the numbers just don’t add up.  But when you’re talking about item-level intelligence at a price point of pennies or less, it’s a game changer.

Companies have been quick to spot this potential: for example, we’re working on a trial with a major UK supermarket chain that’s investigating the deployment of smart reusable packaging at scale. It’s one of many exciting opportunities to change the way we think about plastic and waste in everyday consumables.

We’re also looking at a range of healthcare applications, from temperature sensors in health monitors to smart bandages – an area where the thinness and flexibility of our chips can really make a difference to wearer comfort.

We also see significant opportunities in consumer wearables and even toys and games. In an age where it can be hard to get kids off screens, boosting the interactivity levels of their ‘analogue’ toys by seamlessly adding intelligence holds a lot of appeal.

What keeps your customers up at night?
In recent years, semiconductor supply has been a key issue – concerns over global supply chain resiliency have been reflected by the US and EU Chips Acts and the UK’s recent semiconductor strategy announcement.

There’s now a push to onshore semiconductor fabrication, but if you’re looking to add silicon capacity on an advanced or even a mainstream node, it’s not something you can do quickly – or, often – economically a single fab typically costs billions of dollars to build and takes many years to be deployed. But deployment of new flexible semiconductor fabs takes far less time and because they’re modularly scalable: you can achieve cost-effective, localized manufacturing with a cost structure that’s significantly lower than legacy silicon fabs. And you can do it quickly, too!

Beyond that, as demand for semiconductors continues to grow, there’s increasing pressure for the industry to tackle its carbon footprint. Because our unique production process omits many of the resource-intensive, high-temperature stages of silicon semiconductor manufacturing, it uses orders of magnitude less water and energy, and significantly fewer harmful chemicals and gases. In particular, we don’t create or release PFAS – forever chemicals. While it’s not always easy to lay your hands on the relevant industry figures to make an exact comparison, initial calculations show that chips from our fabs could have a carbon footprint  well over 100  times lower than those manufactured in typical silicon fabs.

What does the competitive landscape look like and how do you differentiate?
Currently, no other company has a comparable offering in commercial production and, to our knowledge, competing approaches in research and development are still many years away from volume manufacturing at scale.

For existing applications using silicon chips, we compete against ‘legacy node’ foundries, but in practice, our differentiation on cost, form factor, production cycle times, sustainability and security of supply gives us unique advantages wherever our performance meets the application requirements.

What new features/technology are you working on?
Innovation is the essential fuel of our growth plans. We’re currently ramping up our second fab in the northeast of England, which will be the first 300mm wafer fab in the UK. It has the capacity to deliver billions of ICs per year, and we’ll be commissioning additional lines at the site to bring capacity to tens of billions of ICs in 2025.

Our next-generation process technology will deliver a 10X reduction in power consumption and significant area reductions, generation-on-generation, for our RFID product lines and to our foundry customers.

We’ll also be advancing our RFID technology roadmap to support expanded NFC features and Ultra High Frequency (UHF) RFID applications, enabling breakthrough solutions at scale in what is one of the fasted growing segments in the semiconductor industry.

In parallel, we’re investing to deliver new, cost-optimized, ultra-thin sensing and control capabilities that further expand our addressable foundry market for a host of exciting, high-impact applications in the consumer, healthcare and industrial segments.

How do customers normally engage with your company? 
Our core offering is the provision of foundry services to our customers. They design the chip, or partner with us to design it, then we manufacture and deliver the diced FlexIC wafers – just like companies such as TSMC or Global Foundries in the silicon space.

We also produce RFID products as ICs that are integrated into intelligent labels and smart packaging solutions by leading brands or RFID tag and solution providers.

Finally, Fab-as-a-Service is our unique solution for the future of distributed semiconductor manufacturing. By installing and operating a fab at the customer’s site of choice, we provide secure, dedicated, localized capacity and the most attainable route to cost-effective, scalable fabrication.

We’re excited for the future. By matching our unique technology with a disruptive business model – and our customers’ innovation – we’re confident that we can change the face of semiconductors, facilitating ubiquitous connectivity and solutions to some of the world’s most pressing data challenges.

Pragmatic Semiconductor

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RISC-V Summit Buzz – Semidynamics Founder and CEO Roger Espasa Introduces Extreme Customization

RISC-V Summit Buzz – Semidynamics Founder and CEO Roger Espasa Introduces Extreme Customization
by Mike Gianfagna on 11-30-2023 at 10:00 am

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Founded in 2016 and based in Barcelona, Spain, Semidynamics™ is the only provider of fully customizable RISC-V processor IP.  The company delivers high bandwidth, high performance cores with vector units and tensor units targeted at machine learning and AI applications. There were some recent announcements from Semidynamics leading up to the RISC-V Summit that extend the company’s focus on customization. I had a chance to meet with the company’s CEO at the Summit to get the back-story on what the announcement really means. Read on to get the whole story about how Semidynamics founder and CEO, Roger Espasa, introduces extreme customization.

What Was Announced

First, let’s look at what was announced leading up to the RISC-V Summit. The headline was Semidynamics launches first fully-coherent RISC-V Tensor unit to supercharge AI applications. The announcement introduced a RISC-V Tensor Unit designed for ultra-fast AI solutions. The design is based on the company’s fully customizable 64-bit cores. The Tensor Unit is built on top of the Semidynamics RVV1.0 Vector Processing Unit and leverages the existing vector registers to store matrices, as outlined in the figure below.

Tensor Unit diagram

This enables the Tensor Unit to be used for layers that require matrix multiply capabilities, such as Fully Connected and Convolution, and use the Vector Unit for the activation function layers (ReLU, Sigmoid, Softmax, etc.), which is a big improvement over stand-alone NPUs that usually have trouble dealing with activation layers.

The Tensor Unit leverages both the Vector Unit capabilities as well as the Atrevido-423 Gazzillion™ capabilities to fetch the data it needs from memory. Semidynamics Gazzillion technology allows the processor to send up to 128 requests to the memory system, whereas other cores can only tolerate very few cache misses. This means that the processor continues doing useful processing while previous misses are served. It is interesting to note that Tensor Units consume data at an extremely high rate and, without Gazzillion, a normal core couldn’t keep up with the Tensor Unit’s demands. Other solutions rely on difficult-to-program DMAs to solve this problem. Semidynamics took a different approach by seamlessly integrating the Tensor Unit into its cache-coherent subsystem. This innovation effectively opens a new era of programming simplicity for AI software.

The Motivation and Back-Story for the Announcement

Roger Espasa

I spent some time with Semidynamics Founder and CEO Roger Espasa at the Summit. Dr. Espasa is not your typical high-tech startup CEO. He has been teaching at the Universitat Politècnica de Catalunya in Barcelona for over 31 years. This work has brought him close to a rich pallet of innovation and an array of venture funding sources. Before founding Semidynamics over seven years ago, he was chief architect at Esperanto Technologies, technical director at Broadcom, a principal engineer and silicon architect at Intel, and an architect at Compaq. Roger has done the job of many of his customers. This gives him a unique ability to understand what they need, and his substantial exposure to innovation allows him to see the path forward with a unique level of insight. He explained that he can dig into the challenges of Semidynamics customers and help to develop unique, focused and highly efficient solutions. And this focus on problem-solving and making its customers successful is what created the new architecture that was announced and demonstrated at the show.

As Roger explained, customers told him they loved the Vector Unit architecture Semidynamics provided, but, for challenging AI workloads there was always a need for more. That request “for more power” is what led Roger and his team to add the Tensor Unit to help address the need for vast processing power. Roger pointed out this enhancement was delivered as part of the RISC-V ISA, making it easier to integrate the Vector Unit, Gazzillion technology and now the Tensor Unit into AI workloads. Ease of programming was a key feature, and Roger’s years of system design experience helped to drive that delivery. He explained that his customers are making huge investments in the SoC that will bring their new product idea to life. Their company is on the line, and Semidynamics intends to remove as many barriers as possible to enable success. This attitude means embracing special requirements, and that’s how Semidynamics founder and CEO Roger Espasa introduces extreme customization.

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