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Huawei and Intel Redrawing the New Mobile Playing Field

Huawei and Intel Redrawing the New Mobile Playing Field
by Ed McKernan on 02-28-2012 at 7:22 pm

This time is differentis a book that was released just months before the financial crises in 2008 describing hundreds of historical cases where smart people ended up making disastrous decisions over the span of 800 years that led to government defaults, banking panics etc… In the semiconductor industry, we also tend to think this time is different due to the rapid advancements made possible by Moore’s Law. A year ago the ARM camp (nVidia, TI, Marvell, BRCM) was riding high at the prospects of winning the mobile market and casting Intel aside. Now, I would argue, that Apple’s stunning growth has forced a completely new game on the industry. In this game the phone carriers are in desperate need for an alternative and Intel and Huawei, with their announcements this week, have shown the way to “save the carriers.”

You want to talk about big money, AT&T’s revenue was $127B in 2011 and Verizon’s was $111B. Repeat these numbers with the carriers the world over and it becomes obvious that there exist a big leagues (call it the $100B club), that few suppliers can play in. Apple frightens the carriers because they have to shell out all the Cap Ex to handle the mobile tsunami imposed by Apple’s iPhone and iPADs. Starting with the 4G LTE enabled iPAD 3 in March and followed by a similarly enabled iPhone 5 in the fall, the tsunami data waves will increase in a magnitude that will be more than a step function. What shall they charge customers for the data onrush, no mathematician can foretell. However, whatever it ends up being, one thing is sure: Apple will have a hand in negotiating the business model.

Five years ago Nokia could never have imagined getting away with selling a phone to carriers for an average of $660. With the iPAD 3 with LTE, expect it to go higher. Apple’s roughly 60% gross margin is significantly more than what they receive for the MAC PCs and is a sense causing the carriers to see a future bloodbath. The carriers need an alternative house brand that provides margin relief and counterweight to Apple, who will likely ramp up to at least 50% of their customers. So while they can not live without Apple, they can’t survive on them alone.

Which brings us to this week and the announcement that Huawei is building its own quad core processor for smartphones and that Intel has made agreements with the UK carrier Orange, the Indian carrier Lava and Chinese equipment manufacturer ZTE to build and sell Medfield based smartphones this year. It should be noted that Huawei and ZTE are the #1 and #2 Chinese Telecom and Networking equipment vendors and furthermore they are both in the top 5 in mobile handsets.

The announcement of Huawei building their own processor is another sign that independent silicon suppliers like nVidia, TI, Marvell and Broadcom will see less fertile grounds to plow in the mobile space. In the last earnings call, nVidia CEO Jen Hsun Huang admitted that sales of Tegra 3 would come in much lower than expected for 2012 because Samsung had decided to use their own in house processors. Vertical integration is the trend and it is absolutely necessary.

Looking much further down the road though, Huawei and Intel appear to be on similar tracks with a slight twist. Huawei is going to go completely in house vertical with the smart phones and telecom equipment with some assist from Qualcomm on the 4G LTE in phones and base stations. They will offer a package deal to carriers – buy the telecom and networking equipment and get the phones at a discount. The net is an increase in cash flow to carrier over buying phones from HTC or Samsung and equipment from Huawei, ZTE, Cisco or Ericsson.

ZTE looks like it will rely on Intel for silicon not only for cell phones but I am guessing also for networking and future telecom gear. Huawei is financially more powerful than ZTE and has in fact set up a design center in Silicon Valley staffed with ex-Cisco engineers to build high end ASICs for Routers and Switches. Their footprint is growing.

With what they believe is a 4 year lead in process technology, Intel is now going to execute a strategy of offering what will be lower cost, lower power silicon in the smartphone and tablet space by the time they convert Atom to 22nm in early 2013. On the other side of the house, it appears that they will expand their data center offerings to the point they can deliver the silicon a ZTE needs to be competitive with Huawei. All of this will likely have an “Intel Inside” marketing pull through the carriers.

As mentioned in a previous blog, the era of independent Fabless chip companies who rely on the leading edge is coming to an end. The winners will own Fabs (ie Intel or Samsung), have IP or be vertically integrated like Apple or Huawei who bury the processor in the total BOM of the phone. Both though will be tempted to jump to Intel to gain access to the latest process technology and gain an edge on Samsung.

For the carriers, they see a need to immediately address the bottom line before Cap Ex overwhelms them. For Huawei, ZTE and Intel the doors of opportunity have just opened up. More Importantly, for Intel this time is no different than how they executed in the 1990s PC Market.

Now, with regards to Google….

FULL DISCLOSURE: I am long AAPL, INTC, ALTR, QCOM


HSPICE Users Talking about Their Circuit Simulation Experience

HSPICE Users Talking about Their Circuit Simulation Experience
by Daniel Payne on 02-28-2012 at 4:46 pm

tony todesco

HSPICE users gathered in January 2012 at the HSPICE SIG(Special Interest Group) to talk about their experiences using this circuit simulator for a variety of IC and signal integrity issues. I wasn’t able to attend in person however I did watch the video and wanted to summarize what I heard:
Continue reading “HSPICE Users Talking about Their Circuit Simulation Experience”


Does 14nm magically put Intel back on the lead smartphone lap?

Does 14nm magically put Intel back on the lead smartphone lap?
by Don Dingee on 02-27-2012 at 2:15 pm

I’ve often wanted to publish a book with nothing but photos of police cars, so that people wouldn’t have to slow down and gawk at them when they have someone pulled over on the side of the freeway. Intel roadmaps seem to have the same effect on people. No matter what is on them, even if there’s nothing really new, they stop people in their tracks just to look.

At Mobile World Congress today, Intel’s Paul Otellini created the latest traffic jam by laying out the plans to move from the Atom Z2460 (Medfield) at 32nm into the Atom Z2580, targeting their new 14nm process in two years. Also, he previewed the Z2000, the first “value” tier push targeting lower cost implementations.

Intel firmly believes they can compete in mobile, and is betting the farm on 14nm to catch up. With roughly twice as many transistors to deal with compared to an ARM Cortex-A9 core, they’re looking to faster memory interfaces, FinFETs, and process shrinks to get it done.

The push to 14nm isn’t surprising at all: Intel has to fill Fab 42. It’s the only play. With the news of HP shrinking their way to greatness in the PC business, it will have to come from Atom, smartphones, and embedded … er, intelligent systems.

While the initial Atom Z2460 performance numbers are in the range of the Qualcomm MSM8960 (BrowserMark: 116425 vs. 110345), they are coming at substantially higher power consumption – about 1W versus something less than 750mW, maybe as low as 450mW. The performance/watt figures still favor the ARM camp, by a lot, and that ecosystem isn’t standing still with things like the Cortex-A7 coming.

Intel has a huge gap to close here, and it’s good to see they are competing to get back on the lead lap, but they have a lot of work left to do.


Yalta is Dead! Synopsys offensive in VIP restart the cold war

Yalta is Dead! Synopsys offensive in VIP restart the cold war
by Eric Esteve on 02-27-2012 at 11:29 am

Last year, you could claim (like I did in this blog) that Cadence was making money with large VIP port-folio, when Synopsys was managing sales of a large Design IP port-folio (thanks to a successful acquisition strategy in the 2000’s). But the latest acquisitions made by Synopsys of VIP centric companies like nSys or ExpertIO should have warned us (and Cadence, by the way): the EDA and IP centric company is investing the VIP field! After the acquisitions time come the new product launch, today the market is discovering… Discovery.

It looks like this product launch is a real offensive, and much more than just an announcement. Synopsys Discovery VIP is written entirely in SystemVerilog, includes native support for UVM, VMM, and OVM, and is compatible with all related verification environments… and supports all major simulators, including Cadence Incisive (!), the product realizes a breakthrough in the VIP jungle. Because of the multiple competing above mentioned standards (UVM, VMM and OVM), the only way to support all of these (and it was a strong market requirement) for a VIP product was to use wrappers. By using wrappers, on top of making the product inelegant, you made it slower. Diminishing simulation run time, offering a performance improved by 3 to 6X is a strong sales argument, I am sure that Synopsys’ sales force will be the first to benefit from this argument, the second being the customers!

Such an argument is based on an identified issue, that every design team trying to complete a SoC design, every marketing team fighting with Time To Market issue, every shareholder expecting a high return on investment knows very well; the cost and elapsed time due to Verification. In fact, I am not so sure that the basic shareholder understands anything about Verification, but he should understand ROI! The next picture is useful to understand the cost breakdown associated with Verification. If you look at the middle left box, you see a 3X cost (or license count, or resources) increase for almost every task (except “Tool, Support and Service” with 20% only, so I suspect that Synopsys will sell Discovery 20% higher than the previous solution?). So, offering a 3 to 6X run time improvement is welcome, to keep the design schedule and consequently the time to market within reasonable limits.

If you look at the product itself, Synopsys includes with Discovery VIP, a Protocol Analyzer which enables engineers to quickly understand, identify and debug protocols in their designs, and debug and coverage management features, so the complete solution is built within a single product.

If we look to Synopsys VIP port-folio, we can see that the war with Cadence will be face to face, protocol by protocol, as they both address the same customer needs. Except for the Memory Models, that Cadence is marketing after Denali acquisition, and where Denali had a monopoly for a long time, but on what constitute the Verification IP market, still to be evaluated, but probably in the $100 to $150 million range, we can expect to see an interesting battle. I am just waiting to know what will be Cadence’ answer to Synopsys’ Discovery offensive!

From Eric Estevefrom IPnest


ISSCC 2012: Silicon Systems for Sustainability!

ISSCC 2012: Silicon Systems for Sustainability!
by Daniel Nenni on 02-26-2012 at 4:00 pm


What can we do for Earth’s sustainability? Besides sorting our garbage and recycling our lawn clippings? Sustainability must be the paramount theme for the future of human society! Semiconductors for a better life! Well, according to my kids, if you take away their smart phones there is no life!
Continue reading “ISSCC 2012: Silicon Systems for Sustainability!”


Universal Flash Storage: Webinar

Universal Flash Storage: Webinar
by Paul McLellan on 02-24-2012 at 2:24 pm

There has been a general trend for over a decade now towards the use of very fast serial interfaces instead of wide parallel interfaces. This has been driven by a number of different factors ranging from the lack of pins on an SoC, the difficulty of keeping wide parallel interfaces free of skew, limitations on printed circuit board wiring space and so on. Apart from the difficulty of building very fast serial interfaces, almost everything is upside.

JEDEC and MIPI (the Mobile Industry Processor Interface) were both working on high-performance serial I/O standards for data transfers between portable consumer devices. In 2010 these efforts were merged to create the Universal Flash Storage (UFS) standard. UFS is designed to offer a fast, reliable and simple means of supporting storage requirements in portable applications such as smart phones. It supports both embedded and removable card applications. Since it is intended primarily for portable applications, the standard features low power consumption.


Next week Arasan is having two live seminars on UFS and the Arasan UFS solution:

  • UniPro controller
  • M-PHY interface block
  • UFS block
  • UFS and UniPro drivers
  • Software stack
  • Hardware verification IP
  • Hardware validation platform

The live webinar will be on February 28th at 6pm PST (and a useful time for people attending in Asia) and again the next morning February 29th at 10AM PST. Register HERE.


Synopsys at DVCon: tutorial, lunch, keynote, exhibits and more

Synopsys at DVCon: tutorial, lunch, keynote, exhibits and more
by Paul McLellan on 02-24-2012 at 1:10 pm

DVCon is next week, which I’m sure you know already if you are in verification. Of course Synopsys has a rich product portfolio in verification and verification IP (VIP) so is pretty visible at the show.

On Wednesday they are sponsoring lunch. Several Synopsys customers will talk about their view of how the verification landscape is changing. Lunch will be in the Pine/Cedar ballroom from 12.30 onwards. No need to register specially if you are attending DVCon.

Following the lunch, Aart de Geuss, CEO of Synopsys will give the DVCon keynote Systemic Collaboration: Principles for Success in IC Design which looks at the big picture view of how the combination of technology and economics drives everything.

On Thursday, from 1.30 to 3.30 there is a Synopsys tutorial New Levels of Verification IP Productivity for SoC Verification. You need to register here for this if you want to attend. The tutorial is fairly technical and is focused on tnew features added to VIP and how to enable VIP in different environments. There is a demo of debugging at the protocol level (that is, at a much higher level than the actual signals and registers).

Of course Synopsys has a booth in the exhibit hall, number 1105. Exhibits are open 3.30 to 6.30 on Tuesday and 4.30 to 7.00 on Wednesday. You can register for just the exhibits for free.

The main DVCon website is here.

Oh, and while I’m here, Monday evening I’m moderating a panel session Hardware/Software Co-Design from a Software Perspective. All the details are in my earlier blog on the subject here.


Call for Papers: International Gathering for Application Developers!

Call for Papers: International Gathering for Application Developers!
by Daniel Nenni on 02-22-2012 at 8:40 pm

SemiWiki would like to call you, your co-workers, and your company to participate at ERSA Conference in Las Vegas , July 16-19, 2012. I will be there and it would be a pleasure to work with you on this very important event!

ERSA, is Engineering of Reconfigurable Systems and Algorithms. Since this year, the emphasis will be on the commercial and industrial challenges. We will have application developers’ session with many hot topics and featured sections. The aim is to connect researchers and developers, entrepreneurs; as well as developed countries with emerging markets. The industrial content of ERSA is not strictly reconfigurable computing.

The Hot Topic: “Reconfigurable Computing Application Development for Heterogeneous Run-time Environments”. Focus on challenges, tools, available technologies and opportunities when it comes to developing and supporting applications, both academic and commercial, that involve reconfigurable computing technologies across mobile, embedded, and HPC domains.

Featured sections:

“Hardware security and trust in reconfigurable heterogeneous systems”

“Developing IP cores and scalable libraries for heterogeneous systems”

You can arrange a demo, exhibition, seminar, tutorial, etc. Note there are over 2000 attendees together (ERSA is a part of Worldcomp). There are around 400 attendees with strong hardware design background. Thus, there is a high visibility of your company.

Note also that early advertisinghelps people to plan their travel to visit your presentation.

For more details, please visit ERSA website at http://ersaconf.org/ersa12 .

If you might be interested, please contactl: org@ersaconf.org , to discuss further details.

ERSA conference is also available as a Thread at SemiWiki:
http://www.semiwiki.com/forum/f2/international-conference-engineering-reconfigurable-systems-algorithms-1201.html, you can add comments there.

SemiWiki Blog:
http://www.semiwiki.com/forum/content/996-premier-international-gathering-%85-application-developers-ersa.html, forward to colleagues.