Ken Brockof Synopsys presented on how to optimize your SoC design for low power at 40nm, 28nm and 20nm nodes in a webinar today. Ken and I both worked together at Silicon Compilers back in the late 1980’s, the best EDA/IP company that I’ve had the pleasure to join.
The webinar made a brief mention of 14nm and FinFETS but didn’t share any details on 14nm libraries or design methodologies. Continue reading “Webinar on Multi-voltage/VT/Channel Length Libraries”
In 1985 Morris Chang was recruited by the Taiwanese government to help develop the emerging semiconductor industry. In 1986 Morris joined the Hsinchu based non profit research institute ITRI as Chairman and President and launched what would be TSMC’s first semiconductor wafer fabrication plant on the ITRI campus. Taiwan Semiconductor Manufacturing Company Ltd. was officially formed in 1987 as a joint venture between the Taiwan government (21%), Dutch multinational electronics giant Philips (28%), and other private investors.
Without a doubt, TSMC created what is today’s semiconductor foundry business model. While at TI, Morris Chang pioneered the then controversial idea of pricing semiconductors ahead on the cost curve, sacrificing early profits to gain market share to achieve manufacturing yields that would result in greater long-term profits. This pricing model is still the foundation of the fabless semiconductor business model.
Even starting 2 process nodes behind competing semiconductor manufacturers (IDMs), TSMC was able to attract customers. 4-5 years later TSMC was only behind 1 process node and the orders started pouring in. In 10 years TSMC caught up with IDMs and the fabless semiconductor industry blossomed enabling a whole new era of semiconductor design and manufacturing. Today TSMC is the undisputed leader with a reported 49% share of the $30B foundry market segment. UMC is second with just over a 12% share, GlobalFoundries is a close third with 12%, and SMIC is fourth with 4.4%.
As the story goes, Morris Chang made the first TSMC sales calls in 1987 with a single brochure:
TSMC Core Values: Integrity, commitment, innovation, and customer trust.
It is interesting to compare the consistency of this statement with the 1997 TSMC mission statement:
We are building the world’s Virtual Fab! We provide the best quality technology, the greatest capacity and the highest standard of service. We are the most reliable choice as a partner in semiconductor manufacturing.
And again with the vision/mission statement on the TSMC website today:
Our vision is to be the most advanced and largest technology and foundry services provider to fabless companies and IDMs, and in partnership with them, to forge a powerful competitive force in the semiconductor industry. Our mission is to be the trusted technology and capacity provider of the global logic IC industry for years to come.
Also according to the current website TSMC has:
While the original intention of TSMC was to aid the Taiwanese semiconductor design houses, Dr. Morris Chang clearly had much larger aspirations which transformed the global semiconductor industry into what is today a $300B+ business that is mission critical to modern life.
A Brief History of Semiconductors
A Brief History of ASICs
A Brief History of Programmable Devices
A Brief History of the Fabless Semiconductor Industry
A Brief History of TSMC
A Brief History of EDA
A Brief History of Semiconductor IP
A Brief History of SoCs
The High Tech Trial of this Century: Apple vs. Samsung may end up being the catalyzing event that advances the established PC Monopolists known as Wintel (Microsoft and Intel) into leadership positions in the new era known as the Mobile Tsunami. Not a chance you say? Consider that the Apple, Samsung War is one that will not be settled by this or any court but be played out over the next decade in the marketplace among well-oiled vertically integrated supply chain driven hardware manufacturers with very strong market channel presence. Spectacular secular growth will subside in a few years but patent protection and shaving pennies off the cost of Billions of Smartphones and Tablets will matter a lot. How is this likely to play out?
Continue reading “How the Apple-Samsung Duel Will Lead to Wintel 2.0”
Cadence has a series of webinars about their digital flow, focused on 28nm design. It is easy for all of us in the EDA ecosystem to assume that everyone is already doing 20/22nm design, if not 14nm already. But in fact most designs are still being done at 45nm and 65nm; 28nm is still a big challenging step.
One of the tools in the Cadence digital flow is First Encounter, which we used to describe as a floorplanner but is now described as a tool for design exploration and prototyping.
This reminds me of an interesting lesson I learned while I was working at Cadence. We had fallen behind in floorplanning and place & route and so we decided to kick off one of those megaprojects that Cadence used to embark on back then. We called it Integration Ensemble. It would be a everything everyone ever wanted. To make sure, we went and talked to all our major customers and ended up with an insane list of features Integration Ensemble should provide. Since we needed to win the air war too, we briefed Richard Goering (then at EETimes) on Integration Ensemble and he wrote about it as the next great thing, coming real soon now. Well, it turned out the project was so complicated that the schedule was long.
Customers insisted, in particular, that the absolute most important can’t-do-without feature was multiple power supplies, which were starting to go mainstream. Multiple power supplies turn out to be hugely complicated to implement since the power supplies don’t actually show up in the netlist (as an explicit connection to every gate) so a huge number of tools need updating. Anyway, the project dragged out, Richard Goering got annoyed that we’d basically pre-announced something that was so far from delivery (I guess he’s forgiven Cadencethese days). Anyway, eventually it turned out all our customers, the ones who told us that we couldn’t possibly release Integration Ensemble without full multiple power-supply support, were all buying First Encounter (from Silicon Perspective). The irony being that it didn’t support multiple power-supplies. What people really wanted was fast placement and good routing estimation. Listening to your customers is not always good.
As Henry Ford once (reputedly) said, “If I’d asked my customers what they wanted they’d have said a faster horse.” Apple is also famous for not doing market research to find out what people want, on the basis that they won’t know they want, for example, an iPad before they get it. I certainly didn’t.
So Cadence bought Silicon Perspective (in a poorly constructed deal with no cap on the earnouts) for a large sum of money. It was what customers really wanted although they couldn’t articulate it, and they asked for a faster horse instead. So the lesson is that you can’t always trust what your customers tell you they want if it is not guiding incremental improvement to existing tools.
First Encounter remains a key part of the digital implementation flow. It is even more important today than when Cadence purchased it, since there is really no timing number you can rely on if the physical placement has not been done since so delay depends on interconnect more than anything else. Trading off performance, power and price (area) is much trickier than it has ever been and First Encounter is an environment for quickly doing the kind of what-if analysis that must be done early if a design isn’t going to embarrassingly blow out one of its budgets. Nobody wants a cell-phone chip, no matter how cool and sexy, if the standby time is only 4 hours.
Josefina Hobbs, a solutions architect at Synopsys, shows the integration of Synopsys Protocol Analyzer with SpringSoft’s Verdi using the Verdi Interoperability Apps (VIA) which gives open access to the Verdi KDB and FSDB databases. She also demonstrates protocol debug made easy using the Protocol Analyzer. This gives users a graphical view of the transfers, transaction, packets and handshaking of a protocol.
Analyzing the implementation of modern protocols is complex. Transactions on buses are interleaved and so the relationship between the transactions themselves, which ones are happening concurrently, and which bus activity is associated with which transaction is not obvious. The Synopsys Protocol Analyzer makes this clear. In the screenshot below, the leftmost part of the window shows the transactions, the middle part (with the arrow) shows the concurrent transactions and the right part (brown) shows the bus activity. By clicking on any of these, the corresponding other pieces of the puzzle are highlighted.
This makes it easy to unravel the complex behavior of highly interleaved traffic, understand activity, identify bottlenecks and debug anything unexpected. The Protocol Analyzer also links with simulation logfiles, as in the screenshot below, so that timelines in the protocol are linked to the same point in the simulation logfile, making it easy to investigate issues by moving up and down the different levels of abstraction.
Protocol Analyzer can also be linked to SpringSoft’s Verdi so that the raw waveforms can be examined, and still have all the links to the higher level representations, and synchronized timelines, as in the screenshot below.
The video is hosted by SpringSoft here and by Synopsys here.
In April I blogged about using the iPad for schematic capture and SPICE circuit simulation. My conclusion was that the technology was interesting but not quite ready for commercial use. Today I tried out the web-based version using my Google Chrome browser instead of the iPad. Install the Chrome app here or visit www.ischematic.com. This is a very interesting cloud approach of using a web browser instead of a desktop program to create schematics, submit a SPICE simulation to the cloud and view the results in your browser. Continue reading “Schematic Capture and SPICE Simulation in the Cloud”
Even though most of us have witnessed the emergence of the fabless semiconductor industry it is still good to go back and remember how we got to where we are today, to realize that the semiconductors that you now hold in your hand were enabled by the rise of the fabless semiconductor business model. This is the first in a series of blogs I will do on this topic.
When I arrived in Silicon Valley in the early 1980’s the semiconductor industry was vertically segregated. Semiconductor IDM’s (integrated device manufacturers) owned and operated their own manufacturing facilities (Fabs). I worked for Data General, a computer manufacturer, at their fab on Mathidla Avenue in Sunnyvale, California. DG manufactured CPU’s and other chips for their line of Mini-Computers made famous by the Pulitzer Prize winning book “The Soul of a New Machine” by Tracy Kidder.
In order to manage excess capacity and increase the ROI of the capital intensive semiconductor manufacturing process, IDMs started offering smaller firms design, manufacturing, and packaging services. This was the start of the outsourcing revolution that we now call the Fabless Semiconductor Industry.
Dr. Morris Chang worked for one of the aforementioned IDMs (Texas Instruments) and went on to found Taiwan Semiconductor Manufacturing Corporation (TSMC). At TI, Morris Chang worked on a four transistor project where manufacturing was done by IBM. This was one of the early foundry relationships. At the same time Morris pioneered the then controversial idea of pricing semiconductors ahead on the cost curve, sacrificing early profits to gain market share to achieve manufacturing yields that would result in greater long-term profits. Morris also noticed in the early 80’s at TI that top engineers were leaving and forming their own semiconductor companies. Unfortunately the heavy capital requirement of semiconductor manufacturing was a gating factor. The cost back then was $5-10M to start a semiconductor company without manufacturing and $50-100M to start a semiconductor company with manufacturing. Some of these engineers went to the IDMs to get wafers from excess capacity but this was not a customer friendly process and sometimes they were getting wafers from a competitor.
In 1987 TSMC started the foundry business 2 process nodes behind current semiconductor manufacturers (IDMs). 4-5 years later TSMC was only behind 1 node and the orders started pouring in. In 10 years TSMC caught up with IDMs and the fabless semiconductor industry blossomed enabling a whole new era of semiconductor design and manufacturing. In the last 25 years and still today the remaining IDMs are being forced to go fabless or fab-lite at 28nm and below due to cost and daunting technical challenges.
If you look at the most recent ranking from iSuppli it is interesting to see that IDMs Renases, AMD, Infineon, Sony, Freescale, NXP, and Fujitsu are going or already have gone fabless. Also, Fabless companies Qualcomm, Broadcom, NVIDIA, Marvell, and MediaTek are climbing the charts. In ten years how many of these companies (other than the memory companies) will still have fabs?
[TABLE]
|-
! class=”blocksubhead” ! Rank
2011
! class=”blocksubhead” ! Rank
2010
! class=”blocksubhead” ! Company
! class=”blocksubhead” ! Country of origin
! class=”blocksubhead” ! Revenue
(million
$ USD)
! class=”blocksubhead” ! 2011/2010 changes
! class=”blocksubhead” ! Market share
|-
| 1
| 1
| Intel Corporation(1)
| USA
| 49 685
| +23.0%
| 15.9%
|-
| 2
| 2
| Samsung Electronics
| South Korea
| 29 242
| +3.0%
| 9.3%
|-
| 3
| 4
| Texas Instruments(2)
| USA
| 14 081
| +8.4%
| 4.5%
|-
| 4
| 3
| Toshiba Semiconductor
| Japan
| 13 362
| +2.7%
| 4.3%
|-
| 5
| 5
| Renesas Electronics
| Japan
| 11 153
| -6.2%
| 3.6%
|-
| 6
| 9
| Qualcomm(3)
| USA
| 10 080
| +39.9%
| 3.2%
|-
| 7
| 7
| STMicroelectronics
| FranceItaly
| 9 792
| -5.4%
| 3.1%
|-
| 8
| 6
| Hynix
| South Korea
| 8 911
| -14.2%
| 2.8%
|-
| 9
| 8
| Micron Technology
| USA
| 7 344
| -17.3%
| 2.3%
|-
| 10
| 10
| Broadcom
| USA
| 7 153
| +7.0%
| 2.3%
|-
| 11
| 12
| AMD
| USA
| 6 483
| +2.2%
| 2.1%
|-
| 12
| 13
| Infineon Technologies
| Germany
| 5 403
| -14.5%
| 1.7%
|-
| 13
| 14
| Sony
| Japan
| 5 153
| -1.4%
| 1.6%
|-
| 14
| 16
| Freescale Semiconductor
| USA
| 4 465
| +2.5%
| 1.4%
|-
| 15
| 11
| Elpida Memory
| Japan
| 3 854
| -40.2%
| 1.2%
|-
| 16
| 17
| NXP
| Netherlands
| 3 838
| -4.7%
| 1.2%
|-
| 17
| 20
| NVIDIA
| USA
| 3 672
| +14.9%
| 1.2%
|-
| 18
| 18
| Marvell Technology Group
| USA
| 3 448
| -4.4%
| 1.1%
|-
| 19
| 26
| ON Semiconductor(4)
| USA
| 3 423
| +49.4%
| 1.1%
|-
| 20
| 15
| Panasonic
| Japan
| 3 365
| -32.0%
| 1.1%
|-
| 21
| 21
| Rohm Semiconductor
| Japan
| 3 187
| +2.2%
| 1.0%
|-
| 22
| 19
| MediaTek
| Taiwan
| 2 952
| -16.9%
| 0.9%
|-
| 23
| 28
| Nichia
| Japan
| 2 936
| +34.1%
| 0.9%
|-
| 24
| 23
| Analog Devices
| USA
| 2 846
| -0.6%
| 0.9%
|-
| 25
| 22
| Fujitsu Semiconductors
| Japan
| 2 742
| -0.5%
| 0.9%
|-
| colspan=”4″ | All Other companies
| 95 610
| -0.5%
| 30.7%
|-
| colspan=”4″ | TOTAL
| 311 360
| 1.3%
| 100.0%
|-
A Brief History of Semiconductors
A Brief History of ASICs
A Brief History of Programmable Devices
A Brief History of the Fabless Semiconductor Industry
A Brief History of TSMC
A Brief History of EDA
A Brief History of Semiconductor IP
A Brief History of SoCs
Consolidation continues in the EDA industry with Synopsys announcing today that they acquired Ciranova, a provider of software to automate custom IC layout. Remember that Synopsys invested in Ciranova back in March 2008 and September 2010 (along with Intel Capital, Mentor Graphics and Alloy Ventures), so this deal has some history to it. Ciranova touts Agile Layout:
Continue reading “Synopsys Acquires Ciranova”
Not yet a year into Rory Read’s term and the AMD board must be considering that the value of the x86 patents and engineering talent is worth much more than the stocks $3B valuation and easier to fathom putting on the auction block than continuing to sell $25 processors into the back channels of China and the Developing World. As I read through the earnings conference call notes, it reminded me of what the end times looked like at Cyrix as processors viewed as obsolete were unsellable at any price. Inventory stacked up in the warehouse with no prospects of a game changer on the horizon. The stock price is now $1 less than the $5 bar that I mentioned last year was a psychological point at which it becomes attractive for some well financed suitors like Qualcomm, nVidia, Microsoft or Samsung to start sizing up as an acquisition. It’s the least they could do to get Intel’s lawyers busy conjuring up various legal counter maneuvers.
Microsoft’s recent announcement of the Surface Tablet could be considered as an affront to its OEM customers or it could be recognized for what the future truly demands: an all in one device that gives customers full access to legacy applications as well as everything the cloud has the potential to be. Theses devices will carry the brand Apple, Samsung, Amazon, Google or Microsoft but not HP or Dell. Apple has forced the vertical model (Applications, cloud and hardware) on the industry and only Samsung is close to competing – and only on the hardware side.
Will Microsoft take on its own processor team like Apple? My bet is that they hesitate in order to not upset Intel or Qualcomm who appear to be the best positioned in the Mobile Tsunami Semiconductor markets coming from two opposing directions. Squeezed in the middle are AMD, nVidia and many of the rest of the ARM camp. Retreating ARMies are unexpected but coming.
The model of eighteen months ago was that of an army of ARM licensed fabless vendors attacking Intel from all sides to win the mobile battle. The PC market has remained resilient and Intel has been able to leverage leading edge process technology to lower power and integrate the all important graphics functionality and thus put AMD and nVidia against the wall in the area they must generate revenue to fund the R&D to survive until tomorrow.
Tomorrow is here thanks to Ultrabooks and Ivy Bridge. Intel’s newest CPU will reach 50% of unit output this quarter and Haswell the successor is arriving in 9 months. Consolidation of AMD within nVidia would allow relieve price pressure in the graphics market and give nVidia an x86 play in the client and server space. If only nVidia was going great guns like in 2007 when the stock approached $40 and was valued at $25B. It would be a done deal. Now, with Intel’s 22nm ramping at great speed there is not much time for nVidia to make a play for AMD because other scenarios are arising that could be more attractive.
Samsung’s acquisition of CSR was a surprise in terms of boldness but gives one a sense of how Samsung and Intel are setting about to load up their IP portfolios as they head down the path of 450mm. Without having all the Mobile Tsunami IP pieces in place, why would one aggressively invest in 450mm and vise versa. Take this one step further and consider: can Samsung compete with Intel without x86. I contend not. If Intel has no x86 competitor than it will go into heavy skimming mode in the mobile client market as it is now doing in Servers. Without a significant AMD presence, Intel has had the luxury of raising server processor prices dramatically. The high growth data center and legacy corporate Wintel market gives Intel the liberty of tossing FREE Atom grenades into the smartphone and tablet markets to severely damage Samsung’s mobile processor revenue.
The wildcard that is coming into play this year and of which we will not fully understand is the magnitude of Qualcomm’s 4G LTE ramp. Alarm bells went off in April when management signaled that demand had greatly exceeded planned supply. Manufacturing efforts were expanded to increase production at four foundries and as of the July earnings call management stated that balance would not be achieved until years end. But then lets not forget the Chinese New Year selling season comes soon after Christmas. Mark me down for balance to arrive in March 2013.
Analysts should be on the lookout for the trend line that places a very high relative value on the communications pieces of the Mobile Tsunami platform relative to the processor and graphics. Intel is aware of this and furthermore recognizes that 4G LTE will likely be a standard feature on many ultrabooks next year. I was very surprised that Apple did not offer 4G LTE as an option to the recently launched MAC Air and MAC Book Pro notebooks.
If Qualcomm believes that they can maintain a leadership position over Intel in the communications space then they need to offer an x86 version of snapdragon directed at the ultrabook and Tablet markets, which within 3 years will be well over 250MU in TAM. The ASPs in this market for Qualcomm would be much higher than what it can achieve in Smartphones and what AMD can ever achieve going it alone. Think of the upside that Qualcomm could achieve if they sold 100MU x86 processors + baseband platforms at $100 (Intel’s average Mobile CPU ASP). Think that is high? Note that Intel’s Ivy Bridge ULV (Ultra Low Voltage) processors targeted at the Ultrabook space sell above $200 today and will average well north of $100 when the whole line is released.
While AMD can continue to be a player in the x86 market, it is likely to be diminished over time as Intel’s process lead grows. The traditional thought that Intel is 80% and AMD is 20% of the market is going to change as Intel no longer is hamstrung by antitrust from servicing 90 or even 95% of the PC market because the compute ecosystem has expanded into smartphones and tablets. AMD’s challenge is to convince one of the many well-funded suitors that x86 is a requisite technology to have in a future driven by the Mobile Tsunami and 450mm fabs.
Full Disclosure: I am Long AAPL, INTC, QCOM, ALTR
The SystemVerilog standard defines an X as an “unknown” value which is used to represent when simulation cannot definitely resolve a signal to a “1”, a “0”, or a “Z”. Synthesis, on the other hand, defines an X as a “don’t care”, enabling greater flexibility and optimization. Unfortunately, Verilog RTL simulation semantics often mask propagation of an unknown value by converting the unknown to a known, while gate-level simulations show additional Xs that will not exist in real hardware. The result is that bugs get masked in RTL simulation, and while they show up at the gate level, time consuming iterations between simulation and synthesis are required to debug and resolve them. Resolving differences between gate and RTL simulation results is painful because synthesized logic is less familiar to the user, and Xs make correlation between the two harder. Unwarranted X-propagation thus proves costly, causes painful debug, and sometimes allows functional bugs to slip through to silicon.
Continued increases in SOC integration and the interaction of blocks in various states of power management are exacerbating the X problem. In simulation, the X value is assigned to all memory elements by default. While hardware resets can be used to initialize registers to known values, resetting every flop or latch is not practical because of routing overhead. For synchronous resets, synthesis tools typically club these with data-path signals, thereby losing the distinction between X-free logic and X-prone logic. This in turn causes unwarranted X-propagation during the reset simulation phase. State-of-the-art low power designs have additional sources of Xs with the additional complexity that they manifest dynamically rather than only during chip power up.
Lisa Piper, from Real Intent, presented on this topic at DVCon 2012 and she described a flow in her paper that mitigates X-issues. The flow is reproduced here.
She describes a solution to the X-propagation problem that is part technology and part methodology. The flow brings together structural analysis, formal analysis, and simulation in a way that addresses all the problems and can be scaled. In the figure above, it shows the use model for the design engineer and the verification engineer. The solution is static analysis centered for the design engineer and is primarily simulation-based for the verification engineer. Also, the designer centric flow is preventative in nature while the verification flow is intended to identify and debug issues.
She also gave a video interview on her presentation at DVCon 2012 and you can watch it here.
