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TSMC versus Intel at 20nm!

TSMC versus Intel at 20nm!
by Daniel Nenni on 04-24-2012 at 7:00 pm
Categories: Foundries, Intel Foundry, TSMC
10 Comments

The biggest news out of the TSMC Symposium last week was the 20nm update. Lots of debate and speculation, just why is TSMC releasing one version of 20nm (20nm SoC) versus multiple versions like in 40nm (LP, G, LPG) and 28nm (HP, HPM, HPL, LP)? Here are my thoughts, I would also be interested in your feedback in the comment section. This really is a big change for both TSMC and the foundry business so it is certainly worth discussing.

Morris Chang did a candid interview in early January discussing Intel as a competitor. Morris is a very clever man, a master at the card game bridge, so you can really read a lot into of what he has said here:

“TSMC’s technologies and performance have reached quite a high level, bringing us into contact with different rivals,” Chang said

The high level is volumes of mobile chips, volumes that will certainly rival Intel’s microprocessor business in the not too distant future.

“The competitors we face are Samsung Electronics Co. and GlobalFoundries Inc., with Intel standing ‘behind a veil’ because it is a rival against many of our customers,” Chang said, adding that these TSMC customers include integrated circuit designers and integrated device manufacturers.

The strategic positioning begins! TSMC is a pure-play foundry and collaborates with customers versus IDMs (Intel/Samsung) that competes with customers. The Apple/Samsung legal drama is a glaring example of this.

At the Symposium, Morris mentioned R&D expenses of TSMC versus Intel and Samsung, the difference being, TSMC collaborates with customers/partners and leverages R&D expenses. So the equation looks like this:

Top 10 TSMC customers R&D expenses + TSMC R&D expenses > Intel + Samsung R&D expenses

Another interesting quote from the article:

Samsung and GlobalFoundries are newcomers in the industry, Chang said, and suggested that TSMC’s customers should diversify their foundry sources rather than rely on TSMC only.

Which is interesting advice coming from the Chairman of TSMC. It is certainly a message to TSMC employees that second source competition is always a threat so even with 50%+ market share there is no time to rest on previous accomplishments. Notice he does not mention Intel here. Of course Morris followed that quote with something of purpose:

“All of our customers rely on TSMC in foundry production, and Intel relies on its own foundry plants,” he said. “If our technologies are not improved enough and Intel keeps improving its technologies, our customers’ products will lose competitiveness to those of Intel. It’s horrible to imagine the outcome.”

Another competitive shot at Intel! Well played Mr Chairman. I wish I could use a bridge analogy here but I don’t play bridge. Morris ended the interview with another shot at Intel:

“TSMC will stand behind our customers and cooperate with them. The battlefield between our customers and Intel is where we compete against Intel,” he added.

So it is the fabless companies, ARM, and TSMC against Intel. I like those odds!

Back to 20nm. Intel has one version of 22nm so to better compete with Intel TSMC will focus all resources on a single SoC optimized version of 20nm, simple as that. TSMC may also offer FinFets at 20nm so customers will have a choice between planar and FinFet transistor implementations, something that Intel does not offer. It is also about capacity. TSMC’s CAPEX hike is all about 20nm and with one S0C optimized version there won’t be the shortages we see at 28nm.

Sound reasonable? Please use the comment section for further analysis.

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Mergers and Acquisitions in EDA should spark Innovation and Start ups

Mergers and Acquisitions in EDA should spark Innovation and Start ups
by Rich Goldstein on 04-23-2012 at 8:13 pm
Categories: EDA
5 Comments

With the recent closure of the Synopsys Magma deal and the economy showing a bit of uptick and some positive outlook compared to the last 3-4 years, I believe it’s time for some of the creative minds that find themselves looking for new opportunity to consider starting their own point tool as well as IP companies.

Many of these people are some of the brightest in technology worldwide yet will discover some new realities of the current job market. The first is that openings in EDA and related areas such as IP are few and far between; the other being that the industries in the Valley that are growing and hiring rapidly don’t have the interest or intelligence to open their doors to veterans of areas besides their own. This is a grim reality of the new wave of mobile, cloud, SaaS, and enterprise companies that are garnering the funds from VC’s and hiring as if it were the boom all over again. I have experienced this myself more times than I can even count in the last year or so as Ive attempted to break new ground and transfer my skills in recruiting for software start ups into these areas, just to be ignored or often times told that they want the “7-10 year” candidates that are hungry and connected to people in their space and grew up using social media and mobile applications in their daily lives at least beginning in college if not sooner.

Intellectual Property (IP) is another avenue for the jobseeker to explore; perhaps a lower cost entrée into starting a smaller company that can realize success and notoriety sooner than building a software tool from the ground floor. There have been recent successes with design services companies that own their own IP and were able to be recognized as a business worthy of acquisition

I am not a technologist, I refer to myself as “buzzword compatible”, but I do understand as the geometries of the circuits get smaller and smaller there are new challenges that need to be addressed. Through the ups and down of the economies and the consolidations that have taken place, the fact still remains that innovation will come from smaller teams of people with an eye on invention as opposed to corporate security and politics. And these pioneers will in fact resurrect the cycle that we’ve all relied on over the years of growth via acquisition. There are private avenues of funding and friends of families and people who have tasted success that can be instrumental in helping these new entrepreneurs.
——————————————————————————————————————————————
Richard Goldstein has been a recruiter and advisor to startups in EDA and IP since 1984 and has placed many of the executives and leaders at startups within this industry. He has also held corporate contract recruiting positions inside companies such as Magma Design Automation, Kilopass Technology, and Xilinx.

Rich@dacsearch.com


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DAC 2012 Must-See! Hogan’s Heros: Learning from Apple

DAC 2012 Must-See! Hogan’s Heros: Learning from Apple
by Holly Stump on 04-23-2012 at 6:30 pm
Categories: EDA, Events


Who doesn’t love the perennial Hogan’s Heros panel at DAC? Always provocative and illuminating, for technologists, entrepreneurs, and strategists.

At DAC 2012, Jim Hogan’s panel is “Learning from Apple”:Apple. We admire their devices, worship their creators and praisetheir stock in our portfolios. Apple is synonymous with creative thinking, new opportunities, perseverance and wild success. Along the road, Apple set new technical and business standards. But how much has the electronics industry, in particular EDA, “where electronics begins,” learned from Apple? It depends.

Lets ask Jim…..What have we FAILED to learn from Apple?

1. Technology vs Customers?

It’s not about being leading edge technology. It’s about the user experience: display, power until charge, applications, and content: graphics/video. A relentless push for higher quality user experience – at minimum system cost. And feature convergence – video, voice, data, audio –in every consumer device.

Job’s Law: “Never compromise the user experience.”I know for the iPAD, Jobs had five guys working directly for him to seek out and understand how people used devices, to better spec the PAD and later projects.

They don’t do things right on the leading edge, but just behind it. They also then beat the living hell out of their supply chain for cost savings, and spend it on things that matter, like displays (check out the brilliant iPAD 3 display, and new power supply spec!)

2. Business and Pricing Models? Market Excitement / Charisma / Image?

Apple business model: give people a design that is useful and trendy and you can demand a premium.And Apple is well-branded. (In the old days, Apple even paid a guy in agarage to stamp an Apple logo on every DRAM…DRAM that no one ever even saw…that’s Apple!) We buy Apple because the darn things always work and are very reliable, the apps themselves work on your device and all other Apple devices. The Brand is King. They can slap an Apple on anything and sell it, i.e. iTunes.

The i4 repositioning is another good example. The price was lowered to $99 (through carriers) thus bringing the Apple experience to many people who had not yet bought. For the carriers, it attracted new subscribers consuming their data plans.

And, EDA needs to think more about adjacent markets. Apple is the number one distributor of music in the world (surpassing Wal-Mart last year.) Think about Siri and its possible evolution….

3. Managing Wall Street?

The best way to manage Wall St. is, show 25% top growth and 25% bottom line growth. Apple showed 100% top line in 2011 and 150% bottom line. Thus they are the most valuable on earth, surpassing Exxon in March. We are indeed in the information age and energy has moved down a notch.

Jim,who are your panelists for “Learning from Apple”?

We have Dr. Jan M. Rabaey, Professor at UC Berkeley, who is currently the scientific co-director of the Berkeley Wireless Research Center and serves on Technical Advisory Boards for a wide range of companies. Dr. Jack Guedj is President and CEO at Tensilica, Inc. He also ran Magnum Semiconductor, which he spun out of Cirrus Logic. Tom Collopy, CTO at Aggios, was VP of Engineering at Qualcomm responsible for the Smartphone/Smartbook market, including Snapdragon (Smartphones, Android.)

OK,Jim, we love Apple! How much is in YOUR portfolio?

(Laughter….)

Click for more information on Hogan’s Heros at DAC 2012

Jim Hogan, Private Investor
Jim is currently the managing partner of Vista Ventures, LLC. Jim has worked in the semiconductor design and manufacturing industry for more than 35 years gaining experience as a senior executive in electronic design automation, semiconductor intellectual property, semiconductor equipment, and fabrication companies. Mr. Hogan holds a B.A degree in mathematics, a B.S. degree in computer science and an M.B.A., all from San Jose State University. He serves on the Board of Advisors at San Jose State’s School of Engineering, and on several private companies’ boards of directors: Altos (acquired by Cadence May 2011), AutoESL (acquired by Xilinx February 2011), Scoperta, CLK, Tela Innovations and Shocking Technologies, Solido and Sonics. Additionally, Jim serves as a strategic advisor to several private and public technology companies.

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Channel Routing Memories

Channel Routing Memories
by Paul McLellan on 04-23-2012 at 1:12 pm
Categories: Uncategorized
3 Comments

Back in the early days of ASIC when we had just two and then (wow!) three layers of metal, place and route was done by putting the standard cells in rows with gaps between them and then using a specialized router to do the interconnection. It would use one layer of metal horizontally and one vertically and avoid jogs. This was called a channel router. For digital place and route today we have lots more layers of metal and we are not restricted to keeping our routing contained in the channel.

But memories are different. They have fewer layers of metal and end up with long narrow areas between the memory arrays and around the outside. Memories are also early into new processes and the first that have to deal with more restricted design rules. As a result, there is a need for routing this sort of area with long jogless nets, just like in the old days of 3-layer metal ASICs.

Normal digital place and route, or a shape-based router, does not give the right results, producing too many jogs, too many vias and is not controllable enough by the designer. But a straightforward implementation of a 1980s channel router isn’t adequate either. The connection points are inside the blocks, care needs to be taken feeding signals through the blocks. What is required is a smart way to create the pins that is aware of just how the channel router is going to behave. Otherwise it is too easy to create designs where one pin blocks another route (remember, we are avoiding jogs and vias). The router needs to drive the pin placement.

Pulsic’s spine and stitch router does this. The pin placement is driven by the router so that eventually everything can be routed with long straight wires. There is an example below, although, of course, a real example would likely involve thousands of nets. The spine router with pin placement can do in 30 minutes what used to take a designer doing it manually 3 weeks. Using intelligent pin sorting the router will typically complete over 95% of the nets leaving just a handful where the designer needs to guide the tradeoffs involved.


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AMS Design using Co-Simulation

AMS Design using Co-Simulation
by Daniel Payne on 04-23-2012 at 11:13 am
Categories: Aldec, EDA, Tanner EDA
1 Comment

The big three vendors in EDA offer AMS simulation tools but what about simulation choices from other EDA vendors?

It turns out there are two privately held EDA companies that have done business since the 1980’s and have just integrated a Verilog A simulator with a SPICE circuit simulator. The two companies are Aldec with a Verilog A simulator and Tanner EDA with a SPICE circuit simulator. To learn more about this AMS simulation capability I reviewed a webinar from March 8th, 2012.

Jeff Miller presented for Tanner EDA and Jerry Kaczynski for Aldec. Each company has over 30,000 EDA licenses in use worldwide.

The AMS tool flow starts with design capture in S-Edit then an automated netlist out to T-Spice AMS which uses Verilog A in Aldec’s Riveria PRO and SPICE in Tanner’s T-Spice:

Waveforms for analog signals are viewed in the Tanner viewer, while digital signals are viewed in the Aldec tool:

With Riviera-PRO the digital simulator features:

  • Verilog, VHDL, SystemVerilog, SystemC
  • Assertion-based verification
  • Command line or GUI operation
  • Code and functional coverage
  • Transaction-level debugging
  • APIs to communicate
  • Runs on Linux, Windows XP, Vista and Windows 7

This is a co-simulation approach, not a single kernel approach like that offered by Synopsys, Cadence and Mentor. For most AMS netlists the SPICE simulation will usually limit the run time.

The demo showed an ADC design where capture is done in Tanner’s S-Edit tool then netlisted. S-Edit automatically detects what block is netlisted for Spice and for Digital. T-Spice is run on the netlist which then invokes the digital simulator, Riviera-PRO.

Q&A
Q: Does the logic netlist run through the T-Spice input file buffer, causing capacity issues?
A: There isn’t a character limit to T-Spice parsing, so we don’t know of any capacity issues.

Q: Is it better to use a 64 or 32 bit OS for my AMS simulation?
A: It really depends on your memory requirements. For large memory requirements then you could run out of memory space on a 32 bit OS, so then use the 64 bit version on Linux or Windows for Riveria. On the SPICE side you can also use either 32 or 64 bit versions.

Q: Which OS versions are supported for this AMS co-simulation?
A: Windows 32 bit or 64 bit, Linux only 32 bit on the SPICE side.

Q: If I have a mixed signal design can I independently specify a Verilog and SPICE view without using two instance names?
A: Yes, you can specify per instance if this cell is Verilog or SPICE view.

Q: Does this co-simulation work with Active-HDL?
A: Use Riviera PRO for this AMS co-simulation for now. Active-HDL could be added in the future if there’s enough demand, it’s not a technical issue just a demand issue.

Summary
If you already own a Tanner EDA or Aldec simulator and want to start doing AMS simulation for IC designs then this affordable co-simulation approach should be considered. I’d expect to see in the product roadmap a few useful features like:

  • Unified waveform viewer, instead of two viewers
  • Cross-probing between schematic, source and wave form viewer
  • Interactive simulation where you can start, stop, measure and continue

The webinar is online here.

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UMC Wins Qualcomm 28nm Second Source Contract!

UMC Wins Qualcomm 28nm Second Source Contract!
by Daniel Nenni on 04-22-2012 at 7:00 pm
Categories: Uncategorized
11 Comments

This is common knowledge in Taiwan but apparently the guys over at SemiAccurate.com did not get the memo. I hear a name change is in the works: www.RarelyAccurate.com. Remember, these are the same clairvoyants who said TSMC shut down 28nm which as we now know is absolutely false. The QCOM elite stay at the Hsinchu Royal Hotel which is 5 minutes away from UMC HQ. The Royal is also my hangout so I see and hear these guys quite a bit.

TSMC absolutely did NOT halt 28nm production!

This article is titled “UMC Wins Qualcomm’s 28nm Node Contract” but what they mean is second source contract. We all know QCOM is at TSMC 28nm, as is everyone else. QCOM mostly uses the TSMC 28nm LP process for both low power and low cost. TSMC and UMC are the only foundries today with both a 28nm LP (poly/oxynitride) process and 28nm HLP (high k metal gate) processes. GlobalFoundries only has 28nm HLP, so sorry Charlie, QCOM will NOT be “moving majority of production to GlobalFoundries” anytime soon.

If you look through the UMC 2010 annual report you will see that UMC has a handful of customers that do the bulk of the business. Leading those is Texas Instruments. TI went fab-lite 5 years ago and chose TSMC for first source and UMC for second source. First tape-outs go through TSMC because TSMC is always first to market with a new node. Once UMC ramps production the fight for the best wafer price begins and that will go to UMC, which is why TSMC’s profit margins are 31% versus UMC’s 9%.

Does TSMC enjoy doing all of the bleeding edge work only to get shut out when serious production starts? Of course not, it is very frustrating but second sourcing is the nature of the fabless semiconductor business.

TSMC 28nm Yield Explained!

Qualcomm and Broadcom are different as they buy wafers from multiple fabs at 40nm and above: TSMC, UMC, SMIC, and GFI, because that is the way they do business. Other companies like Altera, Nvidia, and Oracle, single source at TSMC which is a much more intimate relationship but capacity can always bite you in the ass which at 28nm it certainly did.

One thing you have to understand is that the Fabless – Foundry relationship is hugely contractual. Fabless companies sign up for a certain wafer count in a defined time period and there are penalties on both sides if it is not met. To my knowledge, based on what I have read and heard at the Royal Hotel, TSMC has fulfilledALL contractual commitments on 28nm. Don’t believe me? Ask that question on the next QCOM or NVDA conference call. “Did TSMC meet the contracted wafer delivery numbers at 28nm thus far?”

The Truth of TSMC 28nm Yield!

What happens if the Fabless Company needs more wafers than in the contract? That is called a “Hot Lot” or a rush order which they pay a premium for, up to 50% I have heard. Correct me if you know otherwise.

20nm will be more of the same. The TSMC 20nm first customer list will be the same as 28nm plus maybe Apple. The same yield drama will ensue only to be debunked. Some will stay at TSMC 20nm, some will second and third source if they can. TSMC’s recent CAPEX increase is for 20nm capacity so the race is definitely on!


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Audio IP Subsystems Made Easy with a Complete, SoC-Ready Solution

Audio IP Subsystems Made Easy with a Complete, SoC-Ready Solution
by Eric Esteve on 04-22-2012 at 12:22 pm
Categories: IP, Synopsys

After the launch of ARC based complete sound system IP by Synopsys last month, which could be the effective starting point for subsystem IP offering, providing the initiative will be successful (this was not really the case in the past, as we discussed it in our blog), the company proposes a webinar focusing on:

  • The growing complexity of audio requirements for advanced SoC designs
  • How a pre-verified, integrated audio IP subsystem solution, consisting of hardware, software and prototypes reduces integration effort, lowers risk and accelerates time-to-market
  • The feature requirements for implementing audio functionality into a SoC
  • How configuration of a complete audio IP subsystem can be done in hours

Considering that the trend towards internet-connected consumer devices is driving an increase in the audio requirements and complexity of today’s SoCs, and that these designs need to support elements such as multi-channel, high-definition audio formats as well as plug seamlessly into the host application software, Synopsys is offering a pre-verified, although configurable solution. This allows designers to integrate dedicated audio subsystems to offload the audio processing from the host processor, thus reducing design complexity and improving performance and efficiency of the SoC.

To register to this webinar, just go here, and remind that it will be held on Thursday, April 26.

As far as I am concerned, I will carefully monitor this initiative from Synopsys, as the potential move from a single IP function to a complete subsystem, looking very attractive –in theory- may change the IP market behavior as we know it today. Would the initiative be successful, the market changes could be deep, offering opportunities to new comers to enter and generating partnership between small vendors (like it was the case between PHY and Controller IP vendors in the 2005-2010, but unfortunately not yielding as expected). It could be also an opportunity for one of the two others to attack again the IP market, but with a renewed strategy… We will se.

From Eric Estevefrom IPnest

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Flexible ASIC Strategy!

Flexible ASIC Strategy!
by Daniel Nenni on 04-21-2012 at 9:00 pm
Categories: Uncategorized
1 Comment

During my last Taiwan trip I also spent time with Global Unichip. Clearly, in order for the semiconductor industry to thrive we must enable design starts. With the rising costs and complexity of semiconductor design and manufacturing this is a much greater challenge which is why I’m so interested in GUC, for the greater good of the semiconductor ecosystem.

GLOBAL UNICHIP CORP. (GUC), the Flexible ASIC Leader[SUP]TM[/SUP] is based in Taiwan and provides a comprehensive suite of The Flexible ASIC Services[SUP]TM[/SUP] that meet the unique business and technology requirements of today’s innovative technology company.

The design services businesses really took off with the likes of eSilicon, Open-Silicon, and a dozen others, enabling the outsourcing of semiconductor design and operations. Unfortunately that is a very margin centric business which, as it turns out, is very hard to scale. Single digit margins also limit exit strategies which will kill future investment and growth.

GUC provides an unmatched combination of advanced technology, low power and embedded CPU design capabilities and production knowhow through close partnership with TSMC and major packaging and testing companies that are ideal for advanced communications, computing and consumer electronics ASIC applications. The company has the proven ability to maximize the power/ performance sweet spot while delivering the fastest possible time-to-market. GUC’s uncompromising performance provides the absolute best power, speed, quality, yield and on-time delivery. Our goal is to innovate and deliver world class Flexible ASIC Services that elevate IC visionaries to the next level of leadership in their markets.

How is the Full Service Flexible ASIC strategy different? Simple, it’s a matter of changing with the times. Risk adverse start-up fabless companies are no longer a growth market. Medium to large fabless semiconductor companies are where the growth is. Designing high speed semiconductors in the third dimension is Flexible ASIC. Differentiation through custom IP is Flexible ASIC. Providing a higher level of IP abstraction is Flexible ASIC. The future of ASIC is Flexible ASIC.

“We thought it appropriate to adopt the ‘guc-asic.com’ domain name because it more accurately reflects GUC’s positioning and how our customers are beginning to view us,” said Jim Lai, President of GUC. “The name is also very easy to remember
and very easy to type, which clearly offers some major advantages for our shareholders, customers and partners.”

GUC made some interesting changes last week, a new URL (www.guc-asic.com) and a new logo in support of the Flexible ASIC strategy. Honestly, the old logo made me dizzy so this is a good thing. Search engine optimization is also important and the URL is a key part of SEO. Most importantly it sends a strong message to competitors, partners, investors, and customers. Global Unichip Corp. (GUC), the Flexible ASIC LeaderTM, has a scalable business model.

Based in Hsin-chu, Taiwan GUC has developed a global reputation with a presence in China, Europe, Japan, Korea, and North America. GUC is publicly traded on the Taiwan Stock Exchange under the symbol 3443.


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Milestones to Building a Successful Technology Software Company

Milestones to Building a Successful Technology Software Company
by Daniel Payne on 04-19-2012 at 11:04 pm
Categories: EDA, Events

May 31, 2012 at Silicon Valley Bank, Santa Clara, CA

Join us on May 31, 2012 for the first in a series of conversations exploring concepts and best practices for emerging companies. The first conversation will outline the critical milestones which must be conquered to take a start-up from early stages to a strong, growing, sustainable business. [Additional information]
The three participants in this conversation have had serial success with navigating companies through concept to successful liquidity events. The content is geared to founders and executives of software, systems, and semiconductor companies, as well as others interested in getting a birds-eye view of what companies face as they various stages of success.

Jim Hogan, Private Investor
Dean Drako, President and CEO, IC Manage
Ravi Subramanian, President and CEO, Berkeley Design Automation

Date & Time:
Thursday, May 31[SUP]st[/SUP] 2012
6:00 PM Reception
7:00 PM Emerging Companies Conversation
8:00 PM Q&A

Location:
Thursday, May 31[SUP]st[/SUP] 2012
6:00 PM Reception
7:00 PM Emerging Companies Conversation
8:00 PM Q&A

Cost:
There is no charge for this event. Seating is limited, so please register early!

Organized by:

Steve Pollock, Chairman, EDAC Emerging Companies Committee
Georgia Marszalek, Valley PR
Gloria Nichols, Launch Marketing

Sponsored by:
Chip Estimate
EDA Consortium
Silicon Valley Bank