wide 1

Synopsys Challenges with SpringSoft Acquisition

Synopsys Challenges with SpringSoft Acquisition
by Daniel Payne on 08-03-2012 at 12:41 pm

Another week in EDA and yet another acquisition by Synopsys as they buy SpringSoft this time for $406 million in cash. Paul McLellan wrote a good blog on this merger too.

Last week I blogged about the product overlap and integration challenges that Synopsys faces with the acquisition of Ciranova
.

Let’s take a look at the IC entry and layout products from SpringSoft and how they fit into the tools that Synopsys already owns:
Continue reading “Synopsys Challenges with SpringSoft Acquisition”


Synopsys Aquires Springsoft

Synopsys Aquires Springsoft
by Paul McLellan on 08-03-2012 at 12:07 pm

Today it was announced that Synopsys is acquiring SpringSoft for $406 million dollars ($12.2B Taiwanese). Coincidentally, I was in SpringSoft’s US office yesterday to talk about how Laker is being used for 20nm design. More of that later. But there was certainly nothing to indicate that anyone there was expecting this.

Last week Synopsys acquired Ciranova. They had some good technology for analog automation but it seems clear with this acquisition that Synopsys just wanted to ensure that the Ciranova PyCell technology remained viable and found a home. With the acquisition of Laker, Synopsys has a much stronger position in layout in general and analog automation in particular.

The other part of SpringSoft is the Verdi verification environment. In another odd coincidence, just a few days ago I wrote about the integration of the Synopsys Protocol Analyzer with SpringSoft’s Verdi through the open VIA interfaces that Verdi has provided for about a year now. I guess that integration like that might get a bit tighter going forward.

The verification market is split three ways with Mentor, Cadence and Synopsys all having strong positions. Verdi strengthens Synopsys’s position, of course, but it doesn’t really upset the balance of power enough to put them convincingly ahead. Plus, verification is one of the areas where customers seem to like to have more than one solution, both since the different solutions have different capabilities and to give a stronger negotiating position. Many customers use Verdi with Cadence and Mentor simulators so whether Verdi grows or shrinks as a business due to the acquisition is an open question.

The layout market is the one where this might make a big difference. Cadence has had a dominant franchise in this market with their Virtuoso environment. The lock-in has been the thousands of lines of SKILL code that customers have written and that nobody else can support. One thing I learned yesterday is that 20nm is so different that most of that SKILL is irrelevant and even PDKs are less important since there is so little flexibility about how transistors can be created. The 20nm changes along with the newish analog automation has created an opportunity for SpringSoft’s Laker. Laker has been very strong in Taiwan (SpringSoft is headquartered there) but has recently started to get traction in more and more big name companies outside of its home base. With the Synopsys name and sales channel this could really even up the layout playing field.

Or maybe not. One of the weird things about EDA is that the big sales channels cannot sell products that the customer isn’t asking for. So much of their revenue comes from reselling what they sold last time they don’t like to jeopardize the big deal with a product where they have to work to displace an incumbent. When Cadence acquired Ambit’s synthesis, the sales channel refused to sell it and continued with their strategy of “concede synthesis to Synopsys and try and get the rest of the budget.” Let’s see how good Synopsys’s sales force is at displacing Cadence’s Virtuoso of if they adopt a “concede layout to Cadence and try and get the rest of the budget.”

Since this doesn’t give Synopsys a dominant position in functional verification and since Cadence is the dominant layout incumbent, not Synopsys, I can’t see that this deal is likely to get major regulatory oversight. It is far less contentious than Synopsys acquiring Magma, giving them a second place and route solution, and Finesim, and Tekton static timing, areas where Synopsys was already the leader.

In yet another odd coincidence, the first I knew about the acquisition is that I got an email from Tony Trousset of Atlas Technology Ventures that they had acted as advisers to SpringSoft in the transaction. I’ve not heard from Tony for ages, but he was at Deutche Bank when he was one of our advisers when we sold Compass while I was CEO (eventually to Avant!) back in 1998.


Arteris FlexNoC penetration increase… everywhere

Arteris FlexNoC penetration increase… everywhere
by Eric Esteve on 08-02-2012 at 9:00 pm

The need for Network-on-Chip (NoC) has appeared at the time where chip makers realized that they could really integrate a complete system on a single die to build a System-on-Chip (SoC). At the early times (1995-2005), the so-call NoC IP suppliers were in fact proposing a crossbar switch, a pretty old concept initially developed for Telecom applications where you had to switch between multiple users, every signal (user) having the same priority.

When the chip makers have realized that Moore’ law was allowing complex SoC development, they understood that such development was only possible if they could assemble existing IP blocks (externally sourced or internally designed). Integrating various IP, each of these being a complete functional block, in a chip lead to the next problem to solve: how to efficiently interconnect these functions together and with the CPU (GPU)? Then came the need for something more efficient than just a crossbar switch, a kind of “intelligent” interconnect system, say a Network, and because it’s to be internal, a Network on Chip: the NoC.

The above picture illustrate the move from the design of a Video Engine (in the 1990…), requiring a Village type of traffic when compared with a SoC design of the 2005 (OMAP4 from TI) requiring a City Traffic infrastructure. If we try to be more specific (and scientific!) we can say that a NoC is similar to a modern telecommunications network, using digital bit-packet switching over multiplexed links. Although packet-switching is sometimes claimed as necessity for a NoC, there are several NoC proposals utilizing circuit-switching techniques. This definition based on routers is usually interpreted so that a single shared bus, a single crossbar switch or a point-to-point network are not NoCs but practically all other topologies are. Arteris’ FlexNoC interconnect IP product line generates a true NoC IP with distributed packetized transport and high-level SoC communication services, as opposed to a hybrid bus with centralized cross bars.

Since 2005 and the start of Arteris, FlexNoC, their flagship product, has made his way, initially in the wireless segment (I may be wrong, but I think Texas Instruments was Arteris very first customer, the FlexNoC being integrated into OMAP, the Application Platform for wireless phones/smartphones), rapidly gaining market share in this very demanding, competitive segment. Most of the time, the real competition was with internally developed solution. Everybody who had to compete with the Non-Invented-Here (NIH) syndrome knows how difficult it can be: you may have the best product, the NIH make it very difficult to sale! When looking at Arteris web site, you can see that the company is selling now in Wireless, Video and Imaging, Networking, Automotive and Consumer segments. That you see is also the fact that these customers are mostly located in USA, Korea and Japan. Europe and the rest of Asia was a virgin territory for Arteris… until very recently, on July the 19[SUP]th[/SUP] to be specific, when a press release was announcing that Rockchip had acquired the FlexNoC IP from Arteris.

Which is very interesting is that the company is a “leading Chinese fabless semiconductor company and mobile internet System-on-Chip (SoC) provider will leverage the chip in new cost-effective Android-based tablets and other mobile devices”. The NoC penetration in China is a strong signal: it means that Chinese fabless are playing in the same space than the TI, Qualcomm or Samsung. It also means that the Network-on-Chip, just a concept ten years ago, is penetrating every segment, every region of the world. One reason can be found in Rockchip quote from Li Shiqin: “We evaluated all the leading interconnect technologies and proved that Arteris’ NoC technology is the good choice for our multicore ARM-based SoCs,” said Li Shiqin, IC Design Manager at Rockchip. “Arteris FlexNoC is the suitable way for us to meet our design frequency, power, memory efficiency and QoS requirements.” The combination of Rockchip’s high-performance, energy-efficient processor and Arteris’ FlexNoC interconnect IP will deliver a robust platform for data-intensive tablet applications. These key benefits will translate to faster time-to-market for Android table manufacturers striving to meet fast changing consumer demands.

We also should quote Charles Janac: “Rockchip’s reliance on Arteris FlexNoC as the SoC interconnect within their most important platforms speaks volumes for Arteris’ unique network-on-chip technology,” said K. Charles Janac, President and CEO of Arteris. “Arteris NoC technology resolves key system bottlenecks ? and delivers significant technological and economic benefits.”

To learn a lot more about NoC and Arteris products, just go here.

By Eric Estevefrom IPNEST


Webinar on Multi-voltage/VT/Channel Length Libraries

Webinar on Multi-voltage/VT/Channel Length Libraries
by Daniel Payne on 08-02-2012 at 8:10 pm

ken brock

Ken Brockof Synopsys presented on how to optimize your SoC design for low power at 40nm, 28nm and 20nm nodes in a webinar today. Ken and I both worked together at Silicon Compilers back in the late 1980’s, the best EDA/IP company that I’ve had the pleasure to join.

The webinar made a brief mention of 14nm and FinFETS but didn’t share any details on 14nm libraries or design methodologies. Continue reading “Webinar on Multi-voltage/VT/Channel Length Libraries”


A Brief History of TSMC

A Brief History of TSMC
by Daniel Nenni on 08-02-2012 at 7:30 pm

In 1985 Morris Chang was recruited by the Taiwanese government to help develop the emerging semiconductor industry. In 1986 Morris joined the Hsinchu based non profit research institute ITRI as Chairman and President and launched what would be TSMC’s first semiconductor wafer fabrication plant on the ITRI campus. Taiwan Semiconductor Manufacturing Company Ltd. was officially formed in 1987 as a joint venture between the Taiwan government (21%), Dutch multinational electronics giant Philips (28%), and other private investors.

Without a doubt, TSMC created what is today’s semiconductor foundry business model. While at TI, Morris Chang pioneered the then controversial idea of pricing semiconductors ahead on the cost curve, sacrificing early profits to gain market share to achieve manufacturing yields that would result in greater long-term profits. This pricing model is still the foundation of the fabless semiconductor business model.

Even starting 2 process nodes behind competing semiconductor manufacturers (IDMs), TSMC was able to attract customers. 4-5 years later TSMC was only behind 1 process node and the orders started pouring in. In 10 years TSMC caught up with IDMs and the fabless semiconductor industry blossomed enabling a whole new era of semiconductor design and manufacturing. Today TSMC is the undisputed leader with a reported 49% share of the $30B foundry market segment. UMC is second with just over a 12% share, GlobalFoundries is a close third with 12%, and SMIC is fourth with 4.4%.

As the story goes, Morris Chang made the first TSMC sales calls in 1987 with a single brochure:

TSMC Core Values: Integrity, commitment, innovation, and customer trust.

It is interesting to compare the consistency of this statement with the 1997 TSMC mission statement:

We are building the world’s Virtual Fab! We provide the best quality technology, the greatest capacity and the highest standard of service. We are the most reliable choice as a partner in semiconductor manufacturing.

And again with the vision/mission statement on the TSMC website today:

Our vision is to be the most advanced and largest technology and foundry services provider to fabless companies and IDMs, and in partnership with them, to forge a powerful competitive force in the semiconductor industry. Our mission is to be the trusted technology and capacity provider of the global logic IC industry for years to come.

Also according to the current website TSMC has:

  • Served more than 600 customers
  • Manufacturing more than 11,000 products
  • A total managed capacity of 16.4 million eight-inch equivalent wafers in 2013
  • Compiled the largest portfolio of process-proven libraries, IPs, design tools and reference flows
  • Fab 2, 3, 5, 8 and 12 located in the Hsinchu Science Park
  • Fab 6 and 14 located in the Tainan Science Park
  • Fab 15 located in Central Taiwan Science Park
  • A wholly-owned subsidiary, WaferTech in the United States; TSMC China; and its joint venture fab SSMC in Singapore.
  • A US $70,481 million market capitalization as of 7/31/2012
  • 2011 total sales revenue reached a new high at US $14.5 billion
  • Expected 2012 capital expenditure total of US $8.5 billion
  • Listings on the Taiwan and New York Stock Exchanges (TSM)

While the original intention of TSMC was to aid the Taiwanese semiconductor design houses, Dr. Morris Chang clearly had much larger aspirations which transformed the global semiconductor industry into what is today a $300B+ business that is mission critical to modern life.

A Brief History of Semiconductors
A Brief History of ASICs
A Brief History of Programmable Devices
A Brief History of the Fabless Semiconductor Industry
A Brief History of TSMC
A Brief History of EDA
A Brief History of Semiconductor IP
A Brief History of SoCs


How the Apple-Samsung Duel Will Lead to Wintel 2.0

How the Apple-Samsung Duel Will Lead to Wintel 2.0
by Ed McKernan on 08-02-2012 at 11:00 am

The High Tech Trial of this Century: Apple vs. Samsung may end up being the catalyzing event that advances the established PC Monopolists known as Wintel (Microsoft and Intel) into leadership positions in the new era known as the Mobile Tsunami. Not a chance you say? Consider that the Apple, Samsung War is one that will not be settled by this or any court but be played out over the next decade in the marketplace among well-oiled vertically integrated supply chain driven hardware manufacturers with very strong market channel presence. Spectacular secular growth will subside in a few years but patent protection and shaving pennies off the cost of Billions of Smartphones and Tablets will matter a lot. How is this likely to play out?
Continue reading “How the Apple-Samsung Duel Will Lead to Wintel 2.0”


Cadence Digital Flow

Cadence Digital Flow
by Paul McLellan on 08-01-2012 at 8:01 pm

Cadence has a series of webinars about their digital flow, focused on 28nm design. It is easy for all of us in the EDA ecosystem to assume that everyone is already doing 20/22nm design, if not 14nm already. But in fact most designs are still being done at 45nm and 65nm; 28nm is still a big challenging step.

One of the tools in the Cadence digital flow is First Encounter, which we used to describe as a floorplanner but is now described as a tool for design exploration and prototyping.

This reminds me of an interesting lesson I learned while I was working at Cadence. We had fallen behind in floorplanning and place & route and so we decided to kick off one of those megaprojects that Cadence used to embark on back then. We called it Integration Ensemble. It would be a everything everyone ever wanted. To make sure, we went and talked to all our major customers and ended up with an insane list of features Integration Ensemble should provide. Since we needed to win the air war too, we briefed Richard Goering (then at EETimes) on Integration Ensemble and he wrote about it as the next great thing, coming real soon now. Well, it turned out the project was so complicated that the schedule was long.

Customers insisted, in particular, that the absolute most important can’t-do-without feature was multiple power supplies, which were starting to go mainstream. Multiple power supplies turn out to be hugely complicated to implement since the power supplies don’t actually show up in the netlist (as an explicit connection to every gate) so a huge number of tools need updating. Anyway, the project dragged out, Richard Goering got annoyed that we’d basically pre-announced something that was so far from delivery (I guess he’s forgiven Cadencethese days). Anyway, eventually it turned out all our customers, the ones who told us that we couldn’t possibly release Integration Ensemble without full multiple power-supply support, were all buying First Encounter (from Silicon Perspective). The irony being that it didn’t support multiple power-supplies. What people really wanted was fast placement and good routing estimation. Listening to your customers is not always good.

As Henry Ford once (reputedly) said, “If I’d asked my customers what they wanted they’d have said a faster horse.” Apple is also famous for not doing market research to find out what people want, on the basis that they won’t know they want, for example, an iPad before they get it. I certainly didn’t.

So Cadence bought Silicon Perspective (in a poorly constructed deal with no cap on the earnouts) for a large sum of money. It was what customers really wanted although they couldn’t articulate it, and they asked for a faster horse instead. So the lesson is that you can’t always trust what your customers tell you they want if it is not guiding incremental improvement to existing tools.

First Encounter remains a key part of the digital implementation flow. It is even more important today than when Cadence purchased it, since there is really no timing number you can rely on if the physical placement has not been done since so delay depends on interconnect more than anything else. Trading off performance, power and price (area) is much trickier than it has ever been and First Encounter is an environment for quickly doing the kind of what-if analysis that must be done early if a design isn’t going to embarrassingly blow out one of its budgets. Nobody wants a cell-phone chip, no matter how cool and sexy, if the standby time is only 4 hours.

Details on First Encounter are here. The webinars are here.

A Brief History of EDA


Verdi Integrated with Synopsys Protocol Analyzer

Verdi Integrated with Synopsys Protocol Analyzer
by Paul McLellan on 08-01-2012 at 4:28 pm

Josefina Hobbs, a solutions architect at Synopsys, shows the integration of Synopsys Protocol Analyzer with SpringSoft’s Verdi using the Verdi Interoperability Apps (VIA) which gives open access to the Verdi KDB and FSDB databases. She also demonstrates protocol debug made easy using the Protocol Analyzer. This gives users a graphical view of the transfers, transaction, packets and handshaking of a protocol.

Analyzing the implementation of modern protocols is complex. Transactions on buses are interleaved and so the relationship between the transactions themselves, which ones are happening concurrently, and which bus activity is associated with which transaction is not obvious. The Synopsys Protocol Analyzer makes this clear. In the screenshot below, the leftmost part of the window shows the transactions, the middle part (with the arrow) shows the concurrent transactions and the right part (brown) shows the bus activity. By clicking on any of these, the corresponding other pieces of the puzzle are highlighted.

This makes it easy to unravel the complex behavior of highly interleaved traffic, understand activity, identify bottlenecks and debug anything unexpected. The Protocol Analyzer also links with simulation logfiles, as in the screenshot below, so that timelines in the protocol are linked to the same point in the simulation logfile, making it easy to investigate issues by moving up and down the different levels of abstraction.

Protocol Analyzer can also be linked to SpringSoft’s Verdi so that the raw waveforms can be examined, and still have all the links to the higher level representations, and synchronized timelines, as in the screenshot below.

The video is hosted by SpringSoft here and by Synopsys here.


inShare33

Schematic Capture and SPICE Simulation in the Cloud

Schematic Capture and SPICE Simulation in the Cloud
by Daniel Payne on 07-31-2012 at 8:10 pm

In April I blogged about using the iPad for schematic capture and SPICE circuit simulation. My conclusion was that the technology was interesting but not quite ready for commercial use. Today I tried out the web-based version using my Google Chrome browser instead of the iPad. Install the Chrome app here or visit www.ischematic.com. This is a very interesting cloud approach of using a web browser instead of a desktop program to create schematics, submit a SPICE simulation to the cloud and view the results in your browser. Continue reading “Schematic Capture and SPICE Simulation in the Cloud”


A Brief History of the Fabless Industry

A Brief History of the Fabless Industry
by Daniel Nenni on 07-31-2012 at 7:30 pm

Even though most of us have witnessed the emergence of the fabless semiconductor industry it is still good to go back and remember how we got to where we are today, to realize that the semiconductors that you now hold in your hand were enabled by the rise of the fabless semiconductor business model. This is the first in a series of blogs I will do on this topic.

When I arrived in Silicon Valley in the early 1980’s the semiconductor industry was vertically segregated. Semiconductor IDM’s (integrated device manufacturers) owned and operated their own manufacturing facilities (Fabs). I worked for Data General, a computer manufacturer, at their fab on Mathidla Avenue in Sunnyvale, California. DG manufactured CPU’s and other chips for their line of Mini-Computers made famous by the Pulitzer Prize winning book “The Soul of a New Machine” by Tracy Kidder.

In order to manage excess capacity and increase the ROI of the capital intensive semiconductor manufacturing process, IDMs started offering smaller firms design, manufacturing, and packaging services. This was the start of the outsourcing revolution that we now call the Fabless Semiconductor Industry.

Dr. Morris Chang worked for one of the aforementioned IDMs (Texas Instruments) and went on to found Taiwan Semiconductor Manufacturing Corporation (TSMC). At TI, Morris Chang worked on a four transistor project where manufacturing was done by IBM. This was one of the early foundry relationships. At the same time Morris pioneered the then controversial idea of pricing semiconductors ahead on the cost curve, sacrificing early profits to gain market share to achieve manufacturing yields that would result in greater long-term profits. Morris also noticed in the early 80’s at TI that top engineers were leaving and forming their own semiconductor companies. Unfortunately the heavy capital requirement of semiconductor manufacturing was a gating factor. The cost back then was $5-10M to start a semiconductor company without manufacturing and $50-100M to start a semiconductor company with manufacturing. Some of these engineers went to the IDMs to get wafers from excess capacity but this was not a customer friendly process and sometimes they were getting wafers from a competitor.

In 1987 TSMC started the foundry business 2 process nodes behind current semiconductor manufacturers (IDMs). 4-5 years later TSMC was only behind 1 node and the orders started pouring in. In 10 years TSMC caught up with IDMs and the fabless semiconductor industry blossomed enabling a whole new era of semiconductor design and manufacturing. In the last 25 years and still today the remaining IDMs are being forced to go fabless or fab-lite at 28nm and below due to cost and daunting technical challenges.

If you look at the most recent ranking from iSuppli it is interesting to see that IDMs Renases, AMD, Infineon, Sony, Freescale, NXP, and Fujitsu are going or already have gone fabless. Also, Fabless companies Qualcomm, Broadcom, NVIDIA, Marvell, and MediaTek are climbing the charts. In ten years how many of these companies (other than the memory companies) will still have fabs?

[TABLE]
|-
! class=”blocksubhead” ! Rank
2011
! class=”blocksubhead” ! Rank
2010
! class=”blocksubhead” ! Company
! class=”blocksubhead” ! Country of origin
! class=”blocksubhead” ! Revenue
(million
$ USD)
! class=”blocksubhead” ! 2011/2010 changes
! class=”blocksubhead” ! Market share
|-
| 1
| 1
| Intel Corporation(1)
| USA
| 49 685
| +23.0%
| 15.9%
|-
| 2
| 2
| Samsung Electronics
| South Korea
| 29 242
| +3.0%
| 9.3%
|-
| 3
| 4
| Texas Instruments(2)
| USA
| 14 081
| +8.4%
| 4.5%
|-
| 4
| 3
| Toshiba Semiconductor
| Japan
| 13 362
| +2.7%
| 4.3%
|-
| 5
| 5
| Renesas Electronics
| Japan
| 11 153
| -6.2%
| 3.6%
|-
| 6
| 9
| Qualcomm(3)
| USA
| 10 080
| +39.9%
| 3.2%
|-
| 7
| 7
| STMicroelectronics
| FranceItaly
| 9 792
| -5.4%
| 3.1%
|-
| 8
| 6
| Hynix
| South Korea
| 8 911
| -14.2%
| 2.8%
|-
| 9
| 8
| Micron Technology
| USA
| 7 344
| -17.3%
| 2.3%
|-
| 10
| 10
| Broadcom
| USA
| 7 153
| +7.0%
| 2.3%
|-
| 11
| 12
| AMD
| USA
| 6 483
| +2.2%
| 2.1%
|-
| 12
| 13
| Infineon Technologies
| Germany
| 5 403
| -14.5%
| 1.7%
|-
| 13
| 14
| Sony
| Japan
| 5 153
| -1.4%
| 1.6%
|-
| 14
| 16
| Freescale Semiconductor
| USA
| 4 465
| +2.5%
| 1.4%
|-
| 15
| 11
| Elpida Memory
| Japan
| 3 854
| -40.2%
| 1.2%
|-
| 16
| 17
| NXP
| Netherlands
| 3 838
| -4.7%
| 1.2%
|-
| 17
| 20
| NVIDIA
| USA
| 3 672
| +14.9%
| 1.2%
|-
| 18
| 18
| Marvell Technology Group
| USA
| 3 448
| -4.4%
| 1.1%
|-
| 19
| 26
| ON Semiconductor(4)
| USA
| 3 423
| +49.4%
| 1.1%
|-
| 20
| 15
| Panasonic
| Japan
| 3 365
| -32.0%
| 1.1%
|-
| 21
| 21
| Rohm Semiconductor
| Japan
| 3 187
| +2.2%
| 1.0%
|-
| 22
| 19
| MediaTek
| Taiwan
| 2 952
| -16.9%
| 0.9%
|-
| 23
| 28
| Nichia
| Japan
| 2 936
| +34.1%
| 0.9%
|-
| 24
| 23
| Analog Devices
| USA
| 2 846
| -0.6%
| 0.9%
|-
| 25
| 22
| Fujitsu Semiconductors
| Japan
| 2 742
| -0.5%
| 0.9%
|-
| colspan=”4″ | All Other companies
| 95 610
| -0.5%
| 30.7%
|-
| colspan=”4″ | TOTAL
| 311 360
| 1.3%
| 100.0%
|-

A Brief History of Semiconductors
A Brief History of ASICs
A Brief History of Programmable Devices
A Brief History of the Fabless Semiconductor Industry
A Brief History of TSMC
A Brief History of EDA
A Brief History of Semiconductor IP
A Brief History of SoCs