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January 20, 2014

The Semiconductor Landscape – III

The Semiconductor Landscape – III
by Pawan Fangaria on 01-20-2014 at 12:30 pm
Categories: EDA, General

In continuation to my earlier observations and anticipations (landscape1, landscape2) which came up to my expectations, I was further inspired to ponder over the macros of our ever growing semiconductor industry. We may argue the business is stagnating, we may argue that the pace of scaling is slowing, but when I look back at the year bygone, I can clearly see a thoughtful trend of consolidation in the semiconductor arena, and that is extended to even the semiconductor manufacturing equipment business. At the same time there is expansion in areas which are poised to drive the semiconductor industry going forward. Smart move!

Looking at 2013, it appears that semiconductor industry is turning around, as we see growth numbers trending towards positive ~5.2% (as per Gartner’s estimate based on world’s top10 semiconductor vendors revenue – 2012 rev $299,912M; 2013 rev $315,390M) from decline in earlier years. According to SIA (Semiconductor Industry Association) report the latest Nov 2013 rev has increased to $27.24B from $25.51B in Nov 2012, a healthy ~6.8% increase. This shows a healthy trend in store for future. Revenues from home appliances and its adjacent areas such as sensors, touch controls, smart meters etc. (not to forget smart phones :)) particularly in emerging un-saturated markets has been on the rise. Then there’s a tremendously large market of internet-of-things beaconing at us in the near future.

Having talked about a little bit on macroeconomics of semiconductors let me delve into the next level of strategic affairs in the industry. I will use my pet lenses of Business leadership, Technology leadership and IP leadership.

So, from business leadership angle, I can see consolidations among semiconductor businesses (EDA, IP, design and foundry) along with some of the adjacent areas like semiconductor equipment companies (AMAT acquiring TEL), Microsoft acquiring Nokia and Google about to buy Nest Labs which makes thermostats and smoke detectors. Without going into details with several examples, I would like to point out one distinct pattern of strengthening IP portfolio by large organizations. We know ARM is the leader in IP business. Now we see EDA veterans, Synopsys and Cadence strengthening significantly in this area through several acquisitions over last two years. It’s obvious, that’s an area to fuel growth in semiconductor industry, through internet-of-things in future.

As I had talked about IP leadership in my last article, IP is the brain child of semiconductor industry, it has its own will on whether to join with large magnets or flourish independently. While some of the niche IP organizations have joined hands with large organizations, there are others are doing well and many new IP vendors mushrooming steadily. So, this area will always be ripe, although ridden by heavy competition going forward. What will boost IP business further is internet-of-things market with very aggressive time-to-market schedules.

Coming to technology leadership – this is an interesting area, it leads business. Whenever, there is concentration in a particular business, technology takes a look from a distance and re-organizes itself to move forward from there. While we see foundries looking at 7nm node, FinFET or FD-SOI, there are other avenues growing to take More’s law further through 3D-IC. Newer tools are coming up to handle manufacturing complexities through newer, faster and cost effective methods such as Virtual Fabrication. EDA vendors are moving up the chain to handle large SoC and 3D designs through newer means such as major design decisions and sign-offs done at RTL level and maturing the tools down the line to handle everything automatically.

Looking at economics taking a growth trajectory, we can expect semiconductor industry going through significant leap with newer technologies, newer designs, newer methods and tools and newer market collaterals in the near future. Let’s be optimistic!

SilabTech Awarded 2013 Best Start-up in India

SilabTech Awarded 2013 Best Start-up in India
by Eric Esteve on 01-20-2014 at 8:32 am
Categories: IP

This is obviously great news for SilabTech, and this is the type of news which will change the perception that we (non-Indian) have of the Semiconductor industry in India. About 15-20 years ago, the India Embedded/VLSI industry was perceived as low cost design resource pool, a good place where to implement design center. The hidden insinuation was that decision power was located in western countries… This is still probably true for multinational companies, except that the cost is no more the main criteria why to rely on India based design center, as the quality of experienced designers is now the major reason to relocate design operation in India!

If we look at the winners list of the Mentor Graphics(R) Leadership Awards for the Embedded/VLSI Industry, we see that only Qualcomm and Microchip (two out of seven) are multinational (the full list at the end of this post):

The winners for this year, by category, are:
— Best VLSI/ Embedded Design — Automotive:
TVS Motors;
— Best VLSI/ Embedded Design — Consumer Electronics:
Ineda Systems;
— Best VLSI/ Embedded Design — Defense/Aerospace:
SCL, Chandigarh;
— Best VLSI/ Embedded Design — Telecom/Networking:
Qualcomm;
— Best VLSI/ Embedded Design Company from the Sub-Continent:
Millennium IT;
— Best Electronic System Design Company — Multinational:
Microchip;
— Best Electronic System Design Company — Startup:
Silab Tech;

It’s to be noticed that the panel of judges are eminent business leaders:

Sanjay Nayak, CEO & MD,Tejas Networks;
Krishna Moorthy K, MD – India Design Center, Rambus Chip Technologies;
Santhanakrishnan Raman, Managing Director, LSI India R & D;
Guru Ganesan, President & MD, ARM-India Operations;
Dr. S. Jabez Dhinagar, VP – Advanced Engineering Group, TVS Motors;
and Sunil Thamaran, Managing Director-Cypress India.

These judges are mostly coming from multinational companies like Rambus Chip Technology, LSI Logic, ARM or Cypress: their decision to select a majority of India based design companies (and not multinational R&D subsidiaries) is a clear sign that times are changing. Indian semiconductor ecosystem is moving from low cost design service area it was in the 1990’s to a country of entrepreneur, starting Design IP or Electronic System companies, as it appears to be today. Who say this? Walden C. Rhines, CEO and chairman, Mentor Graphics: “These award-winners showcase India’s rich resource of electronic design talent,” “This talent, combined with a spirit of innovation and a strong entrepreneurial drive, is what makes India an exciting place for the electronic information future,” said Walden C. Rhines, CEO and Chairman, Mentor Graphics.

If we come back to SilabTech example, the company has been built around a team of very experienced analog designers, involved in PLL and High Speed SerDes IP. SilabTech is still in start-up mode, although not involved into a start-up “gambling model” where you create a company and staff it as fast as possible as the goal is a fast exit through acquisition. SilabTech is targeting the long term development, investing wisely when needed: the first Interface IP (USB 3.0, PCIe gen-3, MIPI M-PHY to name a few) have been developed in 28nm technology. Because Silicon proven IP is a must have for such advanced nodes supporting expensive chip development, SilabTech has implemented these IP in a Test Chip (first and third above pictures), so they can claim having Silicon Proven IP. This is everything but a low cost strategy! SilabTech is currently developing a 12,5 Gbps SerDes to be released to Silicon soon…

Times are changing and India based design companies (not only design services companies) are emerging, like SilabTech, following a start-up model closer to US than to China, using VC money rather than money coming from government. The next step will be the emergence of India based Fabless semiconductor, no doubt that we will see fabless coming soon to join this dynamic ecosystem.

To read the full PR on the Wall Street Journal, go here

Semiwiki readers already know about SilabTech… remember this article

By Eric Esteve from IPnest

lang: en_US

Intel is NOT Transparent Again!

Intel is NOT Transparent Again!
by Daniel Nenni on 01-19-2014 at 9:00 am
Categories: Foundries, Intel Foundry, TSMC

Recent headlines suggest that Intel was not transparent about some of the products they showed at the CES keynote. Intel confirmed on Friday that they used ARM-based chips for some of the products but would not say which ones. When your company’s tag line is “Intel Inside” and you hold up a product during your keynote wouldn’t one assume that Intel was actually inside?

Today saying someone is not transparent really means they are being deceptive and when that someone is the CEO of a publicly traded semiconductor company it is serious business, my opinion. Even more glaring is the Intel claim of a 35% density advantage over TSMC at 14nm. This was presented during the November 21[SUP]st[/SUP] 2013 Intel analyst meeting. There is a barely noticeable disclaimer in the bottom right corner that says:

Sources: TSMC keynote, ARM Tech Con 2012, Oct. 30, 2012. Intel data alignment based on internal assessment.

This goes to my argument that Intel is NOT serious about the foundry business. They used a trade show marketing presentation from 2012 for this technical analysis? Is that the best the mighty Intel can do for competitive information?

Based on a thorough investigation by myself and just about every other company in the fabless semiconductor ecosystem this claim has proven to be absolutely FALSE. I write this now so when silicon is out and scrutinized we can go back and see who was telling the truth. Spoiler alert: It is not Intel!

The other interesting Intel news is that their big 14nm fab in Arizona will not be in production anytime soon. The delay was called a “minor correction”. The real reason for the delay, in my opinion, is so that Intel can continue to claim 80% capacity utilization so Wall Street does not downgrade INTC stock. If Intel counted idle fabs, their capacity numbers would be closer to 50% than 80%.

The other big news is that TSMC 20nm is in full production. We already knew this but it is nice to see TSMC talking about it:

“We have two fabs, fab 12 and fab 14 that complete the core of the 20nm-SoC. As a matter of fact, we have started production. We are in the [high]-volume [20nm] production as we speak right now,” said C. C. Wei, co-chief executive officer and co-president of TSMC, during a conference call with investors and financial analysts.

Do you remember last year TSMC said on a conference call that 20nm would be in volume production Q2 2014? And I said they were being cautious, that it would happen in Q1 2014? I know things, believe it. TSMC also said 20nm will account for 10% of wafer revenues in 2014 which would be more than $2B worth of 20nm wafers.

TSMC also did a FinFET update:

Talking at the company’s latest financial meeting, Mark Liu, TSMC co CEO, claimed its 16nm FinFET process is now ready for tape out and could be in volume production this year. “Our 16FinFET yield improvement has been ahead of our plan. This is because we have been leveraging the yield, learning from 20SoC. Currently, the 16FinFET SRAM yield is already close to that of the 20SoC process.”

Let’s not forget what Mark Bohr of Intel said about TSMC last year:

“Bohr claims in TSMC’s recent announcement it will serve just one flavor of 20nm process technology is an admission of failure. The Taiwan fab giant apparently cannot make at its next major node the kind of 3-D transistors needed to mitigate leakage current, Bohr said.”

TSMC 16nm is a FinFET version of 20nm, right? Maybe Mark saw that in a marketing presentation years ago? Intel, you really are better than this. If you don’t have something transparent to say maybe you should say nothing at all.

Managing Heat for System Reliability

Managing Heat for System Reliability
by Pawan Fangaria on 01-17-2014 at 8:30 am
Categories: EDA, Siemens EDA

In most of the electronic equipments, semiconductor chips are a major source of heat generation. And in semiconductor designs several hardware and software techniques are being used to contain power dissipation; a major cause for heat. However due to multiple functionality being squeezed into small form factors, we continue to experience our electronic devices such as smartphone, notebook and other networking and telecom devices that operate continuously, getting heated up after prolonged use. It’s essential to manage that heat to disperse through appropriate enclosure design, cooling, heat sink and other techniques; otherwise even a single chip failure can render the whole system at risk. How to model those designs for cooling of electronic devices which pose several complexities such as sheer number of solid-fluid and solid-solid surfaces, material property, highly cluttered for air circulation etc.?

It was a positive surprise for me coming across this state-of-the-art tool, FloTHERM XT from Mentor. I really admire the versatility of offerings from Mentor across all spheres of semiconductor design from chip and package to complete system, applicable to diverse set of applications including automotive, aerospace and defense.

FloTHERM XT takes EDA and MDA (Mechanical Design Automation) design flows together from concept to product validation, thus minimizing the risks associated with thermal aspects of the design as early as possible. It uses a solid modelling engine that can create a 3D model of the product with the desired level of details to keep the electronic and mechanical design in sync. This unique tool is easily used by design as well as thermal experts who can analyse the system through plenty of what-if scenarios.

FloTHERM XT provides an easy-to-use GUI to build models, automatic meshing, and efficient simulation of complex systems and convergence that significantly reduces overall time spent on thermal simulation compared to any CFD (Computational Fluid Dynamics) based solution.

The whole process is best described through a case study in a whitepaper at Mentor’s website.

[FloTHERM XT – Thermal design flow – Concept to prototype for electronic products]

The design starts with a simple representation of a PCB and components. An initial assessment of temperatures of critical components and cooling strategy is made. And then a complete model of the system is developed in stages with required enclosure and heat sinks designed through MCAD. Interface resistances are added and the full board layout is imported from EDA via FloEDA bridge. After merging enclosure from MDA system and PCB from EDA system, a thorough thermal simulation is performed. The component modelling also evolves through the flow; thermal models can change in complexity as required. FloTHERM XT has advanced library swapping and filtering support to choose appropriate models. The detailed modelling of IC packages is also done to determine if critical junction temperatures are exceeded.

Since power dissipation has increased and products are more compact than ever, thermal designs have become critical bringing EDA and MDA design flows closer together. FloTHERM XT provides a rapid design environment to create model geometry do simulation and develop the best optimized prototype to be manufactured. It has semi-automatic, object based algorithms, with options to adjust the mesh manually where required.

A detailed study of the thermal design issues, complexities involved in CFD based systems and how FloTHERM XT solves those issues in simplistic terms for the user is described in the whitepaper. It’s a good read for thermal, electronic, automotive, aerospace, and defense design engineers.

JasperGold COV App, the Swiss Army Knife for Verification

JasperGold COV App, the Swiss Army Knife for Verification
by Paul McLellan on 01-16-2014 at 12:55 am
Categories: EDA

At the Jasper Users Group meeting in October Rajeev Ranjan presented on the JasperGold COV App which he described as the Swiss army knife for verification. It comes in many sizes and contains many useful tools.

The primary goal of COV is to provide coverage metrics:

stimuli coverage: how restrictive is the design behavior under the formal set up?
property completeness coverage: how complete is the property set?
proof coverage: what coverage is achieved by the proven properties?
bounded proof coverage: what is the coverage and is it enough?

That last item, bounded proof, is used when only a subset of the state-space can be traversed and no violation is encountered. But it is not a full proof. A bounded proof of K cycles implies that all states reachable within K cycles of the reset state have been analyzed and all possible events with K cycles have been triggered.

It is also integrated in with the simulation database since formal doesn’t live in a verification world of its own and assertions that are covered by simulation do not need to be covered by formal and vice-versa. There is a special flow that can be used to improve simulation coverage with the unreachable coverage target detection flow, whereby JG coers items that are not hit in simulation and also confirms items that are unreachable and thus cannot be covered by simulation.

Different companies use the tool in different ways. Customers include Broadcom, ST, ARM, Applied Micro, Juniper, Nvida and others. Different usage models include:
[LIST=1]

Verification coverage for bounded result (property checking, sequential equivalence checking)

Completeness of property set

Protecting against over-constraint, dead-code analysis

Verification coverage from full-proof analysis

Post-silicon debugging

Detect and eliminate unreachable cover targets for simulation

Assist simulation in reaching a hard to reach target

Another facet is protection from over-constraints. Assumptions (constraints) limit the set of legal stimuli but assumptions can interact in complex ways resulting in conflict (not easily identifiable by eyeballing). This leads to the danger of false confidence for proven properties and so should always be used as a sanity check for all the proven properties. A special case is identifying dead code that cannot be reached, which can often lead to very fast identification of RTL bugs early in the design cycle.

There is more in the presentation. If you are a Jasper user (not necessarily one who attended JUG) then you can download the presentations, including this one, here.

Handel Jones Predicts Process Roadmap Slips

Handel Jones Predicts Process Roadmap Slips
by Paul McLellan on 01-15-2014 at 11:51 pm
Categories: ESD Alliance, Semiconductor Services

At the SEMI ISS conference earlier this week, the last speaker in the technology challenges section was Handel Jones of IBS. I’ve known Handel since the mid-1980s when he came to VLSI Technology and told us we were losing money on 90% of the designs we were doing but our cost model was not good enough and so we didn’t even realize. And he was right.

Since SEMI is focused on capital equipment and consumables (wafers, chemicals, sputter targets etc) Handel focused on what he thought the capital budgets were likely to be in the coming years. But one of the things I have learned is that if you really want to know what is going on in the fabs then ask the equipment and consumables guys. Nobody orders a $100M piece of equipment they don’t need, they postpone it. Nobody orders 50,000 wafer blanks if they only need 10,000 this month. We in the semiconductor pundit segment can wonder but these guys know.

Handel has a pretty good track record of knowing too, since he talks to everyone, they are all clients of IBS.

Handel predicted higher growth in 2014. In 2013 most of the growth came from a doubling in memory prices. Unfortunately for the equipment industry, this was mostly because they didn’t overbuild capacity and have a price war, so less equipment went in. In DRAM 3 companies have 90% of the market but the technology is mature due to difficulty in plan scaling meaning that most equipment will be transitioning older fabs to 20nm. Unless there is a new breakthrough memory technology of course. In NAND flash five companies have 90% of supply. Samsung is in the strongest position and are also building a big new fab in Xi’An (China).

The area where Handel was more pessimistic than most reports is on processes coming online in the foundry industry. In particular, there is major uncertainty in the timing of 20nm, 16/14nm FinFETs and then 10nm.

The challenge is that demand for 16/14nm technology is concentrated within a small number of companies in 2016 and potentially 2017 too. Qualcomm and Apple being the two giants (and Samsung in their own fab). Below 32nm, nearly 3/4 of the demand in 2016 comes from mobile application processors and modems (or combined AP and modems) with demand for low power and low cost. High performance is only about 20% of the market.

And even more challenging, the industry is trying to adopt 3 technologies in 3 years, with 28nm HKMG in Q2/2013, 20nm HKMG in Q2/2014 and 16/14nm in Q2/2016. I actually would count that as 4 years but it is aggressive either way. Even if fabs are ready, library, IP and design implementation takes 12-24 months which the design ecosystem probably cannot support.

In processors, the market is obviously dominated by Intel who are now ramping 14nm although behind schedule. On the very day of the presentation, Intel announced they were putting fab 42 on hold and would run 14nm in the same fab as 22nm in Arizona.

TSMC is in high volume at 28nm HKMG gate last. Revenues in Q3 2013 in 28nm were $1.8B. TSMC plans to ramp 20nm in 2014 and 16nm in 2015.

Samsung is now in high volume with HKMG 28nm gate first with Apple as a large customer, as is Samsung themselves. They plan to ramp 20nm in 2014 and 14nm in 2015.

GlobalFoundries is ramping fab 8 in New York with plans to ramp 20nm and 14nm where no timing has really been announced. SMIC is getting stronger and is building a new fab in Beijing. Obviously, China’s wafer demand will continue to grow as mobile in particular expands dramatically. UMC is continuing with a follower strategy.

Handel had the latest version of his cost per gate trends which continues to show them going in the wrong direction. The only way to get costs down is to invest much more, perhaps $1B, in additional architectural and design work to get the design sizes down. So expect slowing of scaling to smaller feature dimensions. The key driver (or un-driver) is the difficulty in reducing cost per gate and cost per bit. Increasing capacity beyond a certain point does not give any economies of scale and will not give lower cost per bit, but will increase losses if fabs are not full.

Handel’s big conclusions:

28nm will have a long lifetimes with opportunities for equipment vendors to expand capacity inside China
20nm parametric yield will improve and it will be a high volume technology node in 2015 but mostly 2016.
16/14nm will provide low cost gates with volume production only in 2017.
10nm will be postponed. Cost per gate will be prohibitive and unclear where demand will come from outside high-speed processors and FPGAs.

Positive Semiconductor Job Outlook in 2014!

Positive Semiconductor Job Outlook in 2014!
by Daniel Nenni on 01-15-2014 at 5:00 pm
Categories: EDA

Based on local traffic patterns and my experience in Silicon Valley over the last 30 years we are looking at a much higher employment rate inside the fabless semiconductor ecosystem, absolutely. Jobs are being filled more so than I have seen in the past ten years. The challenge of course is finding the right people for the right job and properly motivating them. This is critical if we want to thrive and innovate in the coming years. While LinkedIn is currently the defacto employment tool, in my mind there has got to be a better way to fill those jobs with qualified people.

“The December jobs report was an ugly mix of slowing employment growth and disappointing labor supply.” J.P. Morgan economist Michael Feroli.

Unfortunately the Bureau of Labor Statistics December jobs report does not agree with my assessment. For all of 2013, the economy added 2.2 million jobs which was on par with 2012’s gains but in December payrolls only grew by 74,000, the lowest total since January 2011. Meanwhile, the unemployment rate fell to 6.7% in December but the drop came mainly from people leaving the labor force. Hopefully this is a fluke due to the freezing weather and overly conservative holiday spending. The United States lost 8.7 million jobs in the aftermath of the 2007 financial crisis. As of January 1[SUP]st[/SUP] 2014 we have gained about 7.5 million of those jobs back.

“The Conference Board’s Leading Economic Indicators and the results from the latest survey of purchasing managers are two economic readings that suggest employment gains will rebound in the New Year.” Kathy Bostjancic, director of macroeconomic analysis.

Moving forward SemiWiki will focus efforts on a Jobs Forum in hopes of making a difference with the employment issues the fabless semiconductor ecosystem is currently facing. Just a quick survey of our 40+ subscribing companies revealed hundreds of jobs available and hundreds more opening up in the coming months. The challenge is attracting new qualified candidates and to do that we must get better at telling our story.

Joining SemiWiki in this effort is Rich Goldstein, a good friend and experienced employment professional. Recently Rich has been a contract Personnel Director of an Intellectual Property startup (Kilopass Technology), a sourcer for firmware engineers (PMC Sierra), as well as Software Developers (Xilinx), corporate EDA recruiter (Magma Design Automation), and for the better part of 2013 Rich was with AMD.

Rich and I will be writing in more detail about employment opportunities within the fabless semiconductor ecosystem in hopes of driving qualified traffic to targeted career website pages. Your feedback would be greatly appreciated as this project evolves over the next few months. Crowdsourcing wins every time, absolutely.

International CES Wrapup

International CES Wrapup
by Bill Jewell on 01-15-2014 at 4:00 pm
Categories: Semiconductor Intelligence, Semiconductor Services

Semiconductor Intelligence attended the International CES last week in Las Vegas, Nevada. A wide variety of consumer electronics devices were displayed at the conference. These ranged from:

· Fascinating – but is it practical? (personal robots, drones)
· Exciting – but when will it be cheap enough for the mass market? (UHD TV, glasses-free 3D TV)
· Potential hit – devices with near term growth prospects (wearable fitness/health devices)
· Mundane – incremental improvements in established devices (tablets, smartphones)
· Questionable – does anyone really want or need this? (Internet control of lights & appliances)

Despite the wealth of new technology introduced, the near term prospects of the consumer electronics market are weak. Steve Koenig, Director of Industry Analysis of the Consumer Electronics Association (CEA) presented the 2014 forecast by CEA and market research company GfK. The presentation is available at:

http://www.ce.org/Blog/Articles/2014/January/RESEARCH-What-Do-We-Expect-2014.aspx

CEA & GfK expect the worldwide consumer electronics market to decline 1% in 2014 measured in U.S. dollars. This follows a moderate 3% growth in 2014. The only product categories expected to show any significant growth in 2014 are smartphones (+6% vs. 27% in 2013), tablets (+9% vs. 30% in 2013) and video game consoles (+21% vs. -9% in 2013). Smartphones have been a strong growth category for the last few years, but have led to a decline in non-smart or feature mobile phones. The strong growth of tablets has contributed to a decline in PC sales. Video game console growth in 2014 is due to the introduction of the Sony PlayStation 4 and Microsoft Xbox One in late 2013. Despite the advances in LCD TVs such as Ultra High Definition (UHD or 4K) and glasses-free 3D, overall LCD TVs are expected to decline 2% in 2014 after 3% growth in 2013.

In terms of regions, developed countries (U.S., Western Europe, Japan, South Korea, Taiwan, etc.) are forecast by CEA/GfK to see a 4% decline in consumer electronics sales in 2014 after a 2% decline in 2013. Developing countries (China, India, Latin America, Eastern & Central Europe, Russia, Middle East, Africa, etc.) should grow 2% in 2014, a significant slowing from 9% in 2013. According to CEA, developed countries accounted for 60% of consumer electronics sales in 2010. The percentage is expected to decline to 50% in 2014 and continue to decline in future years.

Two of the emerging consumer electronics devices we focused on at CES were Ultra High Definition (UHD) TV and wearable devices for health and fitness. Although these two categories have potential to drive growth in consumer electronics in the future, what is the near term outlook?

All of the major TV suppliers displayed UHD TVs with screen sizes of 85 inches (diagonally) and up. Several UHD TVs are available on the market. Bestbuy.com lists major brand UHD TVs at about $5,000 for 65 inches and $3,000 for 55 inches. By comparison, HDTVs sell for about $1,500 for 65 inches and $750 for 55 inches. The high prices and limited UHD content will limit sales to early adopters for several years. IHS Inc. expects UHD TV sales to hit 10 million units in 2014, up from 1.5 million in 2013. Sales are forecast to hit 38.5 million units in 2018, but will be only 16% of the total LCD TV market.

Wearable devices should have near term impact on the consumer electronics market. Fitness and health are the major drivers of wearable devices. The 2014 market for wearable devices is expected to be about $5 billion. Forecasts for the 2018 market size range from $13 billion from BI Intelligence to $35 billion from the Industrial Economics and Knowledge Research Center (IEK). Wearable devices are a new area of consumer electronics and should drive growth without displacing sales of other electronic devices.

More Articles by Bill Jewell …..

lang: en_US

January 15, 2014

MIPI Alliance Specifications Adoption Status in 2013

MIPI Alliance Specifications Adoption Status in 2013
by Eric Esteve on 01-15-2014 at 11:00 am
Categories: IP

At the beginning of December in Paris I had the opportunity to make a presentation to a very impressive audience, technical gurus from companies contributing to MIPI Alliance specification were here, including ST-Microelectronics, Intel, Qualcomm, TI, Toshiba, Nokia, Samsung, to name a few.

Continue reading “MIPI Alliance Specifications Adoption Status in 2013”

January 15, 2014

Is Intel the Concorde of Semiconductor Companies?

Is Intel the Concorde of Semiconductor Companies?
by Daniel Nenni on 01-15-2014 at 8:00 am
Categories: Foundries, Intel Foundry

An Intel executive recently told me that my Intel articles on SemiWiki are used to motivate employees to work hard and prove me wrong. The converse is also true. The senseless Intel fabless ecosystem bashing motivates me to continue to write so it is a win-win scenario, absolutely. In fact, I should credit Intel’s Mark Bohr for motivating me to write a book chronicling the great and powerful fabless semiconductor ecosystem, but I won’t.

At the SEMI ISS conference this week there were some excellent presentations filled with important market data. Most of which I already knew but seeing it all in one place with a historical perspective was well worth the price of admission. And networking with industry executives from around the world is priceless. I had lunch with David K. Lam, founder of famed semiconductor equipment manufacturer LAM Research. How cool is that!?!?!

Unfortunately, I do not have permission to post the slides so I will summarize the best I can:

The Concorde reference is from the keynote by Rick Wallace, President and CEO of KLA-Tencor. The point being that the Concorde failed not because of technology, it failed because of economics and lack of competition, adding that Moore’s law is much more likely to die in the board room than the manufacturing floor. This is absolutely true.

In my biased opinion, that is Intel’s problem exactly. The laws of physics will not defeat Intel, the natural laws of economics and inflated egos from lack of competition will. BK (Intel’s CEO) said it all with his latest quote, “We will not get into a price war with TSMC”. News flash: TSMC is not your competitor, Samsung is and they are going to eat your economic lunch, absolutely. Just ask Apple.

Bill McClean, President of IC Insights, had the most informative slides which I will use to support my anti Intel bias:

World Wide Semiconductor Sales in 2013:

[LIST=1]

Intel $48.3B

Samsung $33.6B

TSMC $19.8B

QCOM $17.1B

Micron $14.1B

It is interesting to note that TSMC revenue surpasses Intel if you do an apple to apple comparison using the final market value of the chips TSMC manufactures. That would be the price TSMC customers sell their chips for.

Top 10 IC Foundries in 2013:

[LIST=1]

TSMC $19.9B

GLOBALFOUNDRIES $4.3B

Samsung $4.0B

UMC $3.9B

SMIC $2.0B

PowerChip $805M

Vanguard $712M

Grace $710M

Dongbu $570M

Tower Jazz $509M

TSMC again posted double digit gains as did Samsung. SMIC is the real winner in 2013 with a 28% gain. I would attribute this to home court advantage in the China semiconductor market. Notice the 4.6x gap between #1 and #2 and the 39X gap between #1 and #10. TSMC’s lead will continue to grow in 2014, definitely.

Top 10 CAPEX Spenders in 2013:

[LIST=1]

Samsung $12B

TSMC $11.2B

Intel $10.5B

GF $5.5B

SK Hynix $3.7B

Micron $3B

Toshiba $2.9B

UMC $1.5B

Infineon $880M

ASE (OSAT) $770M

Yes, Samsung and TSMC both outspent Intel. Just wait until you see the capacity numbers and you will know why.

Top 10 IC Wafer Capacity Leaders in 2013:

[LIST=1]

Samsung 12.6%

TSMC %10%

Micron 9.3%

Toshiba 8%

SK Hynix 7%

Intel 6.5%

ST 3.5%

UMC 3.5%

GF 3.3%

TI 3.0%

The majority of Samsung’s capacity is memory. Intel also has memory in there so if you only look at logic capacity (SoCs) TSMC is the clear leader by a very large margin.

The question I most commonly get asked (other than people asking for my autograph): Is Intel serious about the foundry business? My answer unfortunately has not changed in the last year. No, Intel is not serious about the foundry business. It is a head fake to appease investors and make waves in the industry, just my opinion of course. Let’s hope the Intel Foundry team proves me wrong.