SemiWiki – Page 798 – The Open Forum for Semiconductor Professionals

October 14, 2014

EDAC Mixer, Kaufman and More. All Things EDAC

EDAC Mixer, Kaufman and More. All Things EDAC
by Paul McLellan on 10-14-2014 at 5:00 pm
Categories: EDA

The next monthly EDAC mixer is next week on Thursday 23rd October from 6-8pm. It will be at the Sonoma Chicken Coop at 90 Skyport Drive in San Jose (right next to where Magma used to be and Atmel is). So come along and mingle with industry peers, all the the benefit of local charities. You don’t need to donate, just pay for your food and drink normally and a portion goes to the charity concerned. This month’s charity is the Mountain View Educational Foundation (MVEF), a volunteer driven non-profit that provides funding for enrichment programs and educational material to enhance the solid academic curriculum and maintain the high quality of education in the Mountain View Whisman School District. To learn more about MVEF, visit their web site at www.mvef.org. If you are going to go, then EDAC would like you to register (it’s free of course) so that they have some idea of numbers. You can register here. See you there.

The 2014 Phil Kaufman Award is going to Lucio Lanza of Lanza techVentures. EDA and IP startups have always been a key source of technology innovation – even today’s larger EDA and IP companies were startups at one point. Over the last two decades, Dr. Lanza has helped guide numerous startups as they developed the innovative technologies needed to keep the industry moving forward. Lucio’s continuing strong support of the industry has included valuable business and technical mentoring based on his years of experience in the EDA and semiconductor industries, as well as financial backing in many cases.

Joe Costello, founding CEO of Cadence Design Systems, is quoted in the press release.These days, when I talk to a young EDA or IP startup I hear about Lucio. He is keeping our industry fed with a steady stream of innovation, new ideas and energy. So in a very practical sense, it is Lucio’s vision and drive that powers today’s EDA industry and plots its future. And for this, we are all very fortunate.

The award will actually be presented at the Kaufman Award Dinner which will be held in conjunction with ICCAD on Tuesday November 4th at the San Jose Marriott (the one downtown) at 301 Market Street. It starts at 6.30pm. You can purchase tickets or tables here.

Making Wafers in Space?

Making Wafers in Space?
by Bill Jewell on 10-14-2014 at 7:00 am
Categories: Foundries, Semiconductor Intelligence

The Albuquerque Journal had an article about a local company sending silicon carbide wafers into suborbital space to improve their quality. ACME Advanced Materials plans to buy low quality $250 wafers, send them into space using their process, and sell the higher quality wafers for about $750. They are working to add gallium nitride wafers to their process. Below is president Rich Glover.

ACME has a current capacity of 250 four-inch wafers per month. They plan to ramp up to 1000 wafers per month in three months and 5000 in six months. The company also plans to eventually move to 300mm wafers. ACME has been sending wafers into orbit since last spring using an unnamed company in Texas. ACME is funded by Cottonwood Technology Fund of New Mexico and Panega Ventures of Canada.

The article is at: http://www.abqjournal.com/478890/biz/made-in-space.html

Silicon carbide and gallium nitride wafers are key materials for wide bandgap semiconductors. Wide bandgap devices can operate at higher voltages, frequencies and temperatures than traditional silicon or gallium arsenide devices. According to the U.S. Department of Energy wide bandgap devices are important to saving energy in improving performance in power electronics, solid-state lighting, industrial motors, DC/AC power conversion, power transmission, electric vehicles and optical electronics. The DOE and private investors plan to spend $140 million over the next five years to fund a consortium in North Carolina on next generation power electronics. Wide bandgap devices will be a key focus of the consortium. The DOE article is at: http://www.manufacturing.gov/docs/wide_bandgap_semiconductors.pdf

A recent report from The Information Network projects the wide bandgap semiconductor market will reach $500 million by 2017 from $150 million in 2013. Another report from Markets and Markets project the silicon carbide semiconductor market will reach $3 billion by 2020. IMS Research (now part of IHS) in 2013 projected the overall market for wide bandgap power semiconductors would be about $2.8 billion in 2022, with about $1 billion from gallium nitride and $1.8 billion from silicon carbide.

The Applied Power Electronics Conference and Exposition (APEC) held in Fort Worth in March 2014 featured numerous sessions on wide bandgap devices. I attended part of the conference. Sessions on wide bandgap devices were featured under the topics of high power industrial, DC-DC converters, and vehicle power electronics. APEC feature six presentations during a three hour session on wide band gap devices. The market is attracting current players in power semiconductors as well as startups. These companies include: ABB, Agilent, Avago Technologies, CREE, Efficient Power Conversion, Fairchild Semiconductor, Genesis Semiconductor, Infineon, International Rectifier (which is being acquired by Infineon), Microsemi, Nortsel AB, OSRAM Opto Semiconductors, Panasonic, Renesas Electronics, ROHM, STMicroelectronics, Texas Instruments, Transphorm, and TriQuint Semiconductor.

For you process junkies, Microsemi and Digi-Key have released a paper on gallium nitride versus silicon carbide. The paper covers process technologies in detail. The paper sees gallium nitride primarily being used in lower power, lower voltage, high frequency applications and silicon carbide mostly used in high power and high voltage applications. The paper is available at: http://www.digikey.com/Web%20Export/Supplier%20Content/Microsemi_278/PDF/Microsemi_GalliumNitride_VS_SiliconCarbide.pdf?redirected=1

The wide bandgap semiconductor market certainly bears watching in the next few years. Any power semiconductor company not investigating this technology needs to find a partner who is.

October 13, 2014

NoC resilience protects end-to-end

NoC resilience protects end-to-end
by Don Dingee on 10-13-2014 at 4:00 pm
Categories: Arteris, IP

Protecting memory with ECC but leaving the rest of an SoC uncovered is like having a guard dog chained up in the back corner of your yard. If the problem happens to be in that particular spot, it’ll be dealt with, otherwise there will be a lot of barking but little actual protection.

Similarly, adding a safety-capable processor like an ARM Cortex-R or a Synopsys DesignWare EM SEP core in a dual-core lockstep configuration is only part of the answer for protecting SoCs.
Continue reading “NoC resilience protects end-to-end”

October 13, 2014June 14, 2019

Proving the Power of Virtual Fabrication

Proving the Power of Virtual Fabrication
by Pawan Fangaria on 10-13-2014 at 7:00 am
Categories: Coventor, EDA

There are many facets of our lives that are being driven to a more virtual method of doing things. This is largely due to issues such as scaling due to whatever reason – technical, business, economic. Let’s look at some general cases: In yesteryears people used to travel all the way for face-to-face meetings; today virtual meetings using video conferencing technology happen within couple of clicks on your Smartphone or notebook. Similarly, I completed one of my management courses attending only virtual classes throughout the course on my notebook screen for several months. And people from across the world often attend on-line webinars on important technical topics. These are just a few ways we see technology enabling more efficiency by moving from physical to virtual, saving us significant time and costs. And these virtual solutions are proven to work very well.

These are mainstream examples but we can see the same trends in the semiconductor area which is growing more and more complex by the day as we move towards newer nodes. The design of a chip is by its nature a virtual process driven by EDA tools. The latest examples being virtual prototyping and virtual platform for architecting and optimizing an SoC at the system level. A chip design sees the real world only at the time of fabrication in a foundry, which tells about how close was the design to the reality. This is a very simplistic visualization of this scenario.

Things get really complex and murky when we look at process variation taking place at ultra low nodes. The result then is what you design is not what you get in the actual fab and you end up in several cycles between the design and the fab. In such a situation, the idea of a Virtual Fabrication Platform to quickly experiment, measure process sensitivities and devise process integration steps for the designs to work correctly during actual fabrication proves to be a boon. It saves time and costs for process engineers and design engineers.

I can recall about a blog I had written about a year ago about how 3D NAND Flash development can be accelerated with the use of Virtual Fabrication, in which David Fried, CTO – Semiconductor at Coventorhad provided his great insight into Virtual Fabrication and how SEMulator3D can help.

Read to know more – What Can Accelerate 3D Semiconductor Manufacturing

Today, while reading an articlewritten by Ryan Patz of Applied Materials who earlier worked at Coventor as well, it revived my memories about the business and technical crisis NAND Flash is experiencing. While 3D NAND is still away, 2D NAND needs continuous scaling in order to be profitable for business. And that needs extensive experimentation to build newer process models for smaller feature sizes and higher yields.

Ryan is a known expert in semiconductor fabrication technology. He studied the quadruple spacer patterning technology, slimming of floating gate (FG), and word-line (WL) and bit-line (BL) direction air gap to enable a “Middle-1X nm NAND” (M1X-NAND) flash memory cell announced by SK Hynixat last year’s IEDM 2013 and experimented further on SEMulator3D’s Virtual Fabrication platform to build a process model to understand the bidirectional air gap formation and corresponding process sensitivity because it’s necessary for the ‘quadruple spacer technology’ to overcome the effects of process variation to deliver a narrow distribution of device performance.

The air gap formation in both directions, WL and BL, is extremely sensitive to the conformality of the dielectric deposition process and FG slimming. In the above image, the baseline model is seen to be centered right in the middle of a steep sensitivity with deposition conformality (lateral/vertical) ratio of 0.1. Any small variation in deposition conformality can have large impact on the air gap cross-section area.

This study clearly shows the advantages of process studies in a virtual platform which can be quickly done off fab and used for process optimization and prioritization. The SEMulator3D is quite well-equipped to devise new optimized process integration flows for the newest nodes and help scaling future technologies.

I am happy to see this study done by using SEMulator3D to further prove the power of Virtual Fabrication. Read Ryan’s article to know more about this study here.

CASPA, ARM and the Internet of Things

CASPA, ARM and the Internet of Things
by Paul McLellan on 10-12-2014 at 7:01 am
Categories: Arm, CASPA, IP, Semiconductor Services

Today I was at the Chinese-American Semiconductor Professionals’ Association conference and dinner. Simon Segars, CEO of ARM, gave the dinner keynote. Somewhat surreally, it was in the same room in the same conference center two weeks ago that he gave they keynote at ARM TechCon. In another coincidence, Mike Muller of ARM gave one of the keynotes at TSMC’s OIP conference the day before, and then at ARM TechCon too. October seems to be all ARM all the time.

The CASPA event was titled Intelligent and Secured Living in a Connected World. It was really about the Internet of Things (IoT) with presentations from Broadcom, AMD, Imagination and SnoopWall. The most provocative presentation was the one by Gary Miliefsky of SnoopWall about privacy and security. He talked about how flashlight apps are all malware and hundreds of millions of phones are infected. He was recorded for ABC news (I think it was) and it should be broadcast early next week. When he was asked whether he thought it was possible to build a secure phone he was pessimistic: you can make it a lot better than it is today but the NSA is simply not going to let you build something that they are kept out of. I don’t know all the details but the Blackphone developed in Switzerland was taken off sale for a time and he is sure now that it is back that it has been compromised. There are videos from other news programs on the SnoopWall website.

Simon Segars talked about the impact of IoT on the semiconductor business and on ARM in particular. At ARM TechCon a couple of weeks ago ARM announced two things that are especially important for the IoT market. First, they announced their highest end Cortex M series, the Cortex-M7. It combines a six-stage, superscalar pipeline with flexible system and memory interfaces including AXI, AHB, caches and tightly-coupled memories, and delivers high integer, floating point and DSP performance in an MCU. Between the M0 and the M7 there is a huge range of performance and these processors are ideal for many IoT projects.

They also announced the ARM mbed IoT device platform. This consists of 3 products:

the mbed OS. This is an operating system for the Cortex-M series that is free for use on theose processors. It consolidates the fundamental building blocks of the IoT in one integrated set of software components. It contains security, communication and device management features to enable the development of production-grade, energy-efficient IoT devices
the mbed Device erver to connect and manage devices in a secure way. It also provides a bridge between the protocols designed for use on IoT devices and the APIs that are used by web developers. This simplifies the integration of IoT devices that provide “little data” into cloud frameworks that deploy “big data” analytics on the aggregated information.
mbed.org The website provides a comprehensive database of hardware development kits, a repository for reusable software components, reference applications, documentation and web-based development tools.

The idea is to make it straightforward to build IoT projects with the mbed OS running on the sensor/compute/communicate chip, the mbed Device Server running on a web server or in the cloud, and mbed.org to create a strong community of developers. The mbed.org website is not new, it already has 70,000 developers using it.

TSMC ♥ Cadence!

TSMC ♥ Cadence!
by Daniel Nenni on 10-11-2014 at 4:30 pm
Categories: Cadence, EDA, IP, TSMC

One of the questions I routinely ask amongst the fabless semiconductor ecosystem is, “How are the EDA vendors doing?” There are always complaints because, let’s face it, we all like to complain. On occasion however I do hear about a vendor who goes above and beyond the call of duty and it really brightens my day.

Of late, the highest praise has gone to Cadence. I was working in Silicon Valley in the early 1980s when EDA began to flourish. It was mostly DMV (Daisy, Mentor, Valid) when two smaller start-ups merged (ECAD and SDA) in 1988 to create Cadence. I credit Joe Costello with making EDA an exciting place to work. Unfortunately, after Joe left in 1997 Cadence seemed to lose its way. In January 2009 Lip-Bu Tan joined Cadence as President and CEO after serving on the Cadence Board of Directors for five years. To me that was a turning point for Cadence which brought them back to what they are today, an industry leader. Cadence stock agrees as it has more than tripled since Lip-Bu took over as President and CEO.

20nm was a defining node as it required much closer collaboration amongst the fabless semiconductor ecosystem. Double patterning is one example but there are plenty of others. At 16nm we have FinFETs and even more challenges ahead especially for analog and mixed signal design and as we all know Cadence is the AMS design market leader. 10nm is well underway and Cadence is a key player in the development of IP and PDKs to which TSMC acknowledged during their Open Innovation Platform Forum:

Cadence Wins Two TSMC Partner of the Year Awards for Soft IP and 16FF+ Solutions

“We presented the awards to Cadence based on the quality results delivered through its Soft IP and 16FF+ solutions,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Cadence has demonstrated its commitment to working closely with us to bring the highest quality design capabilities to IC designers around the world, and we look forward to continuing our partnership in the years to come.”

Dr. Chi-Ping Hsu, senior vice president, chief strategy officer, EDA, and chief of staff to the CEO at Cadence, commented on the awards, saying, “The award recognition from TSMC reflects our long-standing relationship and further demonstrates our ongoing commitment to delivering a strong IP portfolio and advanced-node technology for next-generation SoC designs.”

Dr. Hsu from Cadence further commented, “Customers that create chips for the world’s newest mobile devices are already tapping into the benefits of the 16FF+ design flows and can start to adopt 10nm FinFET solutions to overcome design complexity and get to market faster.”

This did not come as a surprise to me because of the many EDA people I see in Hsinchu. One of the more critical components of collaboration is the willingness to “show up” and during my travels I most often see Cadence executives. Contrary to unpopular belief, there is no such thing as tossing semiconductor designs over the wall to manufacturing so if you want to know who the key players are in modern semiconductor design and manufacturing spend time at the Hotel Royal, The Sheraton, and the Ambassador Hotel in Hsinchu. Or just hang out in the lobby of TSMC Fab 12.

And yes I know Synopsys and other partners were recognized by TSMC, and rightly so, but I give the SemiWiki award for Most Improved EDA Vendor to Cadence, hands down. Ha ha, you thought I was going to say “absolutely” didn’t you?

What’s next in test compression?

What’s next in test compression?
by Beth Martin on 10-10-2014 at 4:45 pm
Categories: Events, Siemens EDA

If you’ll be at ITC TestWeek in Seattle (Oct 20-23), here’s one event you don’t want to miss: a technology reception hosted by Mentor, with Janusz Rajski and Nilanjan Mukherjee as the featured speakers. It is free to ITC attendees and you can register here. [If for some crazy reason you haven’t registered for ITC yet, do that here.]

If you are involved with DFT, you’ll recognize Rajski as the inventor of the embedded deterministic test (EDT) technology that is the basis for ATPG compression. He is a chief scientist and the director of engineering, but you can think of him as Mr. Compression. Mukherjee is the engineering director for the test synthesis group at Mentor Graphics.

EDT has scaled to 100x compression, but new technology nodes and new fault models targeting defects within standard cells are driving the need for even greater compression levels. Rajski and Mukherjee will introduce a novel technology they developed specifically to work with embedded compression to further reduce pattern volume for compressed patterns. You will also learn how Mentor’s customers are using this new technology.

The presentation starts at 7:00pm and should last 40 minutes. After that, they will open the bar, pass the finger foods, and turn on the disco ball. Actually, I made up the disco ball part. See you there!

What: Seminar and Reception, The Next Big Thing in Test Compression (Register)
When: Monday, October 20. 6:45pm Doors open
7:00pm Presentation begins
7:40pm Drinking and dancing begins

Where: WSCC North Galleria, Room 2B

International Test Conference, the cornerstone of TestWeek™ events, is the world’s premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.

October 10, 2014

Full-Chip Electromigration Analysis

Full-Chip Electromigration Analysis
by Daniel Payne on 10-10-2014 at 7:00 am
Categories: EDA

I’ll never forget debugging my first DRAM chip at Intel, peering into a microscope and watching the aluminum interconnect actually bubble and dissolve as the voltage was increased, revealing the destructive effects of Electromigration (EM) failure. That was back in 1980 using 6 um, single level metal technology, so imagine how much more important EM analysis is today on chips using 20 nm and smaller geometries, with 10+ metal layers, and even 3D stacking. Valeriy Sukharev, Ph.D. of Mentor Graphics just wrote an 8 page White Paper titled: Electromigration Analysis At Advanced Nodes, so I read it today to learn what the new EM challenges are all about.

Sukharev earned his master’s degree in solid state electronics and a Ph.D. in physical chemistry of solids and interfaces. He’s been a principal engineer at Mentor since 2008, and before that was at Ponte Solutions as a chief scientist.

The power and ground nets in an IC are prone to EM effects because current flows only in one direction, and the interconnect of either aluminum or copper are subject to EM because the materials have high self-diffusivity. As current flows in a net there is atom depletion and accumulation caused by EM, creating voids and hillocks respectively:

Void and hillock formation

Using a Tunneling Electron Microscope (TEM), researchers at E. Zshech of Fraunhofer IZFP-D showed what voids look like:

Can two identical metal lines with the same electrical load have different EM characteristics? Yes, because there is variation in grain boundaries and atomic diffusivities. The Time To Failure (TTF) is a distribution function, so here’s a chart showing electrical resistance change as a function of time:

Effect of voiding on line resistance

Ideal equations for EM behavior are well understood and come from James Black and Blech calculated some 50 years ago. These equations don’t take into account new effects, like:

Dependency of MTTF on residual stress
Across-die variation
Layout dependent variables

Sukharev is proposing a new physics-based MTTF compact model, which does take into account the new effects listed above. This new model takes into account:

Temperature and current density effects
Impact of residual stress
Process variation

As an example, consider the following table where the time to create a void (the void nucleation time) inside of a 100um length line is a function of the current density and temperature of the stressing test. Values in yellow are immortal, meaning they will not have EM failure. The left column (J/test) has the conditioning temperature responsible for thermal stress-induced voiding.

Expect the next generation of EM tools to take into account a more optimistic approach that more closely model the actual physics of corner current densities and temperatures in the presence of variations. Residual stress effects will also be included in EM calculations for more accurate predictions. Read the complete White Paper here, after a brief registration process.

October 9, 2014July 18, 2025

Maker Movement Embraced by Major Semiconductor Companies

Maker Movement Embraced by Major Semiconductor Companies
by Tom Simon on 10-09-2014 at 10:00 pm
Categories: Arm, Foundries, Intel Foundry, IP, Synopsys

How the Arduino Changed Embedded System Development Forever

In 2005 with the development of the Arduino, everything changed for people building things that required a microcontroller. The Arduino brought with it a low price standard, and open, hardware platform and an easy to use open source development environment. It was not without its limitations, but it opened the doors for literally thousands of people who had ideas and did not want putting together the platform to take most of their time. According to Wikipedia, it is estimated that there are over 700,000 Arduino boards in developer hands.

It used to be that you needed to have a hardware programmer and had to master a long complex tool chain to develop, compile, link and load your code. On the hardware side, the Arduino brought a standard form factor and pin-outs, but more importantly standard libraries for things like digital IO, PWM, SPI and I2C. All of this was wrapped in an easy to install and use free development environment based on GNU tools, including a code editor and requiring no command line input. More information and the IDE are available at www.arduino.cc. The programming is made easy to use by simply connecting a USB cable to the board.

Once there was a ‘standard’ many compatible interface boards, called shields, and devices were developed. The libraries for accessing them were openly available in usable source code format for download and reuse. Sensors like MEMS gyroscopes or accelerometers, and proximity, light, temperature, image, touch, etc. became easy to use. Added to this mix were servos, motor controllers, addressable LEDs, and many other devices. Of course hobbyists picked up on this and it became a rapidly growing cottage industry. Just go to retailer sites like www.adafruit.com or www.sparkfun.com to see what is available.

The first Arduino used an Atmel microcontroller from the AVR series. They are 8 bit CPUs running at a modest 8 or 16MHz, digital IOs, and analog inputs. There is also flash storage on-chip for code storage, RAM for program data storage, and EEPROM. Flash and RAM are limited, but enough to get by for small projects. To give you an idea, all the data in your code was typically limited to 2K bytes. But there is no operating system and the program code can be loaded into the flash using a USB cable. The on-chip flash and EEPROM means that these chips were fabricated using older process nodes and proprietary processes.

Despite the initial limitations people became more ambitious with what they built. If you look today at almost any 3D printer or quadcopter, you will see an Arduino hidden inside. Thus the Arduino has become an enabling technology for a new wave of products. One notable example is the OtherMillthat can be used to fabricate custom PCBs at home.

Arduino clones appeared, many of them using the open source schematics from the Arduino Project. This meant that they were compatible with the Arduino IDE, making it easy for people to adopt. Often their code worked without any changes. New form factors were introduced by the Arduino Project, and other new boards appeared from other sources. Even non Arduino boards and non AVR processors could be supported by additions to the Arduino IDE. Today if you go look for Arduino compatible and ‘like’ development boards, you will be confronted by a large array of choices. Large semiconductor companies with their own processors, some of them ARM based, took noticed and developed their own boards and started bringing them the Maker Faire, which draws over 120,000 people in one weekend, in the San Francisco Bay area.

At the recent ARM TechCon, ST was handing out free development STM32L032 boards that use the ARM Cortex M0 core, a low power processor. However this board uses a non-Arduino tool chain, and setting it up requires some effort. This might be fine or someone who wants to develop a Cortex M0 system for a product and does not need the community of knowledge and code that the Arduino has. But the boards are attractively priced and it looks like there are some independent projects to build an Arduino compatible IDE.

Intel has not been absent from this market. They along with ST, Freescale, and others see the potential in this market. This is especially true as these boards gain wireless connectivity, like Bluetooth and even Wifi. Intel has just release a very small form factor board, called Edison, with a 22nm multi core processor using 2 ATOM cores running at 500Mhz. While it is running Yocto Linux, it offers the option of being programmed with the Arduino IDE. Of course you might prefer to write C++ or node.js for the Linux environment, but for getting started the Arduino IDE is hard to beat. This is not their first effort; they have had another board called Galileo out for some time.

But the new Edison board is different. For about $50 it has built in Bluetooth and Wifi, all in an extremely small, but non-standard, form factor. However Intel partnered with one of the well-known Maker retailers, SparkFun.com, to develop carrier boards that do offer the standard Arduino pin-out geometry. It comes with generous code and data space, 4 GB EMMC and 1GB LPDDR3 respectively. Also one of the cores on the die is a 100MHz Quark core that will run an RTOS developed by Intel’s Wind River subsidiary. Presumably serious IoT and wearable product developers will look to this platform as a powerful, low power and compact vehicle for their designs.

We are in the midst of a rapidly growing and changing landscape for small, powerful and easy to integrate and develop for embedded systems. Not even the Arduino Project is standing still. Their first ARM based board was the Due, and used an ATMEL ARM Cortex M3 core. They have already introduced the Yun, which in addition to the traditional 8 bit AVR processor, has an Atheros AR9331 core with an Open-Wrt based Linux along with Wifi to support a REST protocol interface API in the Arduino IDE. And an even newer offering from the Arduino Project has an ATMEL 32 bit ARM Cortex M0+ core to do both the user code execution and manage wireless interfaces. And of course the Arduino IDE can be used for the software development, just like the original 8 bit Arduino boards.

October 9, 2014June 14, 2019

StarVision to Debug and Analyze Designs at All Levels

StarVision to Debug and Analyze Designs at All Levels
by Pawan Fangaria on 10-09-2014 at 4:00 pm
Categories: Concept Engineering, EDA

In today’s SoC world where multiple analog and digital blocks along with IPs at different levels of abstractions are placed together on a single chip, debugging at all levels becomes quite difficult and clumsy. While one is working at the top level and needs to investigate a particular connection at an intermediate hierarchical level, she has to pass through several steps. Similarly one has to go through specified procedures when merging blocks at different levels of abstraction in a design. What if we have an automated tool which provides an integrated environment for all levels (e.g. RTL, Gate and Transistor) in mixed-signal designs in a single cockpit which can also be customized according to designers’ need? It will significantly improve designers’ productivity in integrating, analyzing and debugging SoC designs.

Yesterday, I came across a five minutes video demoon Concept Engineering’sStarVision tool posted on EDA Directwebsite. Although I have signed-up for Concept’s upcoming webinar on 21[SUP]st[/SUP] Oct, I just dived down this video. It was awesome in introducing the integration and navigation part of StarVision with a real example on how an RTL or a Spice level block can be merged into a design while staying in the same GUI and then stepping through several levels of hierarchy, views, cross probing etc. I could easily visualize how easy it would be for designers to analyze and debug the design using this environment.

This is an example of an IP; the top level is in Verilog with three instances – CPU, SYS and Parity. On the right side is the image of the CPU block which is loaded into the design. Any level of hierarchy inside the CPU block can be easily descended and probed against its code in Verilog.

Driving down the CPU block one can see the content coming from Verilog netlist. Above is the image of a multiplier instance inside the CPU. Its Verilog code view can be opened and probed against the schematic. The probing can be done from both sides.

Now let’s say SYS block which is at RTL level in Verilog has to be loaded and merged with the design.

The above picture shows the Verilog merge option and the top level view after SYS block loaded. The SYS block can again be navigated through for viewing and analyzing its contents down the whole hierarchy.

The Parity block is at transistor netlist level and has the Spice code view. This block is also loaded through hspice merge option as shown above. The demo shows driving down this block as well and cross probing between transistor level schematic and Spice netlist at any point in the hierarchy.

Cone window is an excellent feature through which any signal can be picked from the schematic at any level and clicked through to load objects connected to it. One can navigate through multiple levels of hierarchy at the same time staying in the same GUI and display all the different levels of inputs in the same view.

This is just a small demo which shows loading and navigating through different views of the design. There are host of other important features which makes a designer’s life easy in debugging complex SoC and IC design in complete transparent manner. To mention a few of them are – extraction of circuit fragments and saving as Spice netlists for investigation and re-use, easy design exploration by symbol creation from Spice netlists, dragging & dropping of selected components between all design views, analysis of parasitic networks and creation of Spice netlist for critical path simulation, ERC checking, and many more.

EDA Direct is organizing a free webinar which will provide complete details about Concept Engineering’s StarVision[SUP]TM[/SUP] PROcapabilities along with its usage of in-built utilities to provide a versatile environment for easily analyzing, debugging and integrating SoCs and ICs. The webinar’s schedule is as follows –

Date: 21 October, 2014
Time: 10:00 AM – 11:00 AM PDT
Media: Online via WebEx

Today, 16 out of top 20 semiconductor companies are using Concept Engineering visual debugging technologies. It will be worth spending one hour to know about actual details of this debugging environment.

Contact info@concept.de and sales@edadirect.com for any more information.