SemiWiki – Page 73 – The Open Forum for Semiconductor Professionals

April 15, 2024May 14, 2024

Managing Power at Datacenter Scale

Managing Power at Datacenter Scale
by Bernard Murphy on 04-15-2024 at 6:00 am
Categories: AI, Analytics, proteanTecs

That datacenters are power hogs is not news, especially now AI is further aggravating this challenge. I found a recent proteanTecs-hosted panel on power challenges in datacenter infrastructure quite educational both in quantifying the scale of the problem and in understanding what steps are being taken to slow growth in power consumption. Panelists included Shesha Krishnapur (Intel fellow and IT CTO), Artour Levin (VP, AI silicon engineering at Microsoft). Eddie Ramirez (Arm VP for Go-to-Market in the infrastructure line of business), and Evelyn Landman (Co-founder and CTO at proteanTecs). Mark Potter (VC and previously CTO and Director of HP Labs) moderated. This is an expert group directly responsible for or closely partnered with some of the largest datacenters in the world. What follows is a condensation of key points from all speakers.

Understanding the scale and growth trends

In 2022 US datacenters accounted for 3.5% of total energy consumption in the country. Intel sees 20% compute growth year over year which through improved designs and process technologies is translating into a 10% year over year growth in power consumption.

But that’s for CPU-based workloads. Sasha expects demand from AI-based workloads will grow at twice that rate. One view is that a typical AI-accelerated server is drawing 4X the power of a conventional server. A telling example suggests that AI-based image generation consumes almost 10X the power of just trying to find images online. Not an apples and apples comparison of course but if the AI option is easier and produces more intriguing results, are end-users going to worry about power? AI has the potential to turn an already serious power consumption problem into a crisis.

For cooling/thermal management the default today is still forced air cooling, itself a significant contributor to power consumption. There could be better options but re-engineering existing infrastructure for options like liquid/immersion cooling is a big investment for a large datacenter; changes will move slowly.

Getting back onto a sustainable path

Clearly this trend is not sustainable. There was consensus among panelists that there isn’t a silver bullet fix and that datacenter power usage effectiveness (PUE) must be optimized system-wide through an accumulation of individually small refinements, together adding up to major improvements.

Shesha provided an immediate and intriguing example of improvements he has been driving for years in Intel datacenters worldwide. The default approach, based on mainframe expectations, had required cooling to 64-68^oF to maximize performance and reliability. Research from around 2010 suggested improvements in IT infrastructure would allow 78^oF as a workable operating temperature. Since then the limit has been pushed up higher still, so that PUEs have dropped from 1.7/1.8 to 1.06 (at which level almost all the power entering the datacenter is used by the IT equipment rather than big cooling systems).

In semiconductor design everyone stressed that power optimization will need to be squeezed through an accumulation of many small improvements. For AI, datacenter inference usage is expected to dominate training usage if AI monetization is going to work. (Side note: this has nothing to do with edge-based inference. Business applications at minimum are likely to remain cloud based.) One way to reduce power in inference is through low-precision models. I wouldn’t be surprised to see other edge AI power optimizations such as sparse matrix handling making their way into datacenters.

Conversely AI can learn to optimize resource allocation and load balancing for varying workloads to reduce net power consumption. Aligning compute and data locations and packing workloads more effectively across servers will allow for more inactive servers which can be powered down at any given time.

Naturally Eddie promoted performance/watt for scale-out workloads; Arm have been very successful in recognizing that one size does not fit all in general-purpose datacenters. Servers designed for high performance compute must coexist with servers for high traffic tasks like video-serving and network/storage traffic optimization. Each tuned for different performance/watt profiles.

Meanwhile immersion and other forms of liquid cooling, once limited to supercomputer systems, are now finding their way into regular datacenters. These methods don’t reduce IT systems power consumption, but they are believed to be more power-efficient in removing heat than traditional cooling methods, allowing for either partial or complete replacement of forced air systems over time.

Further opportunities for optimization

First, a reminder of why proteanTecs is involved in this discussion. They are a very interesting organization providing monitor/control “agent” IPs which can be embedded in a semiconductor design. In mission mode these can be used to supply in-field analytics and actionable insights on performance, power and reliability. Customers can for example use these agents to adaptively optimize voltages for power reduction while not compromising reliability. proteanTecs claim demonstrated 5% to 12% power savings across different applications when using this technology.

Evelyn stressed that such approaches are not only a chip level techonology. The information provided must be processed in datacenter software stacks so that workload optimization solutions can take account of on-chip metrics in balancing between resources and systems. Eddie echoed this point in adding that the more information you have and the more telemetry you can provide the software stack, the better the stack can exploit AI-based power management.

Multi-die systems are another way to reduce power since they bring otherwise separate components closer together, avoiding power-hungry communication through board traces and device pins.

Takeaways

For semiconductor design teams, expect power envelopes to be squeezed more tightly. Since thermal mitigation requirements are closely coupled to power, expect even more work to reduce hotspots. Also expect to add telemetry to hardware and firmware to guide adaptive power adjustments. Anything that affects service level expectations and cooling costs will go under the microscope. Designers may also be borrowing more power reducing design techniques from the edge. AI design teams will be squeezed extra hard 😀 Also expect a bigger emphasis on chiplet-based design.

In software stacks, power management is likely to become more sophisticated for adaptation to changing workloads in resource assignments and power down for systems not currently active.

In racks and the datacenter at large, expect more in-rack or on-chip liquid-based cooling, changing thermal management design and analysis at the package, board and rack level.

Lots to do! You can learn more HERE.

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EP217: The Impact and Unique Business Model of Silicon Creations with Randy Caplan

EP217: The Impact and Unique Business Model of Silicon Creations with Randy Caplan
by Daniel Nenni on 04-12-2024 at 10:00 am

Dan is joined by Randy Caplan, co-founder and CEO of Silicon Creations, and a lifelong technology enthusiast. For almost two decades, he has helped grow Silicon Creations into a leading mixed-signal semiconductor IP company with nearly 500 customers spanning almost every major market segment.

Randy provides some background on Silicon Creations unique bootstrapped business model. Today, the company provides critical analog/mixed signal IP to many customers across a wide variety of markets. Silicon Creations has delivered IP in apprixantely 85 process nodes.

Randy explores how the company has succeeded and assesses what its impact will be in the future.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

April 12, 2024April 15, 2024

Silicon Catalyst partners with Arm to launch the Arm Flexible Access for Startups Contest!

Silicon Catalyst partners with Arm to launch the Arm Flexible Access for Startups Contest!
by Daniel Nenni on 04-12-2024 at 6:00 am
Categories: Arm, Events, Semiconductor Services, Silicon Catalyst

Winner and Runner-up to receive the contest’s largest ever technology credit for production tape-outs.

This is an example of why I enjoy working with Silicon Catalyst. They collaborate with our partners and do some really impressive things, all for the greater good of the semiconductor industry, absolutely. If you are not currently engaged with the Silicon Catalyst ecosystem you need to be.

With the overwhelming success of last year’s contest which resulted in $150,000 in Arm technology credit awarded to the winner, this year the bounty has been increased to $250,000 to the top startup.

The 2024 Arm Flexible Access for Startups Contest is open to privately owned startup companies in pre-seed, seed and Series A funding that have raised a maximum of $20 million in funding. The applicant companies need to either be using Arm or considering using Arm in their products. An Arm technology credit of $250,000 and $150,000, will be awarded to the winner and runner-up, respectively, and can be used towards a commercial tape-out and could cover IP fees for a complete embedded system or contribute to the cost of a higher performance system. Both the winner and runner-up will also receive additional benefits, including a pitch review session hosted by the Silicon Catalyst Angels investment group. All contest applicant organizations will also be considered for acceptance to the Silicon Catalyst Incubator/Accelerator.

Last year’s winner Equal1 is a pioneering silicon quantum computing company dedicated to making quantum computing affordable and accessible:

“We are thrilled to be announced as the winner of the 2023 ‘Silicon Startups Contest’. Arm’s support, partnership, and technology credit are invaluable to the development of our QSoC processors. Just as the evolution of classical computers was driven by advancements in silicon processors, we firmly believe quantum computing will follow the same silicon path. Like the majority of chips today, the new era of quantum computing will be powered by Arm, with a focus on power efficiency, performance, proven reliability, and a robust ecosystem.”

– Jason Lynch, CEO, Equal1 Labs

This year, the overall winner receives $250,000 Arm technology credit toward an Arm Flexible Access commercial tape-out. The runner-up receives $150,000 Arm Technology Credit towards an Arm Flexible Access commercial tape-out. The winner and runner-up will also receive:

A free Arm Design Review to enable Arm to review the customer’s design specification, Ticket to Arm’s invite-only ecosystem event for networking and a chance to be featured, and a pitch review session hosted by the Silicon Catalyst Angel investment group.

Additionally, Paul Williamson, Senior Vice President and General Manager, IoT Line of Business at Arm said:

“Arm technology is for everyone, and through this contest, we are recognizing and supporting the next wave of innovators to grow their business and accelerate their SoC designs. We know that time to product and access to the largest possible market are critical for startups, which is why we created Arm Flexible Access for Startups, providing $0 access to a wide portfolio of IP, tools and support, to maximize their chance of success.”

If you remember, we wrote the definitive book on Arm “Mobile Unleashed: The Origin and Evolution of the Arm Processor in our Devices” and we have written hundreds of related Arm articles. This contest is an incredible opportunity to work closely with the #1 processor IP company and the world’s only incubator focused exclusively on accelerating semiconductor solutions.

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April 11, 2024April 8, 2024

Synopsys Design IP for Modern SoCs and Multi-Die Systems

Synopsys Design IP for Modern SoCs and Multi-Die Systems
by Kalar Rajendiran on 04-11-2024 at 10:00 am
Categories: AI, EDA, IP, Security, Synopsys

Synopsys IP Scale, a Sustainable Advantage

Semiconductor intellectual property (IP) plays a critical role in modern system-on-chip (SoC) designs. That’s not surprising given that modern SoCs are highly complex designs that leverage already proven building blocks such as processors, interfaces, foundational IP, on-chip bus fabrics, security IP, and others. This is reflected by a flourishing third-party IP market segment that reached $7.05B in 2023 [Source: IP Nest Reports].

With ~$1.54B of Design IP revenue in 2023, Synopsys holds the #2 position in the third-party IP market segment worldwide and is the leader in interface IP and foundation IP. The company did not get to this position overnight. Synopsys has taken a deliberate and strategic approach to building its IP business over time. Over a course of 25 years, Synopsys has diligently cultivated the world’s broadest IP portfolio spanning building blocks/peripherals, interfaces, foundation IP (standard cells, memories), processors, security, AI accelerators (NPUs, DSP), sensors and more. It is interesting to note that while the third-party IP market grew a little over 6% between 2022 and 2023, Synopsys’ Design IP business grew at about 18%. The company reaffirmed and recommitted to a sustainable mid-teens growth rate for their Design IP business.

Customer-Centric Approach

At the heart of Synopsys’ success lies its unwavering commitment to customer satisfaction. Through unparalleled IP quality, exceptional support, and a reputation for reliability, Synopsys has earned the trust of semiconductor as well as systems companies worldwide. Testimonials from industry partners and customers underscore Synopsys’ reputation as the preferred choice for semiconductor IP solutions.

The following chart shows the results from a blind survey by an independent company.

Synopsys continues to reaffirm its commitment to excellence by prioritizing quality, innovation, and customer support. The company continues to demonstrate its investment commitment by adding both organically developed IP and acquired IP to its portfolio. A couple of recent examples are Synopsys’ Universal Chiplet Interconnect Express (UCIe) IP and its Physical Unclonable Function (PUF) IP through acquisition of Intrinsic ID. This kind of strategic expansion continues to position Synopsys as a trusted partner for semiconductor designs, empowering customers to realize their design goals with confidence.

UCIe IP for Heterogeneous Interoperability of Multi-Die Systems

With the rise of heterogeneous computing architectures and the proliferation of AI and machine learning workloads, designers must increasingly consider both silicon-level and system-level optimizations when designing their products. Multi-die systems are key to the next wave of systems innovations and enable the integration of heterogeneous dies in a single package. The Universal Chiplet Interconnect Express (UCIe) standard was introduced in 2022 to address this heterogeneous die-to-die interoperability need. By standardizing communication between chiplets, UCIe not only simplifies the integration process but also fosters a broader ecosystem where chiplets from different vendors can seamlessly be incorporated into a single design.

One of the things Synopsys’ CEO Sassine Ghazi emphasized during his keynote talk at the Synopsys User Group (SNUG) conference is the importance of multi-die solutions. He spotlighted Intel’s Pike Creek, the world’s first UCIe-enabled silicon, a result of collaboration between Intel, TSMC and Synopsys.

As an auxiliary point, with the evolution to heterogenous SoCs, Synopsys’ EDA tools are tightly integrated with its IP portfolio, allowing for seamless interoperability and faster time-to-market.

PUF IP for Security

Given the increasing sophistication of cyber threats these days, the integrity and security of semiconductor designs are of paramount importance. With the proliferation of connected devices, ensuring the confidentiality and integrity of sensitive data has become increasingly crucial for semiconductor manufacturers and system integrators alike.

Synopsys recently completed the acquisition of Intrinsic ID, a pioneer in PUF IP technology. PUF technology harnesses the inherent variations in silicon chips to generate unique identifiers, offering robust protection against a range of security threats including counterfeiting, tampering, and unauthorized access. By integrating Intrinsic ID’s PUF IP into its portfolio, Synopsys empowers chip designers to embed security features directly into their designs, expediting time-to-market and reducing costs. The acquisition not only expands Synopsys’ IP offerings but also enriches its talent pool with a team of experienced R&D engineers deeply knowledgeable in PUF technology. Synopsys intends to leverage Intrinsic ID’s presence in the Netherlands to establish a center of excellence for PUF technology in Eindhoven, enhancing its research and development capabilities in the critical area of security IP.

Summary

As technology continues to advance and new challenges emerge, Synopsys remains committed to delivering best-in-class solutions and driving the industry forward. With dedication to customer satisfaction and a sustainable advantage, Synopsys is positioned to lead the way in semiconductor IP for years to come. Its drive for innovation, and customer-centricity ensures its place as a trusted partner for semiconductor and systems companies worldwide.

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April 11, 2024April 11, 2024

Enhancing the RISC-V Ecosystem with S2C Prototyping Solution

Enhancing the RISC-V Ecosystem with S2C Prototyping Solution
by Daniel Nenni on 04-11-2024 at 6:00 am
Categories: EDA, Prototyping, RISC-V, S2C EDA

RISC-V’s popularity stems from its open-source framework, enabling customization, scalability, and mitigating vendor lock-in. Supported by a robust community, its cost-effectiveness and global adoption make it attractive for hardware innovation across industries.

Despite its popularity, evolving RISC-V architectures pose design and verification challenges. A significant concern is the potential fragmentation in RISC-V system integration. Exploring RISC-V microarchitectures may result in variants incompatible with each other. Moreover, as the RISC-V ecosystem matures, design complexity escalates, necessitating enhanced verification procedures.

S2C plays a pivotal role in the RISC-V ecosystem as a member of RISC-V International. Let’s explore how S2C aids chip designers in optimizing and differentiating their RISC-V processor-based SoCs across diverse applications.

Key Benefits of the S2C FPGA Prototyping Solution for RISC-V

S2C offers an extensive array of FPGA prototyping systems, ranging from the desktop prototyping platform Prodigy Logic System to the high-performance enterprise prototyping solution Logic Matrix, catering to the diverse needs of RISC-V System Verification or Demonstration. Multiple options are available to meet the diversity of RISC-V, regardless of the scale of the design. In addition to traditional partitioning schemes, S2C also provides ChipLink IP, which ensures high-performance AXI chip-to-chip partitioning.

Robust bring-up and debugging methods enhance user efficiency, including FPGA download via Ethernet/USB/SD card, UART/Virtual UART, Ethernet-based AXI transactor, and a custom logic analyzer for Multi-FPGA (MDM).

S2C also provides a utility to download operating systems & applications from PC to FPGA’s DDR4.

The high-bandwidth transmission enables a much faster boot-up of software, accelerating time to operation.

General Purpose Partitioning and ChipLink

S2C offers a General-Purpose TDM interconnect communication solution, which is applicable regardless of IP logic scale or bus interface type limitations. Configured as a 25Gbps Line Rate, S2C’s General-Purpose Serdes TDM IP can provide up to 20MHz of TDM partitioning for large IP design partitions. With a multiplexing ratio of up to 8K:1, it enables long-distance data communication via optical fiber cables, streamlining the networking process for large-scale SoC prototype designs with simplicity and efficiency.

ChipLink, an AXI-based partitioning solution, facilitates multi-core SoC verification. This low-latency AXI Chip to Chip IP connects RISC-V cores and peripherals across multiple FPGAs efficiently. S2C’s ChipLink AXI IP boasts high speed and low latency, supporting AXI DATA_WIDTH of up to 1024 bits. Each bank accommodates up to four sets of AXI protocols. With multiple Serdes line rates including 12.5G, 16.25G, 20.625G, and 25G, it enables communication at 100MHz between multi-core processors.

Strengthened by a Broad Prototype Tools

S2C offers a comprehensive suite of tools to facilitate and optimize RISC-V SoC design verification. Notably, Prototype Ready IP features over 90 readily deployable daughter cards, simplifying prototyping setup and significantly reducing initialization time and effort.

Additionally, S2C’s multidimensional prototyping software, Prodigy PlayerPro-RT, enables seamless FPGA/Die downloads via USB, Ethernet, and SD Card interfaces. Beyond downloads, PlayerPro-RT offers real-time hardware monitoring, remote system management, and extensive hardware self-testing functionalities, ensuring a smooth and efficient verification process.

S2C further enhances verification with the inclusion of the high-bandwidth AXI transactor, Prodigy ProtoBridge, facilitating swift and efficient data transmission between PC and FPGA prototypes at PCIe speeds of up to 4000MB/s. By offering high bandwidth and fast read/write capabilities, ProtoBridge significantly boosts design productivity.

In the competitive realm of RISC-V SoC development, differentiation is crucial. S2C Prototyping Solutions emerge as a trusted ally, offering a streamlined pathway for verification and demonstration, empowering developers to amplify the unique value propositions of their SoCs.

For more information: https://www.s2cinc.com/riscv.html

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April 10, 2024February 13, 2025

Intel is Bringing AI Everywhere

Intel is Bringing AI Everywhere
by Mike Gianfagna on 04-10-2024 at 10:00 am
Categories: AI, Events, Foundries, Intel Foundry

On April 8 and 9 Intel held its Intel Vision event in Phoenix Arizona. This is Intel’s premier event for business and technology executive leaders to come together and learn about the latest industry trends and solutions in advancements from client, to edge, to data center and cloud. The theme of this year’s event was Bringing AI Everywhere. The event was packed with impressive information from all over the industry. Intel provided a briefing before the event that dove into some of the announcements and advances that would be presented. I will dig into what was presented in this post, along with a summary of Pat Gelsinger’s keynote at the event. The content is compelling – indeed it appears that Intel is bringing AI everywhere.

Briefing Overview

Attending the briefing were three key members of the Intel team. Their combined experience is quite impressive. They are:

Sachin Katti, Senior Vice President & General Manager of Network and Edge Group. Prior to his current role, Sachin was CTO of the Network and Edge Group. Prior to Intel, he had a long career as an Associate Professor at Stanford University. He also founded or co-founded several companies as well. Sachin holds a Ph.D. in Computer Science from the Massachusetts Institute of Technology.

Das Kamhout, Vice President & Senior Principal Engineer in the Intel Data Center and AI Group. Das has worked at Intel for 27 years across many areas including AI, cloud, enterprise software, and storage. He has also been a Board member of the Cloud Native Computing Foundation.

Jeff McVeigh, Corporate Vice President & General Manager of Software Engineering Group. Jeff has also worked at Intel for 27 years. He has held leadership positions in the Software Engineering Group, Super Compute Group, Data Center XPU Products & Solutions, and Visual Computing Products. He holds a Ph.D. in Electrical and Computer Engineering from Carnegie Mellon University.

The presentation began with some macro-observations. Enterprises have reached an AI inflection point, signified by swift adoption and supercharged by GenAI. Gartner estimates that 80% of enterprises will use GenAI by 2026 and at least 50% of edge computing deployments will involve machine learning. IDC expects the $40B enterprise spend on GenAI in 2024 to grow to $151B by 2027.

All this is ahead of us only if we’re able to unlock AI’s full potential. Intel reported that only 10% of organizations launched generative AI solutions to production in 2023. Furthermore, 46% of experts cited infrastructure as the biggest challenge in productionizing large language models. Barriers to adoption persist, openness and choice are limited and transparency, privacy and trust concerns are rising.

Against this backdrop Intel is making several announcements to take down the barriers to adoption, bringing AI everywhere. The five broad areas of focus were defined as follows:

A scalable systems strategy to address all segments of AI within the enterprise with an open ecosystem approach
Enterprise customer AI deployments, successes and wins
Open ecosystem approach to advance enterprise AI
Intel Gaudi® 3 AI accelerator to serve unmet demand for Generative AI solutions
Edge Platform and Ethernet-based networking connectivity products targeted for AI workloads

Let’s look at some of the details.

A Tour of the Announcements

Today, enterprise data and AI models live in two distinct worlds. Enterprise data is secure and confidential, rooted in specific locations, mature and predictable and has a CPU-based processing model. AI models, on the other hand are based on public data, are characterized by rapid change with varied degrees of security and have an accelerator-based processing model.

Intel aims to unlock the enterprise AI model through the power of open ecosystems. Attributes of this approach include:

An Application Ecosystem that is easy and open, by working with industry leaders to provide end-to-end AI enterprise solutions at scale
A Software Ecosystem that is secure and responsible, by driving an open software ecosystem that bridges enterprise data and AI models
An Infrastructure Ecosystem that is scalable and reference based, by shaping the enterprise AI infrastructure through reference architectures, together with partners
A Compute Ecosystem that is accessible and confidential, by building safe and AI capable compute platforms from client to data center

The diagram below is a top-level view of how these pieces fit together. Many more details of the approach were presented, along with a description of the enterprise AI software stack and planned enhancements.

Intel Enteprise AI

The presentation also discussed Intel Developer Cloud that is used by leading AI companies. Intel explained that the platform provides everything you need to build and deploy AI at scale. The diagram below shows today’s processor lineup.

The newest version of the Intel Gaudi AI accelerator brings speedups of 2X – 4X for AI compute, 2X for network bandwidth and 1.5X for memory bandwidth. Benchmark data includes 40% faster time-to-train vs. H100 and 50% faster inferencing vs. H100. The launch partners for this accelerator are impressive, with Dell Technologies, HP Enterprise, Lenovo, and Supermicro.

The Intel Xeon6 Processor with E-cores was also discussed with a 2.4x performance per watt improvement and 2.7x performance per rack improvement. Comparing the second generation Intel Xeon processor to Xeon 6, there is over one megawatt of power reduction delivered. To put that number in perspective, it represents the energy savings of a full year’s worth of electricity use for over 1,300 homes.

The work Intel is doing with high-profile partners on confidential computing was also discussed. A preview of work to deliver connectivity designs for AI was previewed as well. The AI PC era was also discussed. Here, Intel plans to ship 100 million AI accelerators by the end of 2025. The company’s footprint in this market is substantial. Comprehensive strategies and platforms to support AI processing at the edge were also detailed, with 90,000+ edge deployments and 200M+ processors sold.

Pat Gelsinger’s Keynote

Pat Gelsinger

Pat was introduced as Intel’s Chief Geek. He lived up to that description with a 90-minute technology tour-de-force describing Intel’s impact, announcements, and plans. AI was front and center for most of Pat’s presentation. He described Intel Foundry as the systems foundry for the AI era and Intel products as modular platforms for the AI era. A memorable quote from Pat is “every company becomes an AI company.”

Pat then described the major re-tooling that is underway to deploy AI PCs across the entire enterprise. He discussed products that enable AI across the enterprise while reducing power and increasing efficiency. There were several impressive live demos of new technology and its impact, including an AI PC demo livestreamed from inside an Intel fab.

Pat also invited many distinguished guests to join him on stage or via the Internet to describe what their organizations are doing with Intel technology. Among those organizations were Accenture, Supermicro, Arizona State University, Bosch, Naver Corporation, and Dell Technologies (with Michael Dell).

Pat also unveiled, for the first time, the Intel Gaudi 3 AI Accelerator. This is a short summary of a great keynote presentation.

To Learn More

The pre-brief presentation and Pat Gelsinger’s keynote covered a lot of detail across an open scalable system strategy, customer/partner momentum, and next-generation products/services. You can learn more about Intel Vision 2024 here and you can watch a replay of Pat Gelsinger’s keynote here. You will see that Intel is bringing AI everywhere.

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April 10, 2024April 19, 2024

Arteris Frames Network-On-Chip Topologies in the Car

Arteris Frames Network-On-Chip Topologies in the Car
by Bernard Murphy on 04-10-2024 at 6:00 am
Categories: AI, Arteris, Automotive, IP

On the heels of Arm’s 2024 automotive update, Arteris and Arm announced an update to their partnership. This has been extended to cover the latest AMBA5 protocol for coherent operation (CHI-E) in addition to already supported options such as CHI-B, ACE and others. There are a couple of noteworthy points here. First, Arm’s new Automotive Enhanced (AE) cores upgraded protocol support from CHI-B to CHI-E and Arm/Arteris have collaborated to validate the Arteris Ncore coherent NoC generator against the CHI-E standard. Second, Arteris has also done the work to certify Ncore-generated networks with the CHI-E protocol extension for ASIL B and ASIL D. (Ncore-generated networks are already certified for earlier protocols, as are FlexNoC-generated non-coherent NoC networks.) In short, Arteris coherent and non-coherent NoC generators are already aligned against the latest Arm AE releases and ASIL safety standards. Which prompts the question: where are coherent and non-coherent NoCs required in automotive systems? Frank Schirrmeister (VP Solutions and Business Development at Arteris) helped clarify my understanding.

Automotive, datacenter/HPC system contrasts

Multi-purpose datacenters are highly optimized for task throughput per watt per $. CPU and GPU designs exploit very homogenous architectures for high levels of parallelism, connecting through coherent networks to maximize the advantages of that parallelism while ensuring that individual processors do not trip over each other on shared data. Data flows into and out of these systems through regular network connections, and power and safety are not primary concerns (though power has become more important).

Automotive systems architectures are more diverse. Most of the data comes from sensors – drivetrain monitoring and control, cameras, radars, lidars, etc. – streaming live into one or more signal processor stages, commonly implemented in DSPs or (non-AI) GPUs. Processing stages for object recognition, fusion and classification follow. These stages may be implemented through NPUs, GPUs, DSPs or CPUs. Eventually, processed data flows into central decision-making, typically a big AI system that might equally be at home in a datacenter. These long chains of processing must be distributed carefully through the car architecture to meet critical safety goals, low power goals and, of course, cost goals. As an example, it might be too slow to ship a whole frame from a camera through a busy car network to the central AI system, and then to begin to recognize an imminent collision. In such cases, initial hazard detection might happen closer to the camera, reducing what the subsystem must send to the central controller to a much smaller packet of data.

Key consequences of these requirements are that AI functions are distributed as subsystems through the car system architecture and that each subsystem is composed of a heterogenous mix of functions, CPUs, DSPs, NPUs and GPUs, among others.

Why do we need coherence?

Coherence is important whenever multiple processors are working on common data like pixels in an image, where there is opportunity for at least one processor to write to a logical address in a local cache and another processor to read from the same logical address in a different cache. The problem is that the second processor doesn’t see the update made by the first processor. This danger is unavoidable in multiprocessor systems sharing data through hierarchical memory caches.

Coherent networks were invented to ensure disciplined behavior in such cases, through behind-the-scenes checking and control between caches. A popular example can be found in coherent mesh networks common in many-core processor servers. These networks are highly optimized for regular structures, to preserve the performance advantages of using shared cache memory while avoiding coherence conflicts.

Coherence needs are not limited to mesh networks threading through arrays of homogenous processors. Most of the subsystems in a car are heterogeneous, connecting the multiple different types of functions already discussed. Some of these subsystems equally need coherence management when processing images through streaming operations. Conversely, some functions may not need that support if they can operate in separate logical memory regions, or if they do not need to operate concurrently. In these cases, non-coherent networks will meet the need.

A key consequence is that NoCs in an automotive chip must manage both coherent and non-coherent networks on a chip for optimal performance.

Six in-car NoC topologies

Frank illustrated with Arm’s use cases from their recent AE announcement, overlaid with the Arteris view of NoC topologies on those use cases (see the opening figure in this blog).

Small microcontrollers at the edge (drivetrain and window controllers for example) don’t need coherency support. Which doesn’t mean they don’t use AI – predictive maintenance support is an active trend in MCUs. But there isn’t need for high-performance data sharing. Non-coherent NoCs are ideal for these applications. Since these MCUs must sit right next to whatever they measure/control, they are located far from central or zonal controllers and are implemented as standalone (monolithic) chips.

Per Frank, zonal controllers may be non-coherent or may support some coherent interconnect, I guess reflecting differences in OEM architecture choices. Maybe streaming image processing is handled in sensor subsystems, or some processing is handled in the zonal controller. Then again, he sees vision/radar/lidar processing typically needing mostly non-coherent networks with limited coherent network requirements. While streaming architectures will often demand coherence support, any given sensor may generate only one or a few streams, needing at most a limited coherent core for initial recognition. Zonal controllers, by definition, are distributed around the car so are also monolithic chip solutions.

Moving into the car cockpit, infotainment (IVI) is likely to need more of a mix of coherent and non-coherent support, say for imaging overlaid with object recognition. These systems may be monolithic but also lend themselves to chiplet implementations. Centralized ADAS control (fusing inputs from sensors for lane recognition, collision detection, etc.) for SAE level 2+ and beyond will require more coherence support, yet still with need for significant non-coherent networks. Such systems may be monolithic today but are trending to chiplet implementations.

Finally, as I suggested earlier the central AI controller in a car is fast becoming a peer to big datacenter-like systems. Arm has already pointed to AE CSS-based Neoverse many-core platforms (2025) front-ending AI accelerators (as they already do in Grace-Hopper and I’m guessing Blackwell). Add to that big engine more specialized engines (DSPs, NPUs and other accelerators) in support of higher levels of autonomous driving, to centrally synthesize inputs from around the car and to take intelligent action on those inputs. Such a system will demand a mix of big coherent mesh networks wrapping processor arrays, a distributed coherent network to connect to some of those other accelerators and non-coherent networks to connect elsewhere. These designs are also trending to chiplet-based systems.

In summary, while there is plenty of complexity in evolving car architectures and the consequent impact on subsystem chip/chiplet designs, connected on-chip through both coherent and non-coherent networks, the intent behind these systems is quite clear. We just need to start thinking in terms of total car system architecture rather than individual chip functions.

Listen to a podcast in which Dan Nenni interviews Frank on this topic. Also read more about Arteris coherent network generation HERE and non-coherent network generation HERE.

April 9, 2024July 15, 2024

LIVE WEBINAR: Automating the Integration Workflow with IP Centric Design

LIVE WEBINAR: Automating the Integration Workflow with IP Centric Design
by Daniel Nenni on 04-09-2024 at 10:00 am
Categories: EDA, Events, Perforce

hip webinar automating integration workflow social

Subsystem and full-chip integration plays a crucial role in any project – particularly for large SoCs. Our upcoming webinar on April 30 confronts the typical challenges of this process and provides a detailed view into how IP centric design can help you solve them. Join us to learn how transforming your design flow can help your team reliably meet integration milestones, quickly debug issues, and enhance work quality and transparency.

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In today’s landscape, the ongoing challenges of integrating design blocks into SoCs are clear. Teams are often working with a globally distributed workforce, overwhelmingly complex design data, and a lack of expertise on design blocks that were not developed locally.

As teams become more geographically dispersed, integration is complicated by the inclusion of more externally sourced and reused IPs, multiple design sites, and the difficulties of working across time zones. At the same time, the size, volume, and complexity of design files have also increased. This high volume of larger, more complex files can strain existing infrastructure and processes, causing delays and confusion. Lastly, a lack of local expertise on design blocks created by geographically distant teams makes it harder to address integration problems as they arise – leading to longer lead times, inefficient, spreadsheet-based debugging, and repeatedly missed integration milestones.

These complex, interrelated pain points introduce the need for a new and innovative approach. This is where an IP centric design methodology steps in. An IP, also referred to as a design block or module, is an abstraction of data files that defines an implementation, along with the meta-data that defines its state. In IP centric design, each element of the design – from internally reused and externally acquired IPs, to the design environment and the whole platform – is modeled as an IP. This allows the entire project and all related metadata to be modeled as a complete, hierarchical collection of IPs, including all versions and dependencies.

By leveraging an IP centric methodology, along with the use of “IP Aliases” and quality-based integration rules, teams can establish a streamlined, controlled, and transparent integration flow. This automated flow will enable teams to reliably meet key integration milestones, more easily debug integration issues, and improve overall quality.

We have some expert tips and essential best practice guidelines for creating, enforcing, and maintaining an IP centric design flow. The Automating the Integration Workflow presentation will give a more in-depth look at what elements are necessary to establishing an effective IP centric model, including annotation with rich metadata and a versioned, hierarchical Bill of Materials (BoM) that all team members can reference. We’ll also dive into how to support and hone your integration flow over time, giving examples of common governance rules your team can implement, as well as tips for how to consistently enforce them.

Getting your team onboard with this transformation and new approach can have a dramatic effect on your collaboration, productivity, go-to-market timeline, and quality. It will greatly reduce the SoC integration challenges your team struggles with, plus set a minimum quality requirement across all IP and provide an at-a-glance view into IP status and which blocks are ready for integration. And finally, establishing a secure and traceable IP centric design flow can make future IP reuse and integration easier.

Join us for our upcoming webinar, where we’ll walk through each step of the integration process through the lens of IP centric design. Register now to learn how to boost both efficiency and quality through a streamlined integration flow!

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Also Read:

2024 Outlook with Adam Olson of Perforce

The Transformation Model for IP-Centric Design

Chiplets and IP and the Trust Problem

April 9, 2024January 24, 2025

The Data Crisis is Unfolding – Are We Ready?

The Data Crisis is Unfolding – Are We Ready?
by Kalar Rajendiran on 04-09-2024 at 6:00 am
Categories: AI, Alphawave Semi, Automotive, Chiplet, IoT, IP
1 Comment

The rapid advancement of technology, including generative AI, IoT, and autonomous vehicles, is revolutionizing industries and enhancing efficiency. At the same time, such advances also generate huge amounts of data to be transmitted and processed to make sense and provide value to consumers and society as a whole. In essence, heavy reliance on seamless data movement and processing have become integral to various aspects of modern life, from transportation logistics to healthcare and climate control. While the benefits are great and many, and include enhanced decision making, personalization, improved healthcare, and efficient resource allocation, there are various types of potential dangers that go hand-in-hand. At a broad level, we could call what we are marching toward as a potential data crisis in the making.

While this potential data crisis has many aspects to it, the most fundamental concern is the ability to continue to transmit and process data at increasingly higher speeds and very low latencies, without any disruption. Alphawave Semi has published a whitepaper on this specific aspect of the data crisis. Such a data crisis could have far-reaching consequences for individuals, society and the global economy. Businesses make market entry decisions based not only on potential opportunities and risk/reward calculations but also on consequential damages claims exposure. But with a heavy reliance on data and a highly interconnected world, it is difficult to isolate oneself or individual applications from this data crisis.

For example, an autonomous vehicle is expected to process 19 terabytes (TB) of data per hour to conduct itself. At a projected 840,000 autonomous vehicles hitting the streets by 2030, this translates to 1.6 million terabytes of data per hour. A disruption of even the slightest degree could have fatal and widespread catastrophic consequences. Another example involves the medical industry which uses digital health records for patient management.

For example, as of 2021, 88% of US-based doctors were relying on a rugged data infrastructure to support their usage. Any inability to process large volumes of data could lead to misdiagnosis events with dire consequences.

In essence, the overall global data infrastructure needs to be aggressively updated and kept up, to meet the ever-growing demand for data connectivity, integrity, safety and privacy.

Securing our Data Infrastructure

Generative AI, heralded as a transformative force in various industries, relies heavily on data infrastructure to realize its full potential. While it holds promise in improving efficiency and driving innovation, the associated power consumption and computational demands underscore the need for sustainable practices and energy-efficient solutions. While accommodating the demanding requirements of AI applications, our data infrastructure must continue to accommodate regular workloads like streaming videos and video calls.

Whether it’s facilitating seamless data transmission or enhancing interconnectivity within hyperscale data centers, semiconductor innovation takes center stage to meet the growing demands of data-intensive workloads. Legacy technologies with monolithic chip structures are insufficient for addressing the mounting computational pressure. Chiplets and custom silicon solutions emerge as game-changers in maximizing efficiency, reducing power consumption, and minimizing latency within data centers. Companies like Alphawave Semi and other industry leaders are spearheading efforts to leverage these technologies, pushing the boundaries of connectivity and scientific advancements.

As we navigate the complexities of the unfolding data crisis, collaboration and adaptability are key. Stakeholders across industries must come together to address the challenges and opportunities presented by the data-driven era. By investing in sustainable practices, embracing technological advancements, making investments, and fostering an ecosystem of innovation, we can look forward to a resilient, efficient, and interconnected digital future.

Summary

The unfolding data crisis presents both challenges and opportunities for our society. By leveraging connectivity, AI, and semiconductor innovation, we can overcome obstacles, drive progress, and usher in a new era of digital transformation and avert a data crisis.

The Alphawave Semi whitepaper on this topic can be downloaded from here.

Also Read:

Accelerate AI Performance with 9G+ HBM3 System Solutions

Alphawave Semiconductor Powering Progress

Will Chiplet Adoption Mimic IP Adoption?

April 8, 2024April 9, 2024

Simulation World 2024 Virtual Event

Simulation World 2024 Virtual Event
by Daniel Nenni on 04-08-2024 at 10:00 am
Categories: Ansys, Inc., EDA, Events

ANSYS Simulation World is an annual conference hosted by ANSYS, Inc., a leading provider of engineering simulation software. The event typically brings together engineers, designers, researchers, and industry experts from around the world to discuss the latest advancements, best practices, and case studies in engineering simulation and virtual prototyping.

Simulation World 2024 is a free global virtual event

Attendees have the opportunity to participate in keynote presentations, technical sessions, hands-on workshops, and networking events. The conference covers a wide range of topics, including computational fluid dynamics (CFD), finite element analysis (FEA), electromagnetics simulation, Multiphysics simulation, additive manufacturing, and more.

The event provides a platform for users of ANSYS software to learn new skills, exchange ideas, and explore innovative applications of simulation technology across various industries, such as aerospace, automotive, electronics, energy, healthcare, and consumer goods.

Additionally, ANSYS Simulation World often features keynote speakers from industry-leading companies, showcasing how simulation-driven engineering has helped them solve complex engineering challenges, improve product performance, and accelerate time-to-market.

Overall, ANSYS Simulation World serves as a premier gathering for the simulation community, offering valuable insights, practical knowledge, and networking opportunities to help engineers and designers stay at the forefront of simulation technology.

EVENT TRACKS

Inspire: Automative and Transportation
Simulation is transforming mobility to address unprecedented challenges and deliver cost effective, completely differentiated solutions, from safer, more sustainable designs to the complex electronics and embedded software that define them.

Inspire: Aerospace and Defense
The aerospace and defense industries must operate on the cutting edge to deliver advanced capabilities. Digital engineering helps them increase flexibility, update legacy programs, and speed new technology into service.

Inspire Energy and Industrials
Industries rely on simulation to streamline production and distribution of safer, cleaner, more reliable energy through fuel-to-power conversions, and to accelerate, scaling of low-carbon energy solutions.

FEATURED SPEAKERS

Dr. Ajei Gopal
President and Chief Executive Officer, Ansys
Ajei Gopal’s idea to drive “pervasive simulation,” or the use of engineering simulation throughout the product life cycle, has transformed the industry. Prior to Ansys, he served in various leadership roles where he demonstrated his ability to simultaneously drive organizational growth and improve operational efficiency.

Dr. Prith Banerjee
Chief Technology Officer, Ansys
Prith Banerjee leads the evolution of Ansys technology and champions the company’s next phase of innovation and growth. During his 35-year technology career — from academia, to initiating startups, to managing innovation in enterprise environments— he has actively observed, and promoted how organizations can realize open innovation success.

Walt Hearn
Senior Vice President, Worldwide Sales and Customer Excellence, Ansys
As an innovative business leader and simulation expert at Ansys, Walt Hearn leads high-performing teams to develop and execute sales strategy, technical excellence, and mentorship across the organization. He prides himself on ensuring customer success and helping organizations achieve top engineering initiatives to change the future of digital transformation.

Here is a quick video on simulation that I think we can all relate to: