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RAAAM Memory Technologies ay the 2024 Design Automation Conference

RAAAM Memory Technologies ay the 2024 Design Automation Conference
by Daniel Nenni on 06-19-2024 at 12:00 pm

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This is the first year that RAAAM is attending DAC and presenting its revolutionary on-chip memory technology. Remember, DAC is the #1 EDA networking event where new technologies are often launched and this is one of many examples for #DAC2024.

Modern chips in various applications, such as Artificial Intelligence (AI) and Machine Learning (ML), Augmented / Virtual Reality (AR/VR), Automotive, 5G, High performance compute in data centres, etc., require ever-growing amounts of on-chip memory (SRAM) to meet the necessary performances under AI workloads. As a result, the amount of SRAM on almost any chip accounts for over 50% of the chip size. Furthermore, Moore’s Law has ended for SRAM, which no longer scales in advanced CMOS process nodes, resulting in limited on-chip memory capacities and significant cost increase for fabrication.

RAAAM’s GCRAM is the most cost-effective on-chip memory technology in the semiconductor industry, providing up-to 50% silicon area reduction and up-to 10X reduced power consumption over SRAM, and it is fully compatible with the standard CMOS fabrication flow, requiring no additional process steps or cost. RAAAM’s patented technology, an outcome of over a decade of R&D efforts, enables the extension of Moore’s Law for on-chip memories and can be used by semiconductor companies as a drop-in replacement for SRAM in their chips.

RAAAM’s GCRAM will allow customers to significantly reduce their chip cost and power consumption, or alternatively double the on-chip memory capacity with no extra cost, significantly reducing 1000X more the power-consumed due to off-chip memory accesses.

RAAAM’s GCRAM was implemented in various process nodes of leading foundries and full technology qualification is performed based on customers’ demand. 5nm and 16nm solutions are in the commercialization phase and migration to additional process technologies will be implemented during 2025.

RAAAM is one of the many companies participating in this industry-leading event, and you are invited to meet our team on the exhibit floor. We look forward to explore how GCRAM technology can help your product. Please contact RAAAM Here to schedule a meeting at booth #1460. I hope to see you there!

About DAC

DAC is recognized as the global event for chips to systems. DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors. The conference is sponsored by the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE) and is supported by ACM’s Special Interest Group on Design Automation (SIGDA) and IEEE’s Council on Electronic Design Automation (CEDA).

About RAAAM Memory Technologies

RAAAM has developed the most cost-effective on-chip memory technology in the semiconductor industry, providing 50% area reduction over high-density SRAM and reduced power consumption by a factor of five. RAAAM’s patented technology can be used by semiconductor companies as a drop-in replacement for SRAM in their SoCs and can be manufactured cost efficiently using the standard CMOS process allowing to significantly reduce the die size. Founded in 2021, the company is headquartered in Israel with R&D center in Switzerland.

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Primarius Technologies at the 2024 Design Automation Conference

Primarius Technologies at the 2024 Design Automation Conference
by Daniel Nenni on 06-19-2024 at 10:00 am

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DAC attendees who stop by the Primarius Technologies booth (#1415) will be greeted by the breadth of its product portfolio that meet time-to-market windows and optimize designs for better yield, power, performance and area.

That includes ESDiTM, a chip-level human body model (HBM) analysis platform and PTMTM, a power device design and layout verification tool family, from Primarius’ acquisition of Magwel N.V., provider of 3D solver- and simulation-based layout analysis and design solutions for digital, analog/mixed-signal, power management, automotive and RF ICs.

Demonstrations will highlight Primarius’ fast, accurate modeling and cell library characterization and circuit simulation solutions based on its continuous innovation and R&D expertise, including:

  • SDEPTM, the spec-driven extraction platform that builds auto model extraction flows for fast SPICE model extraction, an engine enabling efficient Design-Technology Co-Optimization (DTCO), and an extended capability on top of the de facto golden-standard SPICE modeling platform, BSIMProPlusTM.
  • NanoSpice XTM, the latest high-performance SPICE simulator addressing simulation capacity and accuracy challenges of big post-layout designs at advanced process nodes.
  • NanoSpice Pro XTM, the latest FastSPICE simulator with simulation performance and accuracy needs tailored for SRAM, DRAM, Flash and big analog-on-top designs in high-performance computing, mobile, AI and other advanced applications.
  • NanoCellTM, the latest standard cell library characterization solution employs advanced distributed parallel architecture technology and cell circuit analysis extraction algorithms, embedded with a high-precision SPICE simulator.
  • ESDi, state-of-the-art HBM analysis, simulation and verification tool for on-chip ESD protection.

Chip companies worldwide rely on Primarius’ product portfolio as the continuous iteration of IC industry technology and complexity of IC manufacturing processes rise exponentially and challenges in designing and manufacturing high-end chips increase. Foundries and IDMs use Primarius tools and services to provide their design customers with more accurate SPICE models, completer and more reliable PDKs, and more comprehensive standard cell library within shorter development cycles. Chip designers who require stronger COT capabilities with customized devices and models, and re-characterized cell libraries based on actual applications benefit as well from Primarius’ products.

Primarius’ product portfolio is data-driven, achieving software and hardware synergy through leading semiconductor characteristic testing instruments and EDA products. It provides device testing systems for a full range of device characteristics such as IV, CV, reliability, statistical variation, and the industry-golden low frequency noise testing systems, 9812 series, used by semiconductor companies worldwide. Its latest release, 9812AC, is the only commercial low-frequency noise system under AC excitation, designed for the most advanced process development and chip designs.

Primarius provides complete EDA toolchain and a one-stop design enablement technical development solutions. Innovations like these can shorten the SPICE model development cycle from several months to a few weeks or even hours for quick iteration, addressing the efficiency bottleneck of DTCO. The advanced simulation technologies speed-up challenging circuit simulation, and the latest cell library characterization solution provides throughput with near-linear scaling on thousands of x86 or ARM CPU cores on computer farm or public cloud.

It enables faster turnaround from technology development to advanced chip designs, and solutions include advanced analysis capabilities for high-sigma yield, aging, EM/IR, ESD and signal integrity, targeting optimum yield and PPA.

Primarius Technologies will be in DAC booth #1415.

To arrange a meeting or demonstration of the Primarius Technologies product portfolio, send email to: contact@primarius-tech.com.


Agnisys at the 2024 Design Automation Conference

Agnisys at the 2024 Design Automation Conference
by Daniel Nenni on 06-19-2024 at 8:00 am

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Agnisys Inc. a leader in design and verification automation for hardware development, is gearing up for an impactful presence at DAC 2024. This year’s participation will be marked by various activities designed to engage and inspire the electronic design automation (EDA) community. Attendees can look forward to our Exhibitor Forum presentation, an exciting design contest featuring our IDS-NG tool, and our sponsorship of the ‘I LOVE DAC‘. Join us for live demonstrations, interactive sessions, and hands-on experiences that underscore our commitment to innovation in design automation.

I LOVE DAC PROMOTION
We are proud to sponsor ‘I LOVE DAC‘ at this year’s DAC event. As part of our sponsorship, we are thrilled to offer 44 promo codes for access to premium Engineering Tracks at the conference. This exclusive access includes Keynotes, SKYTalks & TechTalks, Engineering Track Presentations, Engineering Track Posters, the DAC Pavilion and Exhibitor Forum, Exhibits, Tuesday Career Development Day, Hands-On Training, and DAC Networking Events. This is a limited-time offer, so take advantage of this opportunity to be at the forefront of engineering innovation. To secure one of these promo codes, then fill out the form on the Agnisys website, these codes are available on a first-come, first-served basis. Register Today!

AGNISYS DESIGN CONTEST
One of the highlights at the Agnisys booth this year is the Agnisys Design Contest, showcasing our powerful IDS-NG tool. IDS-NG is renowned for its ability to streamline digital design, eliminating the need for manual verification, validation, and integration. Participants will have the opportunity to attend a short demo of IDS-NG, demonstrating its capabilities in creating digital designs rapidly and efficiently. Following the demo, participants can test their skills by using IDS-NG to create their digital designs in a fun and competitive environment.

Participants will see how IDS-NG accelerates the design process, allowing them to create functional designs without the traditional hurdles of verification, validation, and debugging. Every participant will receive a gift, and the day will culminate in a raffle draw at 5:00 PM, offering further chances to win attractive prizes.

EXHIBITOR FORUM
At the exhibitor forum we’ll be presenting on the topic of “Object-Oriented Embedded Hardware for Operational Excellence”, Object-oriented software has made its mark in the industry. It has helped create large software systems. Coming from the Software industry it has been adopted by hardware verification in the form of languages like SystemVerilog and SystemC and methodologies like UVM. But what about embedded hardware?

This presentation will discuss how embedded hardware can be presented in an object-oriented way to firmware and lower levels of system software. We will review the industry standards and non-standard formats that are currently prevalent in this space.

Date: Wednesday 26, 2024
Time: 11:15AM – 11:45AM PDT
Location: Exhibitor Forum, Level 1 Exhibit Hall
Duration: 30 mins

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Weebit Nano at the 2024 Design Automation Conference

Weebit Nano at the 2024 Design Automation Conference
by Daniel Nenni on 06-19-2024 at 6:00 am

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Innovative Memory Architectures for AI – Don’t Miss this DAC Session!

We all know that the proliferation of AI applications is happening at an unprecedented rate while at the same time, memories aren’t scaling along with logic. This is one of many reasons that the industry is exploring new memory technologies and architectures.

When it comes to embedded non-volatile memory (NVM), the incumbent technology, flash, has reached its limits in terms of power consumption, speed, endurance and cost. It is also not scalable below 28nm, so it’s not possible to integrate flash and an AI inference engine together in a single SoC at 28nm and below for edge AI applications.

Embedded ReRAM is the logical alternative. Embedding ReRAM into an AI SoC would replace off-chip flash devices, and it can also be used to replace the large on-chip SRAM to store the AI weights and CPU firmware. Because the technology is non-volatile, there is no need to wait at boot time to load the AI model from external NVM.

ReRAM is also much denser than SRAM which makes it less expensive than SRAM per bit, so more memory can be integrated on-chip to support larger neural networks for the same die size and cost. While on-chip SRAM will still be needed for data storage, the array will be smaller and the total solution more cost-effective. With ReRAM, designers can have a single chip implementation of advanced AI in a single IC while saving die size and cost.

ReRAM will also be a building block for the future of edge AI: neuromorphic computing. In this paradigm, also called in-memory analog processing, compute resources and memory reside in the same location, so there is no need to ever move the weights. The neural network matrices become arrays of ReRAM cells, and the synaptic weights become the conductance of the NVM cells that drive the multiply operations.

Because ReRAM cells have physical and functional similarities to the synapses in the human brain, it will be possible to emulate the behavior of the human brain with ReRAM for fast real-time processing on massive amounts of data. Such a solution will be orders of magnitude more power-efficient than today’s neural network simulations on traditional processors.

At the Design Automation Conference (DAC) 2024, Gideon Intrater from Weebit Nano will go in depth on this topic during his presentation, ‘ReRAM: Enabling New Low-power AI Architectures in Advanced Nodes.’

Gideon’s presentation will be part of the session, ‘Cherished Memories: Exploring the Power of Innovative Memory Architectures for AI Applications,’ which will explore cutting-edge technologies transforming the landscape of memory design. Organized by Moshe Zalcberg of Veriest Solutions and moderated by Raul Camposano of Silicon Catalyst, other presenters include experts from RAAM Technologies and Veevx Inc.

Don’t miss this DAC session!

  • Cherished Memories: Exploring the Power of Innovative Memory Architectures for AI Applications
  • Time: 10:30 AM – 12:00 PM
  • Location: IP Room: 2012, 2nd Floor
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OPENEDGES Technology at the 2024 Design Automation Conference

OPENEDGES Technology at the 2024 Design Automation Conference
by Daniel Nenni on 06-18-2024 at 8:00 pm

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A leading memory subsystem IP provider, OPENEDGES Technology  (OPENEDGES) is set to unveil the 2.0 release of PHY Vision at the Design Automation Conference (DAC) 2024. The event will take place at the Moscone Center West, San Francisco, from June 24th to 26th, where attendees can experience firsthand the enhanced capabilities of this advanced LPDDR PHY visualization and exploration software.

PHY Vision 2.0 is a Graphical User Interface (GUI) software that allows users to configure, control, and visualize the behavior of OPENEDGES’ LPDDR PHY IPs in different operating conditions and applying analog tuning settings. Since its initial debut at last year’s DAC, PHY Vision has been upgraded with improvements in architecture, performance, and portability. The live demonstration will feature OPENEDGES’ 7nm LPDDR5X combo PHY IP and test platform, operating at a data rate of 8533 Mbps.

At OPENEDGES’ booth 2432, visitors can view a live demo of PHY Vision 2.0 and explore the many features and benefits of OPENEDGES’ LPDDR PHY IP, which include:

  • Advanced protocol availability for mature technology nodes
  • Cross-verification with OPENEDGES’ ORBIT Memory Controller (OMC)
  • Reduced silicon footprint and area requirements
  • Accelerated training time with support for firmware customization
  • Fast frequency set point (FSP) switching
  • Optimized low power states
  • Simplified integration of HARD and SOFT IP and more.

Visitors to the Moscone Center West can also learn more about OPENEDGES’ most recent PHY achievement, the successful silicon bring-up of its LPDDR5X PHY IP on 5nm process technology.

OPENEDGES’ wholly owned subsidiary, The Six Semiconductor (TSS), which specializes in developing high-speed DDR PHY IP, will also be present at the booth. TSS engineers will engage with visitors to share their insights and expertise in memory sub-system planning and implementation for low-power systems.

OPENEDGES is a total memory subsystem IP provider offering DDR memory controller, DDR PHY, On-chip Interconnect, and NPU IPs, compatible with the latest DDR technology trends. Contact OPENEDGES here to schedule a meeting at booth #2432.

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Agnisys at the 2024 Design Automation Conference

Weebit Nano at the 2024 Design Automation Conference


Perforce at the 2024 Design Automation Conference

Perforce at the 2024 Design Automation Conference
by Daniel Nenni on 06-18-2024 at 6:00 pm

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Perforce powers innovation at unrivaled scale. Perforce solutions future-proof competitive advantage by driving quality, security, compliance, collaboration, and speed – across the technology lifecycle. We bring deep domain and vertical expertise to every customer, so nothing stands in the way of success. Our global footprint spans more than 80 countries and includes over 75% of the Fortune 100. Perforce is trusted by the world’s leading brands to deliver solutions to even the toughest challenges. Accelerate technology delivery, with no shortcuts. Get the Power of Perforce.

Visit Perforce At Booth #1421 in the Exhibit Hall

Visit the Perforce booth, #1421 in the Exhibit Hall, to get a demo of our latest enhancements and chat with our experts about how Perforce semiconductor solutions can help solve your biggest chip design challenges. While you’re there, play PLINKO and win some fresh Perforce swag. Plus, scan your badge for a chance to win a TheraGun.

Stop By For Happy Hour

On Tuesday, June 25, we’ll be hosting a happy hour at Perforce booth #1421 from 3 to 5 p.m. Stop by with questions, network, and enjoy some drinks on Perforce.

Don’t Miss This Presentation

Perforce VP of Solutions Engineering, Vishal Moondhra, will be presenting on “The Transformation Model for IP-Centric Design: A Blueprint for Improving IP Reuse, End-To-End Traceability, and Collaboration at Enterprise Scale.”

Attend this session to learn how transitioning to an IP-centric design methodology allows organizations to achieve the goal of a streamlined, fully traceable, horizontally scaling, single source of truth for all design management needs across hardware, firmware, and software projects and platforms. The benefits include improved collaboration, accelerated design, more informed build vs. buy decisions, and a streamlining of efforts across design teams.

This session will be held on Tuesday, June 25 at 11:15–11:45 a.m at the Exhibitor Forum Stage.

Skip the Line – Schedule a Meeting

Want to learn more about Perforce solutions for IP and design data management? DAC attendees can skip the line and schedule a meeting or demo with Perforce staff on their website here: Book a Meeting

Meeting times are available Monday, June 24 through Wednesday, June 26 at our booth.

Find More Resources

Visit our DAC event page for information about Perforce at DAC. Learn why 9 of the 10 top semiconductor companies use Perforce. Plus, find more semiconductor and SoC resources, including information on Perforce solutions, whitepapers on IP-Centric Design and supercharging embedded development with modern data management, and more: Perforce at DAC.

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Applied Materials at the 2024 Design Automation Conference

Applied Materials at the 2024 Design Automation Conference
by Daniel Nenni on 06-18-2024 at 4:00 pm

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What is Applied Materials doing in an EDA trade show?
New semiconductor market segments such as AI, automotive and connected devices are growing at an accelerated pace and placing constant increased pressures on the PPAC (power, performance, area, cost) system requirements. In the past, these growing PPAC demands were addressed by scaling down feature geometries and cost per transistor at a predictable pace, known as Moore’s law. But in recent years, geometry scaling has slowed down around 7nm technology geometry to a point that it cannot keep up with the pace of growing PPAC demands, requiring new approaches and innovations.

Today’s technologies are already at atomic levels and there is no single technology breakthrough we can rely on. We need to explore multiple innovative solutions across the entire semiconductor technology chain and holistically evaluate from the system level, chip design architecture, IP design and circuit design, devices, and interconnect to the fabrication processes and materials that this entire chain is founded upon.

PPAC à PPACt

Applied Materials has already identified these challenges a few years ago and has implemented a corporate-wide effort to address them in an integrative manner that explores potential innovative solutions at different levels. Solutions include new material innovations, processing techniques, new device structures, power delivery schemes, interconnect structures, circuit, foundation IP, chip design, and packaging, all the way to the system level. Multiple combinations of these innovations can be modeled and evaluated at each level. Applied’s goal in this effort is to find and develop new solutions with optimized PPAC for each market segment or application. Furthermore, Applied recognizes the importance of bringing these solutions to the market quickly and added a time-to-market dimension changing PPAC to PPACt.

System To Materials (STM) Group

The STM group at Applied is an essential part of this corporate-wide effort. STM has developed technologies and methodologies to identify system level challenges and bottlenecks through innovative solutions at all levels of the value chain. These innovations are accurately modeled through a complete design flow from materials to system level.

STM DAC Exhibit

STM engagements with the design and EDA community are important to understand and address the current industry challenges. At 2024 DAC, learn about the following products and services that are commercially offered by STM at exhibit booth #1522 (under “Sage Design Automation” which is a part of the STM group).

SLiCTM:  Standardcell Library Compiler

SLiC generates the highest quality standard cells at a fraction of time and effort compared to traditional methods. SLiC’s technology flexibility and quick setup time can accelerate DTCO pathfinding effort from months to weeks.  SLiC high throughput and optimized results enable generation of a complete production level logic library overnight. SLiC supports state of the art technologies from 7nm to 1.4nm, including CFET stacked devices.

iDRMTM:  integrated Design Rule Management system

iDRM is a tool to develop, manage and enable correct-by-construction design rule development with clear rule description and automate creation of error-free DRC decks for third party DRC tools. iDRM’s powerful GUI helps to view and edit design rules, as well as check and verify design rule intent.

DRVerifyTM:  DRC Deck QA and Verification

DRVerify checks and verifies DRC decks to make sure they are complete, correct and error-free. DRVerify automatically creates pass/fail test cases from design rule descriptions, runs the tested DRC deck on these test cases, scans DRC markers, compares to the golden rule intent and highlights any possible errors or mismatch.

Ginestra®: Materials-to-Device Optimizer

Ginestra is a material centric simulation platform which links process material properties (composition, stoichiometry, atomic-defects) to device performances and reliability.  Ginestra integrates relevant physics critical to understanding and managing the complexity of materials-to-device co-optimization from materials discovery through device performance, reliability and variability projection. Ginestra’s design and simulation platform accelerates materials-to-device innovation, providing atomic level insights to improve performance, power, area, cost and time to market.

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Ansys and NVIDIA Collaboration Will Be On Display at DAC 2024

Ansys and NVIDIA Collaboration Will Be On Display at DAC 2024
by Daniel Nenni on 06-18-2024 at 2:00 pm

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Highlights:

In less than two weeks the 2024 Design Automation Conference and Exhibit will start on June 23rd  in San Francisco. Ansys will be showcasing its 3DIC Multiphysics solutions together with NVIDIA in the Ansys booth where Ansys solutions will be shown running natively on NVIDIA GPU hardware.

More collaboration with NVIDIA will be on show at the DAC Exhibitor Forum sessions sponsored by Ansys every day from 1:45pm – 3:00pm:

One of the most difficult challenges for IC designers today is power integrity signoff at advanced nodes and how to achieve comprehensive dynamic voltage drop (DVD) coverage. Attend this session to learn how leading IC design teams no longer rely only on traditional vectored/vectorless analysis but are adopting a radical new SigmaDVD™ technology from Ansys to address urgent DVD issues at advanced nodes . SigmaDVD is becoming the leading method for avoiding DVD voltage and timing problems, shift-left prevention of voltage-drop issues, fixing IR violations, and achieving robust, high-coverage power integrity signoff.

AI/ML is causing sweeping changes in almost every industry, and electronic design and simulation are no exceptions. EDA tools have a long history of using heuristics and numerical approximations to ensure designer productivity keeps pace with Moore’s Law. This session will feature Ansys CTO Prith Banerjee joined by industry speakers to discuss today’s practical application of AI/ML for electronic design and simulation, and how this trend will determine the direction of EDA in the future.

Ansys and NVIDIA collaborate closely to enable designers to bring a new paradigm to IC design: Visualizing and optimizing multi-die designs with NVIDIA’s  Omniverse technology. In combination with Ansys electromagnetic, thermal, and mechanical simulation it can provide capabilities never before seen in IC design. This session features representatives from Ansys and NVIDIA demonstrating Ansys solutions operating with NVIDIA’s Omniverse for practical optimization solutions. The session will also cover key aspects of the companies’ collaborations on AI and GPU design and enablement, as debuted in Jensen Huang’s GTC 2024 keynote.

Ansys’ chief technology officer, Prith Banerjee, will be sharing his insights with the DAC Research panel “Why Is EDA Playing Catchup to Disruptive Technologies Like AI?” on Wednesday at 11:30am.

The Ansys 40×40 booth (#1308) is one of the larger ones in this year’s Exhibit, with its major theme of 3DIC Multiphysics simulation and signoff. NVIDIA will be participating in the Ansys booth with a demonstration of its GPU hardware running Ansys simulations solutions. Customers can also register to attend a series of 6 technical Customer Workshops in the Ansys booth where Ansys customers present detailed technical summaries of their experiences and successes in applying Ansys technology for their production IC designs.

Ansys will be presenting in the Intel Foundry booth on support for Intel 18A and advanced backside power delivery technology. Ansys will also present in the Microsoft booth on the cloud-enablement collaboration with Azure to optimize compute times and costs for designing large AI/ML, HPC, networking , and automotive designs.

The impressively broad usage of Ansys products across the semiconductor industry has once again enabled Ansys customers to submit an equally impressive 24 technical papers that have been accepted by the DAC Conference and will be presented in the Engineering Track.

So please make sure to register to attend the conference and join Ansys at DAC. Register for one of our exclusive events or schedule a meeting as we reach out to our customers and partners in advancing the state-of-the-art in Electronic Design Automation.

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IC Manage at the 2024 Design Automation Conference

IC Manage at the 2024 Design Automation Conference
by Daniel Nenni on 06-18-2024 at 12:00 pm

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DAC in San Francisco will once again be a can’t miss event for semiconductor professionals seeking to discover the latest developments in EDA solutions that address the wide range of issues encountered in delivering high quality IC products and electronics systems to the market. IC Manage will be exhibiting its latest innovations from its Global Design Platform, IP Central and Holodeck products that address the growing complexities of design management and data explosion that come along with advanced technology nodes that are enabling today’s cutting edge designs in AI, SoC and high performance analog products.

In the realm of design data management, the IC Manage applications team will be showing the latest GDP-XL features that deliver high performance configuration and release management that scale to 1000s of users managing and tracking millions of IP components and design variations. Other new developments extend customization features that enable customers to adapt to new workflows and usage models without complex programming or major software upgrades. Additionally, the new Time machine feature allows full traceability of design and configuration changes as well as comparison of any 2 design states & recovery of previous design states.

GDP-XL support for Git based version control has also been extended and IC Manage will be demonstrating integration with popular Git environments like Gitlab and how to reliably manage 1000’s of Git repos and release states in building complex SoCs.

IP Central has also evolved and the IC Manage team will be showing how to capture IP components and manage their lifecycle along with the customization features that enable user-configurable search pages and automatically generated and searchable IP datasheets. Integration methods with external systems like Jira for bug tracking will also be covered that are essential in delivering a full IP Asset management environment that allows data sharing across any number of enterprise reporting systems.

Helping IC design teams to leverage Cloud computing or to accelerate their internal data center performance, the Holodeck team will be showing “how to” demos of instant cloud bursting of popular EDA tools like Ansys Redhawk, Verilog simulation, Cadence Virtuoso and Siemens EDA Calibre. Holodeck’s key benefits for EDA tool performance acceleration and storage cost reduction results will also be discussed. Holodeck can deliver elastic computing which requires a a true scaleout storage I/O architecture to be able to deliver high I/O performance across 1000s of compute nodes without having to pre-copy data to the cloud or remote data centers.

For more information, please visit https://www.icmanage.com or to sign up for a DAC demo session please click HERE.

About IC Manage
IC Manage provides hybrid cloud and high-performance design management solutions for companies to efficiently collaborate on design and verification across their global enterprises, while maximizing their IP reuse. IC Manage customers include AMD, Infineon, Microchip, Qualcomm, NVIDIA, Samsung and other top semiconductor and systems companies. IC Manage is based in Campbell, CA, with additional offices throughout the U.S., Asia, and Europe. For more information visit us at www.icmanage.com.

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Mirabilis Design at the 2024 Design Automation Conference

Mirabilis Design at the 2024 Design Automation Conference
by Deepak Shankar on 06-18-2024 at 10:00 am

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This is the first time in 28 years of my visits to DAC that I have seen so many different technologies arrive at DAC in the same year.  Earlier we would have one or possibly two innovative breakthroughs in semiconductors and embedded systems that emerged at DAC. This year I expect six or may be seven to arrive, and I am not including the innovations in EDA software.

At the system-level, new architectures are propelling the need for a shift-left methodology that integrates system-level analysis and exploration, architecture trade-offs, communication with partners and requirements monitoring. Trending technologies include multi-die and Chiplets, RISC-V and ARM co-habiting, power and thermal challenges leading to more complex power management architectures, AI engines vs. GPU for vector and convolution, common architecture for all EV automobiles, micro-assurance experiments, and latency analysis of analog systems.

In the post-Covid era, Mirabilis Design has recognized the emergence of these trends.  To support these trends, we have introduced the concept of validated system-level IP and capabilities on top of performance models.  System-level IP blocks to support Chiplets/UCIe, PCIe6.0, LPDDR_5X, DDR5, DSP, GPU, AI Engines, NoCs, and DSP have been added to the flagship VisualSim Architect. Requirements can be imported from a variety of database and is fully integrated with the simulator, that provides continuous monitoring.  Other new features include thermal characteristics from the power modeling of a cycle-accurate performance model, AI workloads such as DNN partitioning on to AI/GPU/CPU, failures modeling and generation of UPF/UVM/SystemVerilog files for early verification.

We are witnessing a spurt in interest by semiconductor and automotive design communities in exploring the revamped version of VisualSim.  We strongly believe this trend will expand further as more and more designs require AI engines and devices becoming power hungry leading to an increase in thermal cost.

Chiplets have been recognized as the right choice of solution as a rapid response to new customer requirements.  Building a stock/base of different configurations that can be easily assembled for a new application is essential.  The VisualSim model of the application architecture enables a new market for chiplet IP vendors and semiconductor companies. Both can collaborate to create a solution that is optimized for the target application and workload to meet the Power-Performance-Area.  VisualSim hardware builders have been proven to create a new generation of SoC in about 2 weeks, thus enabling rapid trade-off, and dynamic documentation for distribution to OEMs and suppliers.

Power has become extremely important in both traditional processors and emerging applications such as AI, GPU, automotive architecture.  VisualSim Power Digital Twin has been built on top of the VisualSim performance model.  The design can incorporate power management, large number of states, dynamic and leakage, distribution and attenuation, negative impact of power management, batteries, and power generators such as solar panels. The models provides instantaneous and average power plots, power improvement for a new power management architecture, output thermal characteristics for temperature and heat, power for workloads and individual IP and generate SystemVerilog test benches and UPF files.

Inspite of the fact that the large vendors of the EDA industry are missing, I believe it will still be an important one for both the electronics engineers and the EDA companies supporting them.

Website: https://www.mirabilisdesign.com

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