SNPS1670747138 DAC 2025 800x100px HRes
Semiconductor Expert Forum

Posted on

A Master Class with Ansys and Synopsys, The Latest Advances in Multi-Die Design

A Master Class with Ansys and Synopsys, The Latest Advances in Multi-Die Design
by Mike Gianfagna on 12-04-2024 at 6:00 am
Categories: 3D IC, Ansys, Inc., EDA, Synopsys
1 Comment

A Master Class with Ansys and Synopsys, The Latest Advances in Multi Die Design

2.5D and 3D multi-die design is rapidly moving into the mainstream for many applications. HPC, GPU, mobile, and AI/ML are application areas that have seen real benefits. The concept of “mix/match” for chips and chiplets to form a complex system sounds deceptively simple. In fact, the implementation and analysis techniques required to achieve success are substantial.

For many years, Synopsys and Ansys have been creating design flows that escort design teams through early exploration, implementation, and final signoff. The two companies are deeply engaged with many customers on advanced multi-die projects and have helped bring many successful designs to market. Synopsys and Ansys recently teamed up to present a webinar on the latest technology for multi-die design. The result is nothing short of a master class. Let’s explore the latest advances in multi-die design.

The Presenters

The effectiveness of a webinar is heavily influenced by the capabilities of the presenters. A slick polished and shallow presentation may entertain you, but you won’t learn much. A very detailed, but scattered presentation may deliver a lot of information but it’s often hard to find it amidst the noise. The presenters for this webinar delivered a perfect blend of professional polish and deep technical knowledge. The event runs for 45 minutes, but it will seem more like 20 minutes given how engaging both speakers are. The presenters for this webinar are:

Marc Swinnen

Marc Swinnen, Product Marketing Director for semiconductor products at Ansys. Before joining Ansys, Marc was Director of Product Marketing at Cadence Design Systems and has worked in Marketing and Technical Support positions at Synopsys, Azuro, and Sequence Design, where he gained experience with a wide array of digital and analog design tools.

 

 

 

Keith Lanier

Keith Lanier, Product Management Director at Synopsys. Keith focuses on multi-die and 3D heterogeneous integration (3DHI) solutions involving the latest advanced packaging technology. He brings over 30 years of experience in custom design, analog/mixed signal (AMS) and RF/mmWave product experience, including 8 years designing high speed data converters and amplifiers at Analog Devices.

A link to the webinar replay is coming. I highly recommend you watch it if 2.5/3D is in your future. First, let’s look at the structure of the webinar and a few key takeaways.

The Topics Covered

Here is the agenda for the webinar:

  • Multi-Die Design Motivation, Adoption, and Challenges
  • Combined Synopsys-Ansys Solutions for Implementation and System Analysis
  • Multi-Die Design Implementation
  • System Analysis
    • Power Integrity: Electromigration / IR Drop
    • Thermal integrity: Multi-Die Design
    • Signal Integrity: High Frequency Electromagnetic Analysis
  • Golden Sign-off Analysis
  • Customer Successes
  • Summary

This is a lot to cover, but Marc and Keith do a great job covering it all in under 30 minutes. What follows is about 15 minutes of Q&A from the webinar audience. The questions are deep and insightful, and the responses are concise and on-point. You will learn a lot.

Some Takeaways

Some macro-trend motivations for multi-die design are worth repeating. Here are the ones mentioned in the webinar:

  • Accelerated scaling of system functionality at a cost-effective price (>2X reticle limits)
  • Reduced risk & time-to-market by re-using proven designs/die
  • Lower system power while increasing throughput (up to 30%)
  • Rapid creation of new product variants for flexible portfolio management

The size, projected growth and application footprint for this design style are also covered. The numbers and scope will surprise you. Some recent examples of completed multi-die designs were covered. Some of these details surprised me. Below are the results presented during the webinar.

Examples of Recent Commercial Multi Die Designs

What followed was a deep dive into the combined Synopsys-Ansys implementation, analysis and optimization techniques used by both companies to deliver a production, unified flow. A lot of the webinar goes into the details of the complete exploration to signoff flow for multi-die designs, how to use the flow with the multi-physics models and how the tools work together. Case studies are also provided to show application on real designs. Below is a high-level overview of what was covered.

Combined Synopsys Ansys Implementation, Analysis and Optimization Techniques

Real customer success stories are then presented. This really crystallized for me how advanced this flow is and what kind of impact is being achieved. You need to see the results for yourself, but here are the projects covered:

  • Sanechips Builds Comprehensive Ansys Thermal Signoff Flow for Multi-Die Design
  • GUC Leverages Synopsys 3DIC Compiler to Enable 2.5D/3D Multi-Die Designs

To Learn More

What I’ve covered here is a very small subset of the content of this important webinar. As I mentioned, if 2.5/3D design is in your future it’s a must-see event. You can access the webinar replay here. And that’s a master class with Ansys and Synopsys to explore the latest advances in multi-die design.

Posted on

SystemC Update 2024

SystemC Update 2024
by Daniel Payne on 12-03-2024 at 10:00 am
Categories: Accellera, Semiconductor Services

SystemC ecosystem min

SystemC version 1.0 came out in 2000 as a C++ class library for system-level modeling and simulation, and on SemiWiki.com there are some 497 references to the language. I wanted to provide an update in this blog so that engineering teams can become more efficient in using SystemC on their SoC projects, saving time and improving product quality.

SystemC Evolution Day

This one day workshop was co-located with DVCon Europe on October 17th in Munich and had participants from the user community, EDA vendors, and Accellera Working Groups. The keynote from Alex Bennee, Linaro, talked about synergies between QEMU – an open-source machine emulator for running OS and apps for a guest on a host, and SystemC. With co-simulation both software and hardware components can be simulated together.

A panel discussed what SystemC 4.0 should do to widen the simulation community and what the standardization cycle looks like, with panelists from Qualcomm, Infineon, Arteris, MachineWare and Robert Bosch.

The five working groups presented updates:

  • Language – SystemC 3.0.1 update published
  • AMS – LRM for IEEE 1666.1 update started, call to participate in P1666.1
  • CCI (Configuration, Control & Inspection) – latest developments, established regression/CI flow in GitHub
  • Verification – UVM-SystemC library 1.0beta6 released July 2024
  • Synthesis – restarted in early 2024,  plans and development from Fika in May

SystemC ecosystem

Engineers from Intel and MachineWare did a CCI update for an Inspection Proposal in draft form, plus a live demo.

GUI for controlling, inspecting simulation

Chapman University presented on using SystemC TLM 2.0 for loosely-timed contention-aware modeling, looking at trade-offs between simulation speed and timing accuracy. The final hour was an open room discussion about having SystemC multi-kernel support and thread safety, with presenters from MachineWare and COSEDA.

SystemC Fikas

Two to three times per year there are free, virtual workshops, called Fikas – in the Swedish tradition of sharing a coffee and talking with community.  The most recent Fika was May 30th, where three of the working groups presented updates: Language, CCI, Synthesis. You can view the latest presentations and watch the recording online.

SystemC 3.0.1

The latest release of the SystemC Class Library, SystemC 3.0.1, represents a significant step forward in aligning with the IEEE 1666-2023 Language Reference Manual. This update introduces a variety of enhancements, bug fixes, and expanded platform support.

Key bug fixes and improvements include:

  • Alignment with IEEE 1666-2023:
    • Completed the remaining changes to match sc_bind with the revised IEEE 1666-2023 definition
    • Updated the implementation of reset event notification in sc_process_b::trigger_reset_event to comply with IEEE 1666-2023
  • Performance Enhancements:
    • Refactored integer tracing and file writing for improved performance.
    • Enhanced the non-regression test suite
  • Compiler and Build Improvements:
    • Cleaned up various compiler warnings and improved support for sanitizers
    • Addressed issues in autotools and enhanced CMake build flows
    • Updated the list of supported operating systems and compilers
    • Removed configurations that are no longer supported from build flows
  • Datatype Management:
    • Fixed various issues in datatype management, resulting in better performance

These updates ensure that SystemC 3.0.1 is more robust, efficient, and compliant with the latest standards, providing a better experience for developers and users alike.

SystemC Synthesis

At DVCon US 2024 the Synthesis Working Group leaders asked for your participation to further high-level synthesis, and high level verification.

Synthesis Working Group

The Synthesis Working Group has all their status online, and invite you to join their group.

SystemC Community Portal

The best place to visit on the web for all things SystemC is https://systemc.org/ , where each working group keeps you up to date, the annual SystemC Evolution Day presentations and Fikas are archived, plus there are publications, libraries and projects for you to be part of the community.

Summary

In the past 24 years the SystemC language has grown in scope and acceptance for system-level modeling, so that engineering teams can design and verify both hardware and software components together at a higher level of abstraction than RTL. SystemC is also useful as a verification framework and even mixed-signal modeling. Follow up by clicking the links to get more details and improve your engineering skillset.

View presentations from the SystemC Evolution Day online.

Related Blogs

Posted on

Innexis Product Suite: Driving Shift Left in IC Design and Systems Development

Innexis Product Suite: Driving Shift Left in IC Design and Systems Development
by Kalar Rajendiran on 12-03-2024 at 6:00 am
Categories: EDA, Emulation, Siemens EDA

Full Spectrum Development Inexis Developer Pro

At the heart of the shift-left strategy is the goal of moving traditionally late-stage tasks—such as software development, validation, and optimization—earlier in the design process. This proactive approach allows teams to identify and resolve issues before they escalate, reducing costly rework and shortening the overall development timeline. As IC designs become more complex and software demands increase, shifting left becomes critical. Early defect detection, quicker iterations, and the ability to validate performance and power early in the design process help prevent delays and reduce costs. Ultimately, this approach ensures a higher quality product, faster time-to-market, and a more efficient development cycle.

Siemens EDA recently launched its Innexis Product Suite, a comprehensive set of tools designed to reshape the development and validation of integrated circuits (ICs) and complex systems. Building on the success of its Veloce™ hardware-assisted verification and validation system, the Innexis product suite is engineered to support shift-left software development. And its integration with Veloce ensures that both hardware and software are validated in parallel throughout the development cycle. By enabling early software testing, continuous validation, and rapid debugging across virtual and hardware environments, Innexis complements Veloce to optimize the entire verification process.

The following insights were gained from the various talks at the Innexis Product launch event.

The Innexis Product Suite

The product suite is specifically built to enable this shift-left methodology across various stages of the design process. The suite includes several components, each offering unique capabilities and use cases but all aligned with the goal of accelerating development and enabling early validation of both hardware and software.

Innexis Developer Pro

The Innexis Developer Pro plays a pivotal role in supporting the continuous development flow from virtual models to hybrid systems and eventually to full RTL simulations. This tool offers a seamless platform for hardware-software co-development, validation, and analysis. Developers can work across virtual, hybrid, and RTL environments, ensuring that designs are continuously tested and optimized from the very start. By enabling early power and performance analysis, Innexis Developer Pro helps teams identify issues early in the cycle, preventing rework later on. It supports a wide range of use cases, such as enabling pre-silicon validation and accelerating the creation of complex SoCs with heterogeneous cores.

Samsung shared with the audience, how the Innexis suite has accelerated their software development by providing a configurable reference platform that mimics a Samsung A75-based CPU subsystem and integrates Samsung GPU IP. With the Innexis stack, Android boots in under 10 minutes, compared to 20+ hours on traditional emulators, and Veloce Strato enables faster pre-silicon performance analysis by executing GPU RTL. Samsung’s successful shift-left with Innexis has streamlined their development process, enabling software development as early as the first RTL milestone, with RTL to Innexis readiness in just one week, pre-verified software stacks, and a configurable testbench for efficient custom driver integration and testing.

Innexis Architecture Native Acceleration (ANA)

For teams looking to develop software early in the process, Innexis ANA provides a high-speed, cloud-based platform. By utilizing Arm-based servers, ANA enables the execution of software workloads at speeds up to 2-4 GHz, significantly faster than traditional simulation-based platforms. The cloud-native environment offers scalable resources and enables team collaboration by allowing the sharing of models and workloads across different locations. With Innexis ANA, engineers can develop and test software long before RTL or silicon are available, optimizing performance and identifying software defects early. It also integrates seamlessly with other parts of the suite, enhancing the shift-left workflow and ensuring continuous development without delays.

Arm shared with the audience, Innexis ANA benchmark numbers that demonstrate 50-100X boot time performance improvement when using realistic software workloads compared to a QEMU-based Instruction Set Simulator (ISS) virtual platform.

Innexis Virtual System Interconnect (VSI)

Another key component, Innexis VSI, facilitates the creation of system-level digital twins. This tool integrates multi-behavioral models of various subsystems, such as sensors, ECUs, and environmental models, to simulate the interactions within a complete system. By providing visualization and analysis capabilities, VSI helps engineers understand system behavior before physical prototypes are available. It is especially useful in industries like automotive, where system-level validation is critical for complex designs such as autonomous driving systems or electric powertrains. VSI can also be cloud-enabled, offering scalable simulations and real-time collaboration, which accelerates the design process and ensures all system components function together as intended.

Innexis Product Suite Benefits

The Innexis suite’s benefits are far-reaching. First, it helps accelerate time-to-market by enabling earlier testing and identification of defects, thus reducing design iterations and re-spins. Second, it offers cost savings by allowing issues to be addressed early, preventing expensive last-minute fixes. Third, it fosters collaboration by enabling teams to work seamlessly across geographic locations, sharing models, data, and workflows in real time. Finally, Innexis contributes to performance optimization by providing tools to run realistic software workloads early, ensuring that power and performance benchmarks are met before hardware is finalized.

Shifting Left Using AWS

The shift-left approach using Software and Digital Twin through virtual Hardware in Loop (vHIL) testing in the cloud accelerates the development cycle by enabling silicon virtualization before target hardware is available.

AWS highlighted to the audience, how Arm’s validated IP subsystems and AWS’s scalable cloud infrastructure ensure that teams have access to high-performance, cloud-native tools, enabling them to scale their development efforts quickly and efficiently. With Innexis ANA offering cloud-based benchmarking and software profiling, these capabilities ensure that developers can test and validate their designs in real-world conditions long before physical hardware is available. By utilizing Arm64-based Graviton instances on AWS, native execution of embedded software offers performance and efficiency gains over traditional emulation, allowing early software development before silicon is available. This approach reduces reliance on upfront HIL testing, enables early issue discovery, and offers scalable cloud-based resources for improved software quality and faster development cycles.

Summary

The Innexis Product Suite represents a paradigm shift in IC and systems development. By enabling shift-left in hardware/software co-design, early defect detection, and comprehensive system-level validation, Innexis empowers engineers to meet the challenges of modern IC design and accelerate the development of complex systems. With its cloud-native capabilities, powerful simulation tools, and integration with Veloce, Innexis provides the tools necessary to deliver high-quality products faster, more cost-effectively, and with higher reliability.

To learn more, visit

The Innexis solution page.

Press announcement page.

Also Read:

Relationships with IP Vendors

Handling Objections in UVM Code

Next Generation of Systems Design at Siemens

Posted on

How Breker is Helping to Solve the RISC-V Certification Problem

How Breker is Helping to Solve the RISC-V Certification Problem
by Mike Gianfagna on 12-02-2024 at 10:00 am
Categories: Breker Verification Systems, EDA

How Breker is Helping to Solve the RISC V Certification Problem

RISC-V cores are popping up everywhere. The growth of this open instruction set architecture (ISA) was quite evident at the recent RISC-V summit. You can check out some of the RISC-V buzz on SemiWiki here. While all this is quite exciting and encouraging, there are hurdles to face before true prime-time, ubiquitous application of RISC-V processors are commonplace. A big one is certification. I’m not referring to verification of the design, but rather certification of the RISC-V ISA implementation. Does the processor reliably do what is expected across its broad range of applications? Can we trust these devices?

It turns out this is a large and complex problem. The graphic at the top of this post illustrates its breadth. Solving it is critical to allow broad deployment of the RISC-V architecture. I decided to poke around and see what was being done. Breker has “verification” in the company name, so it seemed that would be a good place to start. I contacted my good friend Dave Kelf and I wasn’t disappointed. There is a lot going on here and Breker is indeed in the middle of a lot of it. Let’s see how Breker is helping to solve the RISC-V certification problem.

The CEO Perspective

Dave Kelf

I’ve known Dave Kelf a long time. He is currently CEO of Breker Verification Systems. Dave explained there are a lot of RISC-V design efforts underway at large companies, startups and advanced research. These programs include open-source projects, commercial programs and universities. He told me Breker alone is being used in 15 RISC-V development programs underway at present.

Dave explained that in the processor world, there are devices from companies such as Arm, Intel and AMD that come with a certification from the vendor. These devices undergo extensive testing. This creates a level of “comfort” that the device will perform as advertised under all conditions. The tests done by these companies can take on the order of 1015 clock cycles to run. That is indeed a mind-boggling statistic.

Dave provided an overview of what is involved in certifying a processor architecture like RISC-V. He explained that it’s important to understand that this task is a lot more complex than certifying a point-to-point communication protocol (think Wi-Fi). It’s also a lot broader than verifying a specific processor design. Before the processor gets that golden stamp of approval, it needs to be checked for all potential use cases, not just the one being used on a particular design.

The architecture of the certification test suite needs to be developed and agreed to by a steering committee that has a sufficiently broad ecosystem perspective. Then the actual tests need to be built and verified. Then comes the task of running the certification suite. Do companies self-certify, or does an independent lab do that work? And finally, how is all this funded?

A complex and daunting set of problems to solve, but this kind of proof of capability is what will be needed to achieve mainstream use across a broad range of applications for RISC-V. The good news is that RISC-V International has taken up the cause. Dave explained that after the RISC-V Summit last year work began. So, this project is about 10 months old. Breker, along with many other members of the RISC-V community is providing support and effort to realize these important goals.

Dave explained that there was a presentation on this work at the recent RISC-V Summit. This presentation filled in a lot more details for me.

The President and CTO Perspective

Adnan Hamid

Adnan Hamid, Executive President and CTO at Breker gave the presentation on RISC-V certification. As mentioned, this effort started after last year’s RISC-V Summit. It is being driven at the RISC-V International Board level. A key part of the RISC-V organization is the technical steering committee (TSC). This is where all the details for components of the RISC-V ecosystem are developed, both hardware and software. A certification steering committee (CSC) has been created that exists at a peer level to the TSC.  One way to think about this is that the CSC has the mandate to check the TSC to ensure a coherent path to certification can be developed. The diagram below illustrates the entities involved in the program. The goal is to deliver holistic brand value.

Organizations Involved in Certification

Adnan shared some of the details of the program. Although it is still early days, these are likely to include:

  • Allows implementations to ensure compliance with RISC-V standards
  • Goal is to provide confidence to the RISC-V ecosystem that it will correctly operate on certified implementations
  • Certifies processors, SoC components, and platforms
  • Certifies RTL and silicon
  • Includes commercial-grade certification materials
  • Customers pay to obtain certificate
  • Fee based on certification cost
  • “RISC-V Compatible” Branding Program
  • Certificate must meet customer requirements
    • Must be available in a timely fashion
    • Must be based on ratified RVI standards

Certification is planned to be done in phases as shown below.

Certification Deployment Phases

The CSC is taking shape. It currently has the following five working groups:

Certification Working Groups

You can see a recording of the full presentation Adnan gave here.

Dave and Adnan are actively involved in the Customer Survey and Tests & Models groups. There are about 24 companies involved in this effort so far, and that number is growing.

How You Can Help

There is a lot being done on RISC-V certification. And a lot more to do as well. If you’re like most folks in semiconductors today, you are thinking seriously about how the open architecture of RISC-V could help. If you are interested in RISC-V, the certification team wants to hear from you. They need your input which will be used to shape this program. There is a survey underway to better understand your needs.

Let your voice be heard. You can access the survey here. Do it today! And that’s how Breker is helping to solve the RISC-V certification problem.

Also Read:

Breker Brings RISC-V Verification to the Next Level #61DAC

System VIPs are to PSS as Apps are to Formal

Breker Verification Systems at the 2024 Design Automation Conference

Posted on

CEO Interview: Ollie Jones of Sondrel

CEO Interview: Ollie Jones of Sondrel
by Daniel Nenni on 12-02-2024 at 6:00 am
Categories: CEO Interviews, Semiconductor Services, Sondrel

xr:d:DAFvo1pPrb0:9,j:897746449552040023,t:23092711

Sondrel has just appointed a new CEO, Ollie Jones, so we had a chat with him to find out his vision for the company.

Ollie is a highly driven, commercially astute senior leader with 20+ years Commercial and Business Development experience across Technology and Engineering sectors.

Ollie has worked extensively across Europe, North America and Asia and has held a variety of commercial leadership roles in FTSE 100, private equity owned and start-up companies.

Most recently Ollie was Chief Commercial Officer for an EV battery start up where he led the acquisition of new customer partnerships with some of the world’s leading car brands.

Prior to that, roles held include VP Commercial and Business Development for a market leading global automotive engineering firm with responsibility for driving the sales growth of its electrification business unit, and VP Customer Business Group where he was responsible for leading multiple large and complex key accounts across Europe and Asia with over $1bn cumulative revenues.

Sondrel was founded over two decades ago in 2002 and is a well-known name in Europe but not in the USA. Why do you think that is?
Sondrel is fundamentally a service company. To give customers the best possible service when you are starting out, you need to be close to them so, being headquartered in the UK, Sondrel focussed on the UK, European and Israeli market for the first phase of the company’s growth as it is our home region. That enabled us to ensure that we built up a reputation with customers for going above and beyond in order to deliver high quality products. As we grew from pure “design services” towards more turnkey “ASIC” developments, we expanded our skills with design centers to include Morocco and India. It is only recently that we have started addressing the American market as we believe that we offer something that US customers want.

So how are you differentiating yourselves?
We sit perfectly in the zone of just the right size to be able to deliver chips with a high level of personal service. Our rivals are often too large with too many projects to give the level of personal service that we provide or too small to have the expertise needed to deliver the kinds of ultra-complex custom chips that are our speciality. This is 100% aligned with my own career, which has always been customer focussed. At Sondrel, we want customers to be successful and are completely focused on that mission. That means giving each customer a level of care and attention to details that will be almost impossible to match.

How does that tie in with delisting from being on the stock exchange and going private?
The challenge with being a listed company is that you have two objectives that can often conflict. Firstly, to deliver to investors who often have short timeframe goals and, secondly, to deliver to customers where the timescales are measured in many months. And there are times when it is very difficult to do both effectively as many companies have found and have gone back to being private. Sondrel is company with amazing engineers, huge experience and a stellar reputation with customers. That’s a solid foundation for the future of any company. And so that became the course of action with a delisting and restructuring. Then, as planned, I became the CEO to really focus, capitalise and commercialize the company’s strengths – customer focus, personal service, high quality and world-class design skills for ultra-complex custom chips.

Your background is from the commercial side of technology.  Does that help or hinder you as a CEO?
Absolutely it helps. When you think about it, the commercial aspects are critical to both our customers and our own ability to grow.  Over the past year, when I was VP of Marketing & Sales, I met each of Sondrel’s regular customers. Some of them have been using Sondrel for many years for project after project. In every case, when I asked them why pick Sondrel, the answer was always because Sondrel cares. We care passionately about the customer, the customer’s project and the commercial success of the chip – and our strong engineering team reflects this. We will do everything we can to be outstanding partners for our customers. The real shame is that most of our work is covered by NDAs so we cannot talk publicly about all our successes. This customer-first approach is something I’ve embraced throughout my career and was rooted in always seeking solid, mutual commercial success. So, “yes” I think a commercial background is a significant advantage to being a CEO.

It sounds like you are going to be very hands on?
This is very much the way I do things and how Sodrel operates. Frequent face-to-face meetings and continuous communications. People always want to do business with people they know, like and trust. We really dig into a new business opportunity to fully understand what the customer is trying to achieve and what matters most to them. And then we invariably exceed expectations by providing insights and ideas to make the project better by drawing on our experience from hundreds of successful projects. A design project for a billion-transistor chip is incredibly detailed and complex and we have the in-house tools, design flows and experience to deliver to agreed budgets and timeframes.

We work with the customer early in their definition stages, helping the customer where we can to make the right decisions for their chip project, unlike many of our rivals. This builds a huge level of trust and confidence in our ability to deliver chip designs which means that the customers then started asking us to handle the whole chip supply chain process right through to final silicon. This is now a standard turnkey service that enable customers to focus on their skill sets safe in the knowledge that their silicon will be delivered. This is particularly of interest to startups who are skilled in innovation but not in all the challenges of taking a chip through the supply chain stages of the manufacturing, testing and packaging so they need to outsource that to someone like us.

And that is why our US office is located in the heart of Silicon Valley so we can provide a personal service to all the exciting innovative startups located there.

There is only one of you, so how can Sondrel provide the level of personal service that you described for every customer?
We do that by having a mindset of customer-first, across the company. We even assign a Customer Success Manager to customer projects. Their job is to ensure that everything is running to schedule and that the customer is always in the loop, ensuring that the customer’s project is successful, which means we are successful in meeting the customer’s expectations. It’s how we deliver a very personal service to every customer.

You have said personal service is what differentiates Sondrel. What does that mean in practice?
Companies come to Sondrel because they want a chip that is custom made to their exact specifications. Basing your project on standard, off-the-shelf chips means that anyone can copy it. A custom chip is unique and the Power, Performance and Area have been tuned precisely to deliver the performance and cost required. And determining those parameters is done right at the start of a project discussion at the Architectural Specification stage. This is a perfect example of where we are different. Our team creates an in-depth, holistic view of the chip, what its functions and features are, and how to make it. For example, what node to use, what IP will be needed, which of our Architecting the Future reference architectures to use, how to incorporate Design for Test, etc. This means that Sondrel provides customers with an incredible detailed plan of how it will successfully design the chip. Often it includes improvements that Sondrel has brought to the table based on its engineers having experience in successfully delivering hundreds of other projects over the years.

This is level of intense personal service inspires confidence and trust that Sondrel will deliver to schedule and requirements that is continued throughout the project with regular meetings so that the customer is always fully informed on progress along with new ideas to make the design even better. For example, in one recent project we were able to reduce the power requirement of the chip, much to the delight of the customer.

You mentioned Architecting the Future. What is that?
This is a family of pre-defined reference architectures that provide a fast start for a new project rather than starting from scratch every time. This means that not only can we deliver a project faster but it also means that we can handle more projects simultaneously as our engineers can focus on the complex novel parts of a design knowing that the framework is already tested and ready to be built on.

Reusing trusted IP is fundamental to the ability to design chips and that’s what these architectures are. They reduce risk and time to market to help ensure customer success.

Talking about IP, I note that you have started licensing IP?
That was one of my first tasks as CEO to realise and commercialize existing assets. We have a library of IP blocks that we have created over the years for various projects where we found there was no commercial IP available with the performance or functionality required. They might be a bit unusual but that’s what we need when creating our ultracomplex chip design so, if we needed it for a chip design, then others might as well. In fact, we have just licensed our first IP block – our Firewall IP.

It’s yet another way to help customers be successful through our personal service of ensuring that they get exactly what they need.

Also Read:

Sondrel Redefines the AI Chip Design Process

Automotive Designs Have No Room for Error!

Sondrel’s Drive in the Automotive Industry

Transformative Year for Sondrel

Podcast EP263: The Current and Future Impact of the CHIPS and Science Act with Sanjay Kumar

Podcast EP263: The Current and Future Impact of the CHIPS and Science Act with Sanjay Kumar
by Daniel Nenni on 11-29-2024 at 10:00 am

Dan is joined by Sanjay Kumar. Most recently, Sanjay was senior director at the Department of Commerce on the team implementing the CHIPS and Science Act. Before that, he was in the industry for more than 20 years, up and down the semiconductor value chain working at systems companies such as Meta, fabless companies such as Infineon, NXP, Broadcom and Omnivision and manufacturing companies such as Intel Foundry.

Sanjay provides a detailed analysis of the impact across the semiconductor value chain resulting from the CHIPS and Science Act. He details the significant industry investments that have resulted from the initial funding from the US Government.

Sanjay describes the collaboration between ecosystem companies and what the impact has been, and could be in the future. He discusses the impact AI has had as well. He describes possible future collaboration scenarios and the potential positive impact on the US semiconductor manufacturing sector.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

Posted on

CEO Interview: Dr. Yunji Corcoran of SMC Diode Solutions

CEO Interview: Dr. Yunji Corcoran of SMC Diode Solutions
by Daniel Nenni on 11-29-2024 at 6:00 am
Categories: CEO Interviews

Dr. Yunji Corcoran (1)

Dr. Yunji Corcoran is the Chairwoman and CEO of SMC Diode Solutions. Dr. Corcoran has managed a successful career in the power semiconductor field for over 30 years, specializing in design, manufacturing, and global sales. She holds a bachelor’s degree in physics from Nanjing University and a PhD in semiconductor materials from Stony Brook University in New York. She currently focuses on management functions but still considers herself to be a dedicated engineer. Outside of the semiconductor business, Dr. Corcoran is passionate about traveling, cooking, and collecting cookbooks from around the world.

Tell us about your company?
SMC Diode Solutions is an American-led semiconductor design and manufacturing company based in Nanjing, China.

Since the company’s founding in 1997, SMC has provided customers with high-quality products and timely delivery. SMC’s products have been designed with great attention to detail and performance while focusing on the needs of customers.

The SMC team designs and manufactures its own products that are widely distributed in global markets. SMC’s portfolio includes Silicon Carbide Schottky rectifiers and MOSFETs, Silicon Schottky rectifier diodes, ultrafast recovery rectifier diodes, TVS diodes, Schottky and rectifier modules, and many more.

What problems are you solving?
At SMC, we focus on solving two major problems: the first is power conversion and the other is efficiency. The function of the devices we produce is to convert the voltages, whether that’s from AC to DC, DC to DC or DC to AC. During the conversion, we ensure our products minimize the conversion loss while increasing efficiency.

What application areas are your strongest?
In general, we work with any market segment that has to do with power conversions and protections such as power supply, AC-DC and DC-DC converters, and inverters. We also create products for the aerospace, automotive, and medical industries. With the opening of our new fab in June 2024 and growth of our silicon carbide capacity, we are also growing our presence in the electrical vehicle and renewable energy markets.

What keeps your customers up at night?
I think the thing that keeps our customers up at night is exactly the same thing that keeps us up at night: how to survive in this very competitive market. In today’s market, you not only need to make great products that satisfy your customers’ needs, but you also need to be constantly researching, innovating, and striving to be better than your competitors. Our customers choose to work with us because they know they will receive good, quality products from us to in turn provide quality products to their customers. So, in short, the constant question and pressure of how to keep improving upon their products is what keeps our customers up at night. We have a strong focus on research and development at SMC, so I hope our dedication to creating better products helps to ease the pressure and concern our clients also face.

What does the competitive landscape look like and how do you differentiate?
The discrete power semiconductor market is a very competitive market, and there are quite a few players with very similar products. What makes SMC different is our unique products and services. From the initial design to manufacturing, we use the most advanced technology and software to create the best products possible. For example, our power diodes and MOSFET products have a lower power loss compared to our competitors which is a very important parameter for those types of products. Not only do our products perform well and have really great reliability, but we also bring a personal touch through our customer care. Our whole company is dedicated to providing a personal service to our customers, and we approach everything with flexibility and care.

What new features/technology are you working on?
As always, SMC’s focus is on our products. We pride ourselves on making quality products and delivering enhanced performance through technology innovations. Currently, we are working on expanding our products portfolio now that we have more than quadrupled our production capability with the recent opening of our new fab. We are also looking into extending our existing power module capability as the next step to strengthen our market position.

We’re excited about what’s to come and are continuously innovating and updating our products and product offerings. Our focus remains on our products and with growing interest in those, we will continue to grow our business and provide the best power product for our customers.

How do customers normally engage with your company?
As a company with a presence in the United States, Germany, China, and South Korea, we have distributors and clients all over the globe. You can contact our distributors or a local sales representative in your area for additional information about our company and products. Detailed contact information is on our website.

Additionally, more often than not, you will find someone from our company at any major semiconductor event. For general questions, feel free to contact us at sales@smc-diodes.com or check our website updates to see where you can find us next.

Also Read:

CEO Interview: Sandeep Kumar of L&T Semiconductor Technologies Ltd.

CEO Interview: Dr. Sakyasingha Dasgupta of EdgeCortix

CEO Interview: Bijan Kiani of Mach42

Posted on

CEO Interview: Rajesh Vashist of SiTime

CEO Interview: Rajesh Vashist of SiTime
by Daniel Nenni on 11-28-2024 at 10:00 am
Categories: AI, CEO Interviews

Fotosbyt/san jose

Rajesh Vashist is SiTime’s Chairman and Chief Executive Officer and has served in this role since September 2007. Prior to joining SiTime, Mr. Vashist served as CEO and chairman of the board of directors of Ikanos Communications, Inc., a semiconductor and software development company, from July 1999 to October 2006. Mr. Vashist led the organization from a two-person pre-revenue startup to a public company with 90% market share and a market value of $600M. Prior to Ikanos, Mr. Vashist served as a general manager of a $450M business unit at Adaptec, a storage company, and held various general management and marketing positions at Rightworks, an ERP software company, Vitelic Semiconductor and Samsung Semiconductor.

Tell us about your company.
Precision Timing is the heartbeat of modern electronics. Whether it’s in AI data centers, networking infrastructure, automated vehicles, personal mobility or IoT, nothing works without precise timing. In today’s connected intelligence era, SiTime’s uniqueness lies in delivering Precision Timing to enable electronic products that are smarter, faster and safer. We are taking a new approach to the highly fragmented timing market, using semiconductor technology and processes to reimagine time. SiTime is the only company that is solely focused on all aspects of timing, from components to systems and software. We are using microelectromechanical systems (MEMS) technology to transform the $10 billion timing market with products that offer higher performance, smaller size, lower power consumption and unmatched reliability. What makes SiTime unique, apart from our Precision Timing technology, is the diversity of applications, products, customers, and our team.

What problems are you solving?
The timing market has been historically fragmented, but with the need for today’s electronics to be faster, always connected, more intelligent, and safer, a differentiated approach is vital. To meet these requirements, electronics are now being deployed in the “real world,” outside pristine environments such as air-conditioned offices. Here, electronic devices are being subjected to environmental stressors such as rapid temperature changes, extreme temperatures, shock and vibration. The incumbent timing technology for the past several decades, quartz, is susceptible to these stressors, which can impact the performance and reliability of intelligent, connected electronics. Our MEMS and analog technologies solve this problem. We deliver Precision Timing solutions that are orders of magnitude more resilient to these environmental stressors and help make electronics smarter, faster, and safer. For example, we are enabling higher timing performance and accuracy in AI data centers and 5G networks, where nanosecond-level synchronization is required, even in the presence of environmental stressors.

Our semiconductor-based MEMS technology enables us to offer the smallest size, more features, and higher stability, which, again, meets the requirements of modern electronics. With our fabless semiconductor supply chain and built-in programmability, we deliver better supply reliability and the flexibility to configure a device to each customer’s exact application requirements. Over the past decade, we have improved our Precision Timing performance by several orders of magnitude, something that the incumbents have not been able to do. To summarize, we deliver higher performance, more features, higher reliability, smaller size and lower power to our customers.

What application areas are your strongest?
Our strongest markets for Precision Timing include AI data centers and all the networking electronics within, communications, automotive safety and infotainment, IoT, and aerospace and defense. Specific applications within these markets include 800G/1.6T optical modules, smart network interface cards (SmartNIC), 5G remote radio units (RRUs), advanced driver assistance systems (ADAS) cameras, radar and LiDAR, smartwatches and low-Earth orbit (LEO) satellites. For example, AI networking requires ultra-low jitter and latency, which our timing products deliver. Similarly, in autonomous vehicles, Precision Timing is critical for sensor synchronization and rapid decision-making. Our Endura Epoch Platform, for example, is making inroads in aerospace and defense applications, offering unmatched performance and reliability for critical applications such as positioning, navigation and timing (PNT) services. In fact, because of the various benefits of our timing technology, it’s safe to say that we are crucial to the future of electronics.

What keeps your customers up at night?
We’ve realized that we have two kinds of customers: the ones who have experienced and seen the benefits of our programmable timing chips and those who we are working closely with to come up with creative ways to address their timing issues. Our customers are concerned about keeping pace with rapid technological advancements. Whether they’re developing AI, communications, automotive or IoT applications, they must continuously innovate with their products. With the explosion of data-driven applications, companies also worry about achieving low-latency, high-reliability networks, especially as 5G and AI infrastructures continue to scale.

Another point is the ability to meet customers’ needs for scaling fast when the demand for their products increases. SiTime’s silicon manufacturing process ensures a stable, reliable, and independent supply chain with shorter lead times for the highest-quality timing products in the market. Our job is to be inventive and dependable so customers can be comfortable.

What does the competitive landscape look like and how do you differentiate?
After being asleep for so many years and considered a commodity product, timing technology is undergoing a transformation, led by SiTime. Traditional quartz-based timing solutions have been incumbents for the past several decades, but they are rapidly being displaced, given their lack of differentiation and programmability as customers demand smaller, more resilient and reliable, and energy-efficient Precision Timing solutions that our MEMS technology offers. SiTime differentiates itself as the only pure-play silicon timing company, which gives us a unique position to drive innovation in this market. Our programmable clock and oscillator solutions enable customers to tailor their timing devices for specific application needs, a major advantage in high-performance sectors like AI computing and data centers. We also focus heavily on system-level solutions, combining silicon MEMS technology with analog circuitry, advanced algorithms and high-volume packaging, which enables us to deliver unmatched precision, reliability, small size and low power consumption.

What new features/technology are you working on?
As the world becomes more connected and intelligent, we are focused on developing more Precision Timing solutions that meet the demand for stability, resilience, and lower power consumption.

For example, we have design wins with our Precision Timing products in all key applications of the AI ecosystem, including GPU and CPU boards, interconnect switches, optical modules, NIC cards, accelerator cards, active cables, and switches. To provide a sense of scale of our focus on AI, in 2024, we shipped 70 unique part numbers across 14 product families to 30 different customers developing AI hardware.

One of our key product innovations for the world of AI is our Chorus clock generator—the industry’s first integrated clock system-on-a-chip (ClkSoC) designed for AI data center applications. The Chorus ClkSoC integrates a clock IC, a silicon MEMS resonator, and oscillator circuitry into a single chip. By integrating the resonator and eliminating the need for external quartz crystal devices, Chorus simplifies system clock architectures for AI systems, accelerates design time by up to six weeks, and improves reliability and resilience. Chorus clocks are engineered to deliver 10 times better performance in half the size of equivalent quartz-based devices.

Another recent innovation is the Endura Epoch Platform, a ruggedized MEMS-based oven-controlled oscillator (OCXO) that provides significant improvements in size, weight, and power (SWaP) while delivering benchmark timing performance for AI data centers and 5G infrastructure. Epoch OCXOs solve critical timing issues that were previously insurmountable with quartz technology, especially when deployed under extreme environmental conditions. We’re also expanding the use of MEMS technology in emerging markets like aerospace and defense with our Endura Epoch Platform, which offers enhanced performance and resilience for critical PNT services.

How do customers normally engage with your company?
We collaborate closely with each customer’s technical team to design and deliver Precision Timing solutions that meet their unique application needs. This collaborative, system-level approach allows us to build deep, long-lasting relationships with industry leaders and ensures that our timing technology continues to meet their evolving requirements. We also engage with our customers’ commercial teams to ensure adequate supply and other business terms. In addition to the large players in electronics, we also support smaller players who might be developing new applications, devoting equal attention to their developments.

How do you see Precision Timing evolving in the future, and what role will SiTime play in that transformation?
Precision timing will become even more critical as the world continues to embrace AI, 5G-Advanced and 6G communications, automated driving, personal mobility, and IoT. We’re not only addressing today’s timing technology needs but also anticipating future demands. SiTime will continue to innovate in the areas of MEMS technology, analog circuits, packaging, integration, and software to develop Precision Timing solutions that push the boundaries of what’s possible. We envision a world where SiTime’s Precision Timing products are embedded in every critical application, from the cloud to the edge, enabling faster, smarter and more connected systems everywhere.

Also Read:

CEO Interview: Dr. Greg Newbloom of Membrion

CEO Interview: Sandeep Kumar of L&T Semiconductor Technologies Ltd.

CEO Interview: Dr. Sakyasingha Dasgupta of EdgeCortix

CEO Interview: Bijan Kiani of Mach42

Posted on

CEO Interview: Dr. Greg Newbloom of Membrion

CEO Interview: Dr. Greg Newbloom of Membrion
by Daniel Nenni on 11-28-2024 at 6:00 am
Categories: CEO Interviews

Greg Nebloom Membrion

Greg Newbloom, Ph.D., is the founder & CEO of Membrion, a cleantech startup focused on recycling wastewater from harsh industrial processes. Membrion makes electro-ceramic desalination (ECD) membranes out of the same material as the silica gel desiccant packets found in the bottom of a beef jerky package. Dr. Newbloom’s leadership and entrepreneurial efforts have been recognized by a half-dozen regional and national awards including a “35 under 35” from the American Institute of Chemical Engineering and a 2024 Meaningful Business 100 award (MB100).

He has 50 patents in addition to co-authorship of a textbook and 300+ citations in many publications. His work is regularly featured in both local and national media. Dr. Newbloom has a BA in Science from Oregon State University, an MA in Science from The University of Washington, and holds his Doctor of Philosophy (Ph.D.), in Chemical Engineering also from The University of Washington.

Tell us about your company:
Membrion is a pioneering technology company that specializes in electro-ceramic desalination membranes. We help industries manage some of the toughest wastewater challenges, providing innovative solutions that handle high-salinity, acidic, and heavy-metal-laden wastewater in addition to advanced recovery objectives in water stressed areas. Our focus is on sustainable water reuse, ensuring that companies can meet their environmental goals without compromising on efficiency.

What problems are you solving?
We address the critical need for efficient and cost-effective wastewater treatment, especially in industries dealing with corrosive and complex effluents. Traditional filtration methods often struggle with these challenging conditions, but our ceramic membranes excel where others fail, providing an effective way to treat and recycle water in even the harshest environments.

What application areas are your strongest?
Our strongest applications are in industries with highly complex wastewater streams, including semiconductor manufacturing, metal finishing, mining, and chemical processing. These sectors often face the most stringent regulations and operational challenges when it comes to wastewater treatment, and Membrion’s solutions are tailor-made to meet those needs.

What keeps your customers up at night?
Our customers are concerned about staying compliant with changing environmental regulations, reducing their water consumption, and finding cost-effective ways to manage wastewater. They also worry about system downtime due to trucking delays and fouling or corrosion in their current water treatment systems, which can halt production and increase costs. Membrion alleviates these concerns by offering onsite, durable, reliable, and high-performing membrane technology that minimizes these risks.

What does the competitive landscape look like and how do you differentiate?
The water treatment industry is full of conventional polymeric membranes and chemical-based treatments. Membrion stands out by offering a unique ceramic membrane that is more durable and resistant to harsh conditions. Unlike competitors, our technology thrives in highly acidic, saline, and heavy metal-contaminated wastewater, offering a longer lifespan and better performance over time. This differentiation enables our customers to reduce operating costs while achieving their sustainability goals.

What new features/technology are you working on?
We are continually improving the efficiency and longevity of our ceramic membranes, exploring advanced applications in emerging markets such as mineral extraction (copper, lithium, and others) and battery recycling. We are also working on expanding our modular membrane systems to be more scalable and easier to integrate into existing industrial setups.

We offer a Water Service Agreement to our customers which provides a no-risk, performance-based model where you only pay for treated water that meets your specifications. With no upfront costs for equipment or maintenance, Membrion guarantees effective wastewater treatment at a lower price than traditional methods.

How do customers normally engage with your company?
Customers typically engage with us through direct consultations, where we assess their specific wastewater challenges and design customized solutions. We also partner with engineering firms and integrators to implement our technology into new or existing water treatment systems. Additionally, we offer pilot programs to allow customers to test our membranes in their operations before committing to full-scale adoption. If you think Membrion solutions will be a good fit for your facility, let us know your wastewater challenges: https://membrion.com/contact-us/.

Also Read:

CEO Interview: Sandeep Kumar of L&T Semiconductor Technologies Ltd.

CEO Interview: Dr. Sakyasingha Dasgupta of EdgeCortix

CEO Interview: Bijan Kiani of Mach42

Posted on

MZ Technologies is Breaking Down 3D-IC Design Barriers with GENIO

MZ Technologies is Breaking Down 3D-IC Design Barriers with GENIO
by Mike Gianfagna on 11-27-2024 at 10:00 am
Categories: 3D IC, EDA, MZ Technologies

MZ Technologies is Breaking Down 3D IC Design Barriers with GENIO

3D-IC design can be both exciting and frustrating. It’s exciting because it opens a new world of innovation possibilities – opportunities that aren’t constrained by the rules of monolithic chip scaling. It can be frustrating because of the large array of complex technical challenges that must be overcome to make this new paradigm accessible. MZ Technologies’ mission is to conquer 2.5D & 3D design challenges for next generation electronic products by delivering innovative, ground-breaking EDA software solutions and methodologies. MZ’s flagship product is GENIO, and the company recently announced a comprehensive roadmap for it. If 2.5 & 3D design are in your future, this is big news. Let’s examine how MZ Technologies is breaking down 3D-IC design barriers with GENIO.

What’s Coming

GENIO™ is an integrated chiplet/packaging co-design EDA tool. The announced roadmap calls for improvements to the product throughout 2025, starting with four significant additions that will be unveiled in mid-January.  Other new features will be added around the middle of the year and at year’s end.

The features coming at the beginning of the year address some truly difficult design challenges. The focus is thermal and mechanical stress. These enhancements will also include an improved and modernized user interface.  

These new features tackle next-generation 3D-IC design challenges head-on.  To provide some background, 3D heterogeneous devices suffer from thermal stress that comes from uneven heat distribution during operation, potentially leading to warping and even reliability failures. To address thermal challenges, robust management strategies are essential. Application of the right tools will minimize temperature differentials. The result is optimal performance and longevity of the chiplets used in the design.

Mechanical stress can result from processes such as thermal expansion mismatch and substrate flexing. These effects can cause interconnect failures and even delamination. A robust approach is needed to maintain structural integrity and performance across varying operational conditions and material interfaces. The new version of GENIO delivers enhanced capabilities in both areas. Mid-year, the company is expected to add additional thermal and interconnect features to GENIO.

Anna Fontanelli

These enhancements build on the momentum already achieved by GENIO. Anna Fontanelli, Founder and CEO of MZ Technologies commented, “MZ Technologies rolled out the first commercially available co-design tool three years ago and we feel an obligation to the EDA community to continue to innovate.”

What’s Already Here

MZ Technologies has already released several enhancements. GENIO 1.7 saves even more design time than the previous version thanks to its ability to track and classify potential design process issues.

Using a dedicated, always-on dock, the newest version alerts designers to a full list of problems classified by severity, scope, and category. This extensive check provides a real-time update after any operation and new violations are added to something called the Issues Dock. The user can select an issue in this dedicated dock and all errors and warning are highlighted with a severity-driven color across the GUI and the 2D/3D design views. The amount of data associated with 2.5 & 3D design is massive and this feature helps to manage that complexity.

The new version performs several categories of checks, including placement rules during floor planning to catch violations such as overlapping instances, out of boundary placement, and ignored keep-out zones. Other checks spot vertical routing connectivity issues such as broken nets and crossing fly lines. The graphic as the top of this post shows an example of this capability.

To Learn More

MZ Technologies provides automated solutions that facilitate the design and optimization of complex, heterogeneous IC systems. You can learn more about this unique company on SemiWiki here. You can read the full text of MZ Technologies roadmap announcement here. And you can find out more about GENIO here. And that’s how MZ Technologies is breaking down 3D-IC design barriers with GENIO.