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CEO Interview with Moti Margalit of SonicEdge

CEO Interview with Moti Margalit of SonicEdge
by Daniel Nenni on 03-22-2026 at 2:00 pm

SonicEdge Moti Margalit

Moti Margalit is the CEO and co-founder of SonicEdge, a deep-tech pioneer reinventing sound through ultrasonic modulation – unlocking smaller, vibration-free speakers with studio-quality audio.

With a background in lasers and electro-optics, Moti transitioned from technologist to inventor. His career spans 150+ patents and a pivotal stint at Intellectual Ventures, where he learned to turn scientific breakthroughs into market-defining products.

A problem-solver with an entrepreneurial spirit, Moti was inspired to create SonicEdge when a conversation about hearing aids revealed the limitations of traditional audio tech. Today, he is on a mission to make SonicEdge as transformative for sound as LEDs were for light by scaling its tech to power the future of immersive, personalized audio.

Tell us about your company

For 150 years, speakers have worked the same way – a coil, a magnet, and a moving diaphragm. SonicEdge is changing that. Our patented modulated ultrasound technology represents a fundamental paradigm shift in how sound is generated: solid-state MEMS micro-membranes replace all moving mechanical parts, producing an ultrasonic carrier that is actively modulated into full-range audible sound. This is the architecture that gives AI glasses a voice, makes truly invisible hearables possible, and brings studio-
quality audio to form factors that legacy drivers simply cannot reach.

Our chip-scale speakers measure 6.5×4×1mm – delivering more output per milliwatt and per cubic millimeter than conventional drivers at this scale. With 28+ patents, a signed development contract with a leading AI glasses company, and a chip integration partnership with a leading global semiconductor manufacturer announced at CES 2026, SonicEdge is building the audio foundation for the next generation of wearables.

What problems are you solving?

The consumer electronics industry is caught in a contradiction: devices are getting smaller and smarter, but the speaker inside them is still a mechanical component engineered in the early 20th century. Voice-coil drivers are bulky, power-hungry at small scales, and impose hard physical limits on how thin and light a wearable can be.

Others have tried to solve this with MEMS, and hit a fundamental wall. Silicon
membranes moving air directly at audio frequencies produce limited output, yielding narrow-band, low-efficiency tweeters that cannot replace a full-range driver. The physics simply don’t scale.

SonicEdge’s breakthrough was to ask a different question entirely. Rather than moving air at audio frequencies, our MEMS membranes vibrate at 400kHz – acting as the world’s smallest air pump, far above the threshold of human hearing. That ultrasonic carrier, invented and patented by SonicEdge, is then amplitude-modulated to produce audible sound across a 2Hz–40kHz range – wider than any conventional driver at this scale. The speaker die measures 6.5×4×1mm, contains no voice coil or permanent magnet, and fabricates on standard MEMS processes. Unlike piezoelectric MEMS tweeters, this delivers full-range output from a solid-state chip – the first of its kind designed for high-volume consumer wearables.

What application areas are your strongest?

SonicEdge’s strongest application areas are those where the speaker has historically been the hardest component to fit – where industrial design, comfort, and miniaturization leave no room for the mechanical compromises of legacy drivers.

In smart glasses and AI glasses, the challenge is extreme: a speaker must live
inside a temple arm that is millimeters thin, yet deliver clear, directional audio all day. This is precisely the use case SonicEdge’s modulated ultrasound technology was built for, and it is already being designed into leading AI glasses platforms.

True wireless stereo (TWS) earbuds and open-wear speakers (OWS)
represent the highest-volume opportunity. As the market shifts toward open-ear designs that sit lightly on or around the ear rather than sealing the canal, output efficiency and form factor become critical – both areas where SonicEdge’s solid- state architecture outperforms conventional drivers.

Hearing aids demand the most stringent combination of miniaturization, power efficiency, and audio fidelity of any consumer device. SonicEdge’s modulated ultrasound speaker is a natural fit for next-generation OTC and prescription devices pushing toward near-invisible form factors.

Smartwatches and wearable devices increasingly require embedded audio for
notifications, voice assistants, and health alerts – in housings where a
conventional speaker is simply too thick and too power-hungry to integrate
cleanly.

Smartphones and mobile devices represent a longer-term but significant
opportunity: as handsets continue to thin and under-display designs leave less
internal volume, a solid-state speaker that fabricates like a semiconductor
becomes an attractive alternative to the last remaining mechanical component in the device.

Beyond audio, SonicEdge’s ultrasonic pump technology opens doors into adjacent applications entirely. The same 400kHz MEMS air-pumping mechanism that generates sound can be redirected toward active chip cooling, a growing challenge in AI-edge and wearable processors, as well as gas sensing, micro-fluidics, and other applications where a solid-state, chip-scale actuator operating at ultrasonic frequencies offers capabilities no mechanical device can match.

SonicEdge’s modulated ultrasound MEMS technology – invented and patented by SonicEdge – has been designed into AI glasses, TWS earbuds, open-wear speakers, hearing aids, smartwatches, and smartphones. The same ultrasonic MEMS pump architecture that generates full-range audio from 2Hz to 40kHz is also applicable to active chip cooling, gas sensing, and micro-fluidic actuation – all from a solid-state, semiconductor-fabricated die with no moving mechanical parts. SonicEdge holds 28+ patents covering modulated ultrasound audio, MEMS transducer architecture, and ultrasonic pump applications across consumer electronics and industrial sensing.

What keeps your customers up at night?

The companies building the next generation of wearables and hearables are navigating a market that is simultaneously saturating and accelerating. Differentiation is getting harder. Consumers expect devices that are lighter, thinner, and more capable with every product cycle — and the gap between what industrial designers want to build and what legacy components allow them to build is widening.

At the component level, the speaker remains the most stubborn constraint. It is the one part of the device that hasn’t fundamentally changed – still mechanical, still bulky relative to everything around it, still a ceiling on how slim a frame can be or how long a battery can last. For product teams designing AI glasses or next-generation earbuds, the audio subsystem is often the last thing to get resolved and the first thing that forces a design
compromise.

Alongside form factor pressure, there is a deeper anxiety about platform lock-in. As AI becomes the dominant interface for wearables – with always-on voice assistants, real-time translation, and health monitoring – audio quality and latency are no longer just product features. They are the user experience. Getting the acoustic foundation wrong at this stage means building on a constraint that compounds with every subsequent generation.

SonicEdge helps its customers bridge those constraints – and in doing so, gives them back the freedom to put the magic back into audio.

What does the competitive landscape look like, and how do you differentiate?

The competitive landscape for miniaturized audio breaks into three tiers. First, the legacy dynamic driver manufacturers, the companies with decades of mechanical refinement behind them, who are reaching the physical limits of how small and efficient a voice-coil driver can be made. Second, a wave of MEMS speaker startups attempting to miniaturize conventional speaker physics onto silicon – most of whom have produced capable tweeters but have not solved the full-range output problem. Third, the semiconductor giants who supply the audio chipsets that sit behind all of these drivers, and who are increasingly looking for a next-generation transducer technology to integrate.

SonicEdge competes in none of these tiers in the conventional sense, because
modulated ultrasound is not a refinement of existing speaker technology, it is a replacement for it. Where others optimize within the constraints of legacy acoustic physics, SonicEdge operates outside them entirely. The differentiation is not incremental, it is architectural.

That distinction is increasingly recognized at the highest levels of the industry.
SonicEdge holds a signed development contract with a leading AI glasses company, and at CES 2026 announced a chip integration partnership with a leading global semiconductor manufacturer – embedding SonicEdge’s modulated ultrasound IP directly into next-generation audio chipsets. When the semiconductor layer adopts your architecture, the competitive conversation changes fundamentally.

The MEMS speaker competitive landscape includes legacy dynamic driver
manufacturers, piezoelectric MEMS tweeter companies, and emerging solid-state audio
startups. SonicEdge is the only company to have developed and patented a full-range solid-state speaker based on modulated ultrasound – a technology category it created.

Unlike piezoelectric MEMS speakers, which produce limited-bandwidth output
unsuitable for full-range audio, SonicEdge’s modulated ultrasound architecture delivers 2Hz–40kHz response from a 6.5×4×1mm die with no voice coil, no permanent magnet, and no mechanical moving parts. SonicEdge’s modulated ultrasound IP is being integrated directly into next-generation audio chipsets by a leading global semiconductor manufacturer.

What new features/technology are you working on?

SonicEdge’s development roadmap in 2026 is focused on three fronts: deepening silicon integration, expanding the SonicTwin platform, and scaling array-based acoustic architectures.

On the silicon front, the CES 2026 announcement of our chip integration partnership with a leading global semiconductor manufacturer marks a structural shift in how SonicEdge’s technology reaches the market. By embedding modulated ultrasound IP directly into next-generation audio chipsets, SonicEdge removes the last integration barrier for OEMs — the technology becomes part of the semiconductor stack, not an add-on component. This is the path to high-volume deployment across the full range of wearable and hearable platforms.

The SonicTwin module, the smallest integrated speaker-microphone solution currently on the market,is being extended in 2026 to support advanced environmental awareness, health monitoring, and ultra-low-latency audio. Co-packaging MEMS speakers with microphones in a single module enables tighter acoustic feedback loops, improved active noise cancellation, and the always-on audio intelligence that next-generation AI wearables demand.

Further sensor integration is on the roadmap – bringing biometric and environmental sensing into the same compact acoustic package.

Array-based solutions represent one of the most compelling frontiers. By arranging multiple MEMS transducers in controlled configurations, SonicEdge can deliver precisely steered acoustic beams – enabling private listening experiences where sound reaches only the intended listener, and dramatically reducing audio leakage and noise pollution in shared or public spaces. This beamforming capability, native to the solid- state MEMS architecture, opens new dimensions of both user privacy and acoustic design freedom that no conventional speaker array can match.

How do customers normally engage with your company?

SonicEdge serves two distinct tiers of customer engagement.
For product teams and smaller OEMs, the path to integration is straightforward: production-ready MEMS speaker modules and SonicTwin speaker-microphone units are available for direct evaluation and design-in.

These customers get access to a fully characterized, semiconductor-fabricated acoustic component that drops into their design process with minimal friction and no custom development required.

For strategic partners, the engagement runs deeper. A product team facing a specific acoustic constraint that conventional components cannot resolve will find in SonicEdge a technical collaborator, not just a supplier. SonicEdge’s engineers work alongside partner teams to optimize the modulated ultrasound architecture for their specific form factor, power envelope, and acoustic targets – co-defining what becomes possible rather than simply substituting one component for another. As silicon integration matures
through the semiconductor chipset partnership announced at CES 2026, this strategic model will scale further by bringing SonicEdge’s technology to a broader set of OEMs through the established supply chains of a global semiconductor manufacturer, while preserving the depth of technical partnership that has defined the company’s most significant relationships to date.

Also Read:

CEO Interview with Dr. Mohammad Rastegari of Elastix.AI

CEO Interview with Jerome Paye of TAU Systems

Podcast EP334: The Unique Benefits of LightSolver’s Laser Processing Unit Technology with Dr. Chene Tradonsky


Podcast EP336: How Quadric is Enabling Dramatic Improvements in Edge AI with Veer Kheterpal

Podcast EP336: How Quadric is Enabling Dramatic Improvements in Edge AI with Veer Kheterpal
by Daniel Nenni on 03-20-2026 at 10:00 am

Daniel is joined by Dr. Veer Kheterpal. Veer has founded three technology companies and possesses full-stack expertise spanning software to silicon across edge and datacenter applications. Currently, he is the CEO & co-founder of Quadric, a semiconductor IP licensing company that delivers the blueprints for efficient, flexible AI processors to a wide range of customers designing chips for varied applications.

Dan explores the innovative solution offered by Quadric with Veer. The solution includes licenseable AI processor IP and a software stack that opens the opportunity to develop innovative AI applications at the edge. Veer describes some of the agentic edge-based AI applications he uses today to run his company. He explains that it is now possible to achieve in one day the volume of communication follow-up, presentation development and proposal generation that used to take one to two weeks. The power and flexibilty of the Quadric platform help to make this possible.

Veer describes the impact Quadric-enabled edge-based agentic AI can have on personal laptops, industrial manufacturing, robotics and security. He describes the power of software innovation that Quadric enables for AI deployment, using statistics to discuss performance improvements over the past few years. Hardware has delivered about 15X but software has delivered 25-30X.

CONTACT QUADRIC

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

 


Captain America: Can Elon Musk Save America’s Chip Manufacturing Industry?

Captain America: Can Elon Musk Save America’s Chip Manufacturing Industry?
by Jonah McLeod on 03-20-2026 at 6:00 am

Elon Musk Lip Bu Tan Wafer Deal

Intel has posted three consecutive years of falling revenue and an $18.76 billion loss in 2024 alone—and the U.S. government has handed it tens of billions of dollars to fix the problem. The government money isn’t fixing the real issue, which isn’t technical. It’s cultural. Intel got slow, political, and risk-averse—the kind of company where decisions take forever and nobody wants to be wrong in a meeting. Meanwhile TSMC, the company Apple relies on to make its iPhone chips, just keeps getting better because it runs its factories like a military campaign. That gap is the problem. And there’s only one guy who might be able to close it.

Elon Musk. Before you roll your eyes, hear the pitch first.

In 2010 Musk picked up the shuttered NUMMI plant—a sprawling East Bay facility that GM and Toyota had just abandoned—for $42 million, which was basically nothing for a five-million-square-foot factory. The workforce that had operated the place under GM was so dysfunctional that even their own union called them the worst in the American auto industry—drinking on the job, deliberate sabotage on the assembly line. The place had a long history of failure before Toyota briefly made it work and then walked away. Musk took the same buildings, retooled them, and built a car factory from scratch inside them. Today it produces nearly 560,000 vehicles a year—30 percent more than NUMMI ever managed at its peak—and it’s now the highest-volume car plant in North America. He didn’t inherit a working operation. He inherited a corpse and built it into the most American-made car company in the country by domestic parts content. The chip that runs it is the one thing he hasn’t figured out how to make in America.

What Musk fixed at Fremont wasn’t the technology. The technology was already there—the buildings, the basic equipment infrastructure, the workforce pool. What he fixed was the culture. The decision velocity. The intolerance for excuses. The willingness to surface problems instead of burying them. He took a factory that had failed under two of the most experienced automotive manufacturers in the world and made it the best in the business—not by inventing new manufacturing physics, but by running the place differently.

Ford, GM, and Toyota didn’t lose to Musk because they lacked engineers or capital or decades of manufacturing experience. They lost because their organizations had calcified. Decisions required consensus. Problems got smoothed over. The gap between what was happening on the floor and what leadership believed was happening grew until it became unbridgeable. Sound familiar? It should. Dylan Patel at SemiAnalysis documented the same process at Intel with analytical rigor—a company that under Andy Grove ran on what he called “constructive confrontation”: data-driven decision-making, extreme accountability, an engineering culture so intense that Pat Gelsinger once described meetings with Grove as “dentistry without Novocaine.” You came in with your numbers or you had no right to be there. That culture made Intel an unstoppable freight train. Then Grove stepped down, and Intel chose its first non-engineer CEO. From that point forward, Patel documents, technical decisions gave way to political ones, fiefdoms replaced accountability, and the organization that had once yelled its way to clarity became one where problems got buried to protect careers.

By the time Bob Swan—a professional CFO on his tenth such role—was running Intel, the company was spending as much on stock buybacks as on capital expenditures for its fabs. That’s not a manufacturing company. That’s a financial engineering operation wearing a semiconductor company’s clothes. Samsung’s own semiconductor leadership admitted the same disease in a staff memo—”the culture of hiding or avoiding problems to get through the moment”—as its best engineers walked out the door for SK Hynix and its customers walked out the door for TSMC. Three different companies—GM, Intel, Samsung. Same organizational failure. Same result.

There is one American industrialist who shares Grove’s essential operating philosophy—and it isn’t anyone running a semiconductor company. Grove ran Intel like a company perpetually one bad decision from irrelevance, even when it dominated the market. Problems surfaced fast because hiding them was more dangerous than fixing them. Decisions got made fast because slow decisions were a form of organizational decay. He’d survived Nazi occupation and Soviet rule before arriving in America with nothing. He knew what institutional failure looked like from the inside. He spent his career making sure Intel couldn’t repeat it.

Musk is a South African immigrant who built his companies in industries where entrenched incumbents had used decades of institutional advantage to avoid the hard work of genuine competition. Both men arrived as outsiders. Both built their credibility through manufacturing discipline rather than inherited position. Both are brutally intolerant of the gap between what leadership believes is happening and what is actually happening on the floor. Grove called it constructive confrontation. Musk calls it “delete the requirement“—if you can’t justify why something exists, remove it. Same philosophy. Different century.

Grove took a memory chip company being destroyed by Japanese competition and transformed it into the dominant microprocessor company in the world—by betting everything on manufacturing and architectural discipline when the old model was failing. Musk took a dead car factory and made it the highest-volume plant in North America—by betting everything on a new operating culture when the old one had failed twice. The semiconductor industry now has a vacancy that looks exactly like the one Grove filled in the 1980s. The question is whether Musk sees himself in that role—not just as a frustrated chip customer, but as the person who can rebuild American semiconductor manufacturing culture the way Grove built it the first time.

The question nobody in the semiconductor industry is asking out loud is: could Musk do to chipmaking what he did to car making?

Intel’s problem isn’t that making advanced chips is physically impossible for Americans. It’s that Intel can’t organize itself to do it with the speed and discipline the job requires. The engineers exist. The equipment exists. What’s missing is an operator willing to run the place like TSMC does—relentlessly, with zero tolerance for excuses and slow decisions. That’s not a technical skill. That’s an organizational one. And it’s exactly what Musk demonstrated he can build at Fremont—turning a production line two global giants had given up on into the most productive car factory in North America.

The obvious pushback is that Musk knows nothing about semiconductor manufacturing. That’s true. But TSMC’s edge is the culture of the people running the factories—how fast they make decisions, how seriously they take yield, how intolerant they are of the kind of bureaucratic drag that paralyzed Intel. You can hire process engineers. You can’t easily hire the operator mindset that makes them work as a unit. Musk had never run a high-volume car factory when he took over Fremont. He knew how to fix a broken manufacturing culture. That turned out to be the only thing that mattered.

And right now, the timing couldn’t be better. Intel is cutting its global workforce by nearly a third—from 109,000 people to a target of 75,000—with no severance packages and no buyouts, just a pink slip and nine weeks of benefits. Process integration engineers, yield development engineers, module technicians: the exact people you need to staff a world-class fab are hitting the job market in waves. Intel is, unintentionally, assembling Musk’s talent pool for him. The broader industry faces a projected shortage of 88,000 engineers by 2029, which sounds like a problem until you realize that the operator who can offer the most compelling mission and the best compensation will win that war. Musk did it at Fremont.

The rest of the world isn’t waiting around to see what America does next.

Jensen Huang just paid $20 billion for Groq—not the company, but its patents, software stack, and people, including founder Jonathan Ross, who built the Language Processing Unit as a purpose-built AI inference chip. The deal is structured as a licensing agreement, letting Nvidia sidestep antitrust review while absorbing a serious competitor in the inference market. The chip itself is already in production—Samsung is manufacturing the Groq 3 LPU on its 4-nanometer process, and Jensen thanked Samsung by name at GTC. Where exactly those wafers are being pulled is Samsung’s business. The irony is that the most strategically significant AI inference chip now being produced for the American market is being made by a South Korean company, designed by technology Nvidia just bought, for a market TSMC and Samsung have every intention of owning.

That’s the landscape. Not one American foundry in that picture.

Japan is making its own move. Rapidus—a government-backed foundry startup in Hokkaido—is racing to put 2-nanometer chips into mass production by 2027. Tokyo has committed $12 billion to the project so far, with Toyota, SoftBank, and Sony behind it. The technology was licensed from IBM. The fab is rising in Chitose, a dairy-farming town near Sapporo that is now home to some of the most advanced lithography equipment on the planet. Rapidus won’t beat TSMC on volume—analysts are clear about that. The pitch is fast turnaround, geopolitical safety, and a manufacturing address that isn’t Taiwan or Seoul. Japan watched its semiconductor industry collapse in the 1990s when Korean and Taiwanese competitors outmaneuvered it on cost and scale. It is not making that mistake again.

But there is a structural problem no amount of government funding solves. The founding keiretsu members—Toyota, Sony, NTT, SoftBank, and the others—aren’t just investors. They were meant to be the anchor customers. The logic was that Japan’s industrial giants would seed the demand that justified the fab. What they haven’t done is commit their chip designs to Rapidus’s unproven process, because doing so means staking their own product roadmaps on a foundry that hasn’t yet demonstrated commercial yield—and that decision has to work its way through the same consensus-driven corporate culture that governs everything else in a keiretsu. The customers and the investors are the same companies. And they’re still watching.

Now look at the playing field. TSMC is the dominant foundry and is not slowing down. Samsung is manufacturing the chips that Nvidia just spent $20 billion to control. Japan is spending $12 billion of public money to build a national foundry from scratch. Intel is firing engineers by the thousands and hoping the bleeding stops. And the United States—the country that invented the semiconductor industry, that created Silicon Valley, that still produces the best chip designers in the world—has no foundry operator with the culture, the speed, or the will to compete at the leading edge.

TSMC is building factories in Arizona right now. That sounds like it solves the problem—American soil, American chips. It doesn’t. It’s still TSMC running the place. It’s not an American company with an American manufacturing culture. It’s a Taiwanese company operating a satellite. And every advanced wafer Arizona can produce through 2027 is already spoken for by Apple, Nvidia, AMD, and Qualcomm. Tesla couldn’t even get in the queue.

Which brings us to the Samsung Taylor fab—and to understand Taylor, you have to understand Samsung’s history in Texas first.

The Austin fab opened in 1996 on what had been a cornfield on the northeast edge of the city—the first foreign-owned semiconductor fabrication plant ever built in the United States. It made chips for Apple’s first iPhones, Nvidia’s early GPUs, and Tesla’s first Autopilot computer. It turned a profit—the first time Samsung had ever done so at a fab outside South Korea. For three decades the Austin fab made money by doing what it was designed to do: mature nodes, established customers, competitive yields, steady execution.

The Taylor fab is a completely different bet. Samsung broke ground there in 2022 with $17 billion in capital and $6.4 billion in U.S. taxpayer money, planning to make 4-nanometer chips. Then AI exploded, the market moved to 2-nanometer, and Samsung pivoted mid-construction—turning a controlled build into chaos. By mid-2024 its 2nm yield was running between 10 and 20 percent, numbers that make chips commercially useless. Samsung pulled back to a skeleton crew and stopped installing equipment. The fab was 92 percent built and effectively dead. No customers. No production. No path forward.

Then Musk signed a $16.5 billion contract to manufacture Tesla’s AI6 chip there—the processor that will power its self-driving cars and Optimus robots. Samsung’s stock jumped nearly 7 percent the day it was announced. Analysts called it transformational. What actually changed was that Samsung had a customer on paper. The yield problem didn’t move. Mass production has since slipped to 2027 at the earliest. Tesla’s AI6 is now running at least six months late because Samsung can’t get its 2nm process stable.

The yield numbers at Taylor are the symptom. The disease runs deeper—and it’s the same disease Dylan Patel documented at Intel. Samsung’s own semiconductor leadership admitted in a staff memo that “the culture of hiding or avoiding problems to get through the moment, and reporting unrealistic plans based solely on hopeful expectations” had spread through the organization. There are credible reports that Samsung Foundry management concealed actual yield data not just from customers but from its own chairman. Qualcomm left over yield failures. Nvidia left. Google left—transferring its Tensor chip to TSMC after years with Samsung. The market share gap between Samsung and TSMC has widened from 35 percentage points in 2019 to nearly 60 points today. That’s not a process problem. That’s an organizational one—the same organizational failure Patel documented at Intel, playing out in a fab near Giga Texas, on chips Musk is waiting for.

The parallel to Fremont is exact. NUMMI failed under GM not because the technology was wrong or the workers were untrainable. It failed because the culture was broken—problems hidden, decisions avoided, accountability diffused across layers of management until nobody owned anything. Musk walked in, ripped out that culture, and replaced it with one where problems surface fast and get fixed faster. The Taylor fab is NUMMI with a cleanroom. The equipment is there. The building is there. The contract is there. The customer, Musk, is there. What’s missing is someone willing to run the place the way TSMC does—and intolerant enough of excuses to fix the yield problem that Samsung’s own leadership has been too hierarchical and too slow to address.

Which is precisely why Taylor is a more compelling entry point for Musk than Intel. Intel is America’s designated semiconductor champion—every move watched, litigated, and second-guessed by Washington. Samsung Taylor is a Korean company’s American asset. The politics don’t follow it. It’s sitting on American soil with American taxpayer money already spent. The fab is built. The equipment is going in. The process node is right. The only thing missing is an operator who can fix the culture and make the yields move.

Musk posted on X that the fab is “conveniently located not far from my house.” It’s 40 minutes from Giga Texas. He is sending his most critical AI chips—the ones that will determine whether Tesla’s autonomous vehicle program lives or dies on schedule—to a fab that can’t yet make them reliably, run by an organization that hid its problems until they became a crisis. Austin proved Samsung can run a profitable American fab. Taylor is proving that having the money to build one and knowing how to run one are entirely different things. And the only reason that fab exists at all is $6.4 billion in American taxpayer money.

That experience—his own supply chain held hostage to a foreign manufacturer’s yield problems, TSMC’s capacity locked out by Apple and Nvidia, the entire U.S. semiconductor strategy resting on companies that aren’t American—appears to have been the breaking point. Musk just announced Terafab: Tesla’s bid to build the chip supply chain America never built for itself. A vertically integrated facility. Logic, memory, and packaging under one roof. Two-nanometer process technology. The stated target is 100,000 wafer starts per month, scaling toward a million.

Nobody should mistake an announcement for a running fab. Semiconductor fabs take years to build and commission. Tesla has zero semiconductor manufacturing experience. Jensen Huang, who knows this industry as well as anyone alive, called the challenge “virtually impossible”—and Huang has every incentive to want more chip production capacity in the world. The skeptics are not wrong about the difficulty. But they said the same thing about the American car industry. That it was mature. That the incumbents were too entrenched. That nobody was going to walk into Detroit’s backyard and outmanufacture Ford, GM, and Toyota on American soil. Musk did it anyway. In Fremont. On a cornfield that became a car lot that became a corpse that became the highest-volume auto plant in North America.

The question no one is asking out loud: what’s the fastest way in?

Building a greenfield 2nm fab from scratch takes years and tens of billions of dollars. Hiring a team capable of running it takes years more. But there’s a 92-percent-complete, $44-billion fab sitting 40 minutes from Giga Texas, already contracted to make Tesla chips, struggling with yield problems that are fundamentally about manufacturing culture—exactly what Musk demonstrated he can fix at Fremont. Intel brings American political complexity, legacy obligations, and a workforce already demoralized by three years of decline. Samsung Taylor brings none of that. It’s a clean asset with a broken culture, a customer already in place, a contract running to 2033, and an operator who told Samsung he would walk the production line personally.

No acquisition has been announced. No takeover is confirmed. But the logic is identical to Fremont—a distressed manufacturing asset, underperforming against its potential, in exactly the right location, making the right product, failing for the reasons Musk has proven he can address.

He didn’t build a new car factory in 2010. He took over a dead one and made it the best in the business.

The vacancy is real. The asset is sitting there. Musk has seen enough—he just announced Terafab, his bid to build the chip supply chain America never built for itself. Whether he starts from scratch or starts 40 minutes from his front door is the only question left.

Also Read:

Intel Foundry: How They Got Here and Scenarios for Improvement

Things From Intel 10K That Make You Go …. Hmmmm

Global 2nm Supply Crunch: TSMC Leads as Intel 18A, Samsung, and Rapidus Race to Compete


WEBINAR: Reclaiming Clock Margin at 3nm and Below

WEBINAR: Reclaiming Clock Margin at 3nm and Below
by Daniel Nenni on 03-19-2026 at 2:00 pm

Webinar Blog Image Reclaiming Clock Margin

At 3nm and below, clock networks have quietly become the dominant limiter of SoC power, performance, and yield. Yet most advanced-node designs still rely on abstraction-based signoff methodologies developed when voltage headroom was generous and interconnect effects were secondary.

That assumption no longer holds

As supply voltages approach device threshold and interconnect resistance increases, clock delay becomes highly sensitive to waveform shape, power delivery interaction, and local variability. In this regime, traditional signoff methodologies evaluate uncertainty sources independently – voltage sensitivity, jitter, aging, LVF residuals – and combine them conservatively. The result is structural pessimism.

You can access the webinar replay here. And that’s how to reclaim margin in advanced nodes.

Across many advanced-node clock networks, signoff guard bands routinely consume 25-35% of the clock period. A meaningful portion of that margin – often on the order of 10-15% – exists not because silicon requires it, but because abstraction-based methodologies approximate electrical behavior rather than directly enforcing it.

This has real consequences

Clock distribution can account for 30-40% of total SoC dynamic power at advanced nodes. Guard banding frequently translates into elevated operating voltage to preserve frequency targets. Because dynamic power scales with the square of supply voltage, even modest over-voltage applied to protect worst-case assumptions can impose a disproportionate power penalty.

The key question is no longer whether margin exists. It is whether your methodology can distinguish modeling pessimism from true silicon limitation.

In this upcoming webinar, we will examine how clock margin inflation occurs and where recoverable margin typically resides in advanced-node designs. We will break down how near-threshold voltage sensitivity, power-supply-induced jitter, interconnect-dominated delay, aging derates, and residual variability accumulate under abstraction-based signoff flows.

We will then explore how full-clock, SPICE-accurate electrical analysis – applied from clock synthesis through final signoff – exposes modeling-driven pessimism and enables safer, physics-grounded margin reduction.

Representative advanced-node design scenarios will illustrate:
  • How per-stage delay pessimism accumulates across clock depth
  • How jitter guard bands can be materially overestimated
  • How recovered margin can be traded for voltage reduction or frequency headroom
  • Why margin recovery disproportionately amplifies system-level PPA

If you work in STA, CTS, timing signoff, or advanced-node program management, this session will challenge long-held assumptions about clock verification at scale.

At 3nm and below, competitiveness is no longer determined by how much margin you can add. It is determined by how much unnecessary pessimism you can remove – with confidence.

If you are responsible for timing closure or PPA optimization in advanced-node designs, this webinar will be directly relevant to your work.

You can access the webinar replay here. And that’s how to reclaim margin in advanced nodes.

Also Read:

What is the 3nm Pessimism Wall and Why is it An Economic Crisis?

The Risk of Not Optimizing Clock Power

Taming Advanced Node Clock Network Challenges: Jitter


WEBINAR: HBM4E Advances Bandwidth Performance for AI Training

WEBINAR: HBM4E Advances Bandwidth Performance for AI Training
by Don Dingee on 03-19-2026 at 10:00 am

HBM advantage in AI training

The rapid proliferation of LLMs and other AI applications, and of high-end GPU platforms that run them, is putting intense pressure on the performance requirements for memory technologies. Designers need to be keenly aware of how to make the most of their memory and controller choices, which can be moving targets given the rapid pace of new developments. To wit, Rambus is launching its cutting-edge HBM4E memory controller IP product with AI training applications in mind. With this launch, a webinar hosted by Nadish Kamath, Director of Product Marketing at Rambus, explores HBM technology and makes the case for selecting HBM4E for the most advanced AI training applications.

The “memory wall” versus AI training

Kamath starts with a reference to the “memory wall,” which is an ongoing challenge for computing system designers. Traditional dynamic RAM technology has steadily advanced – and when viewed on its own timeline, the progress looks good – but Kamath says it’s not anywhere near keeping pace with processor technology. Over the past two decades, processor technology has improved 60,000x. Over the same period, DRAM bandwidth has increased by only 100x, and interconnect bandwidth by even less, 30x.

A major reason for this disparity is the difficulty of achieving the broad interoperability needed to recapture the massive investments in DRAM fabrication capacity if memory interface specifications advance too quickly. Mainstream memory must be usable across as many processor architectures as possible. Ditto for interconnect specifications; in fact, that situation may be even more economically acute. Processors, however, have fewer constraints. GPU internal architecture, especially given multicore technology, has grown by leaps and bounds while maintaining consistent interfaces to other off-chip subsystems.

However, as is often the case, there’s a catch. Massive GPUs targeting AI training are so fast now that it’s getting difficult to keep their engines fed with data from the memory subsystem. Because AI training data is, by its very nature, a unique stream that changes from sample to sample, caching, which has been a boon to CPU technology, is much less effective. That means the performance burden now falls on main memory, and advanced memory architectures must prioritize raw bandwidth on optimized interfaces.

Advantages of HBM in AI training

That’s where HBM comes in. Where other technologies like LPDDR6 accompany consumer-level GPUs, offering a balance of performance, capacity, and cost, HBM sits squarely in the higher-performance space for GPUs targeting AI training servers. The HBM specifications continue to stretch in several dimensions – wider buses, faster transfer rates, higher stack heights with multiple HBM dies in a 3D footprint, and larger individual die capacity. HBM4E uses the same 2048-bit interface as HBM4 and increases the transfer rate by up to 2x.

Rambus is focusing on HBM memory controller IP, and carving out an advantage there. Kamath says lessons learned from 100+ HBM design wins and decades of memory interface expertise have rolled into their new HBM4E controller IP offering. Where competitive HBM controller IP products may be limited in the transfer speeds they can achieve, Rambus is leveraging its experience to deliver the full 16 Gb/sec per pin from its updated HBM4E controller, translating to 4.1 TB/s of bandwidth per HBM4E memory device.

There’s more in the webinar, as Kamath steps through additional information on AI use cases, background on the HBM architecture, and a full description of their HBM4E controller’s capabilities. If you’re trying to get more out of AI training servers and racks, give this a watch.

Register for the webinar today:   HBM4E Advances Bandwidth Performance for AI Training

Also Read:

How Memory Technology Is Powering the Next Era of Compute

Siemens Wins Best in Show Award at Chiplet Summit and Targets Broad 3D IC Design Enablement

Siemens Fuse EDA AI Agent Releases to Orchestrate Agentic Semiconductor and PCB Design


Siemens Wins Best in Show Award at Chiplet Summit and Targets Broad 3D IC Design Enablement

Siemens Wins Best in Show Award at Chiplet Summit and Targets Broad 3D IC Design Enablement
by Mike Gianfagna on 03-19-2026 at 8:00 am

Siemens Wins Best in Show Award at Chiplet Summit and Targets Broad 3D IC Enablement

The recent Chiplet Summit in Santa Clara was buzzing with new designs and new design methods. It felt like the industry had turned a corner at this year’s event with lots of new technology and design success on display. Siemens EDA had a large presence at the show and took home the Best in Show Award for Packaging Design. There were a lot of companies at the show but only three Best in Show Awards. This accomplishment is significant. I spent some time chatting with a long-time friend at the show to get some of the backstory on what’s next.

The information was quite exciting – the best is yet to come. Let’s examine how Siemens wins Best in Show Award at Chiplet Summit and targets broad 3D IC design enablement.

The Award

Siemens won in the Packaging: Design category for its Innovator3D IC™ solution. The other two Best in Show awards were for Packaging: Hardware and Connectivity and Interoperability. Chuck Sobey, general chair of this year’s Chiplet Summit provided some comments. “Siemens’ Innovator3D IC stands out for its combination of design lifecycle coverage and breadth of industry-standard data models. As multi-die integration grows more complex, this solution gives designers the tools to move faster and innovate with confidence. We congratulate Siemens EDA on this well-deserved recognition.”

AJ Incorvaia, senior vice president of Electronic Board Systems, Siemens Digital Industries Software also commented. “The recognition of Innovator3D IC at Chiplet Summit reinforces our mission to deliver cutting edges technologies that radically accelerate how our customers are developing the next generation semiconductors. With Innovator3D IC, we are delivering a true system-level design approach where heterogeneous dies, chiplets, interposers and packages are optimized and validated within a single unified flow.”

This is an impressive achievement. While at the show I did some digging to find out more.

What’s Next

Tony Mastroianni

I was able to spend some time at the show with Tony Mastroianni, senior director of 3D IC Solutions Engineering at Siemens EDA. I have some great memories working with Tony that go all the way back to RCA Solid State in Somerville, New Jersey.

Later, I worked with Tony as he pioneered advanced package design at eSilicon Corporation. Tony has quite a broad background in chip and advanced package design with additional work in analog design at Silicon Compiler Systems, and design and consulting work at Mentor Graphics and ASIC Alliance Corp. After eSilicon was acquired by Inphi, Tony once again focused on advanced packaging there before joining Siemens EDA over five years ago.

Tony pointed out that the challenge in front of us is not an advanced packaging problem. Rather it’s a massive system design problem. One that must integrate chiplets using advanced packaging technology to deliver next generation products based on a 3D IC approach. Innovation in materials will be important here. Tony mentioned the move to organic interposers. This change will lift the reticle size limit that silicon interposers have. He envisioned 2 X 3-foot rack size interposer panels that will replace PCB boards and integrate ~1,000 chiplets.

To tame a problem of this size requires a substantial focus on integrating many tools to deliver complete solutions to address the various phases of 3D IC design. This is what Tony is working on with a team of senior architects and a substantial group of engineers to build and test solutions. This group is not part of any product team, so it delivers a central engineering function to build and test complete solutions. If enhancements are needed at the tool level this is done in collaboration with the product groups. I was impressed to hear this strategy. It is quite forward-looking.

There are several phases of design that must be integrated to form a complete solution. Juan Rey, senior VP and GM of Calibre and Siemens EDA CTO gave a keynote at the Chiplet Summit that provided a glimpse of what is coming. He talked about a heterogeneous 2.5/3D IC design process that includes:

Design planning and prototyping:  with system design/modeling, HW/SW, PCB, and system in package (SIP) partitioning, planning, and optimization, including thermal analysis and signal integrity/power integrity (SI/PI) planning.

Design implementation: including design/verification for the system and chiplet RTL. HW/SW co-simulation/validation and hardware design start here, as does substrate and interposer design/verification. So does SIP thermal, stress, SI/PI and static timing analysis (STA) analysis as well as chiplet physical design and verification. SIP DFT design and verification and chiplet DFT design and verification also start here.

Verification and signoff: continues many of the previous tasks and adds SIP and chiplet test program development.

Prototype manufacturing, bring-up and release to manufacturing: adds validation/bring-up, interposer and substrate manufacturing, package assembly, chiplet manufacturing, SIP final test and characterization/qualification.

Juan also discussed how Siemens applies AI to improve 3D IC design productivity. Machine learning, reinforcement learning, generative, and emerging agentic AI capabilities are integrated across the end-to-end design flow, enabling faster optimization, broader design space exploration, and more efficient convergence on optimal system-level PPA.

This is a high-level overview. There are many more tasks involved but you get the idea. This process is quite a bit more complex than monolithic chip design and building integrated capabilities that work together is what Jaun was describing and what Tony and the team are working on.

We touched on many other additions to the design process, including more prevalent use of fiber optic communication to increase speed and reduce power. Integrated photonics and backside power delivery are two game-changing additions to manage performance and power.

My conversation with Tony opened many new areas where Siemens can have a significant impact on 3D IC design. I expect there will be more announcements coming from this work. I will be watching for it.

To Learn More

If 3D IC is in your future, Siemens EDA has a lot to offer. You can learn more about how Siemens Digital Industries Software is enabling 3D IC design here.  And that’s how Siemens wins Best in Show Award at Chiplet Summit and targets broad 3D IC design enablement.


Siemens Fuse EDA AI Agent Releases to Orchestrate Agentic Semiconductor and PCB Design

Siemens Fuse EDA AI Agent Releases to Orchestrate Agentic Semiconductor and PCB Design
by Bernard Murphy on 03-19-2026 at 6:00 am

Fuse Agentic System

Though terminology sometimes get fuzzy, consensus holds that an agent manages a bounded task with control through a natural language interface. An agentic orchestrator, itself an agent, manages a more complex objective requiring reasoning through multi-step actions and is responsible for orchestrating those actions. By way of example, setting up an individual simulation might be handled by an agent. An orchestrator could manage setting up multiple scenarios for running simulation, launching those runs, debugging detected failures and summarizing results. More hands-free automation, at least in principle, freeing engineers to explore a wider range of optimizations and analyses.

A concrete example

These days I’m very much into specific instances of AI benefits rather than abstract potential benefits. Amit Gupta (chief AI strategy officer, senior vice president and general manager, Siemens EDA) shared a nice example, close to his prior roots in founding and growing Solido.

A designer wants to fully characterize a logic function across all relevant process corners. They have Liberty files for some voltage and temperature corners, encoded in the file names, but not all. The orchestrator figures out what is missing and sets up tasks for a generator agent to build the missing files, here leveraging Solido ML-based technology.

Next the orchestrator triggers validation agents to check the generated files, looking for potential inconsistencies or unphysical behavior. Where problems are found the orchestrator can trigger repair agents, then re-run validation. This may resolve most errors, perhaps leaving only one or two files that must be corrected manually.

Contrast this with the effort a designer must invest today: figuring out which files are missing, setting up Solido runs to build those files, checking each and manually repairing errors, then re-running validation. Each step well within the capabilities of the designer but together a lot of administrative overhead, burning expert designer cycles that could be better invested elsewhere. Agentic systems automate that overhead, directed by natural language setup. Not replacing the developer but making them more productive.

A challenge

In the example above, all the EDA technologies managed by agents are from Siemens EDA. How does an agentic flow work when tools you might want to include in an agentic task are provided by competing EDA vendors? In my earlier example of setting up multiple simulation scenarios, running, then debugging, maybe your approved simulator is from one vendor whereas your preferred debugger is from another. How well can an orchestrator work in a mixed vendor flow?

This isn’t a question of data compatibility. Most EDA tools support industry approved or de facto standards. The issue is that effective agents need deep insight into how to control tools, for which there no standards (in fact standards here would stifle innovation). An agent must understand not only internal controls within a tool but also the intent behind those controls. In the Fuse Agentic flow this insight is enabled by a RAG pipeline.

I have written before about RAG (retrieval augmented generation) and its evolution to higher accuracy. First generation RAG, as in early chatbots, digested natural language text from any source and then could answer question prompts on any topic covered in that area. Pretty slick except that while often impressive, answers were sometimes spectacularly wrong. When you (a human) read the retrieved text, this isn’t too damaging – you quickly spot the mistake. But it is a big problem when an agent is relying on the accuracy of retrieval.

Now there is a concept of advanced RAG, which itself depends on agentic methods to improve accuracy in retrieval through reasoning, self-reflection and verification. Accuracy goes up significantly, as you have probably noticed in recent AI responses accompanying Google searches. Newer methods continue to advance but the important point here is that we can have more confidence in document scraping, which equally can drive more accurate agentic behavior around a tool (though still not perfect; still requiting that we trust but verify, as in all things AI).

Which leads back to how to integrate a “foreign” tool into an agentic flow. A design team or the tool providers can build a model by scraping tool documentation, and that model can then be integrated under the Fuse EDA AI agent.

More on the Fuse EDA AI Agent

Fuse can plan and orchestrate across the full range of Siemens EDA tools, from front to back in IC and PCB circuit design, implementation, verification and manufacturing sign-off. For industry-standard agentic compatibility, Fuse supports MCP interfaces, the NVIDIA Agent Toolkit, Nemotron models and the NVIDIA AI infrastructure for enhanced tool calling and reasoning capabilities.

Fuse builds on an advanced RAG pipeline and a multimodal EDA-specific data lake spanning RTL, simulation, implementation, test and more.

Siemens already boasts endorsements from Samsung (Jung Yun Choi, executive vice president of Memory Design Technology, Samsung Electronics) and NVIDIA (Kari Briski, vice president of generative AI, NVIDIA).

The product debuted at NVIDIA GTC 2026 and is available today. You can learn more HERE.


Accelerating Computational Lithography Using Massively Parallel GPU Rasterizer

Accelerating Computational Lithography Using Massively Parallel GPU Rasterizer
by Kalar Rajendiran on 03-18-2026 at 10:00 am

Rasterization Polygon to pixel based representation

As semiconductor manufacturing pushes deeper into the nanometer regime, computational lithography has evolved from a supporting step into a central pillar of advanced chip design. Mask synthesis, lithography simulation, and optical proximity correction (OPC) now demand unprecedented levels of accuracy and computational throughput. At the heart of these workflows lies rasterization, which is the process of converting complex geometric layouts into ultra–high-resolution pixel grids.

Rasterization – Polygon to pixel-based representation

 

Siemens EDA recently published a whitepaper presenting an innovative approach to addressing this topic. The whitepaper explores why rasterization has become a bottleneck and how an innovative rasterization algorithm using massively parallel GPU configuration addresses the challenges. Real-world performance results presented in the whitepaper reveal the innovative technique’s impact on next-generation semiconductor manufacturing.

Why Rasterization Matters More Than Ever in Lithography

Rasterization is often associated with computer graphics, but in electronic design automation (EDA), its role is far more consequential. In computational lithography, rasterized layouts are used to simulate how light propagates through masks and how photoresist responds at nanometer scales. Unlike graphics applications, where a pixel can be treated as simply on or off, lithography requires precise fractional pixel coverage and strict preservation of connectivity between extremely fine features. A tiny error introduced during rasterization can propagate through simulation and OPC loops, ultimately affecting yield and manufacturability.

As technology nodes shrink below a few nanometers, the resolution required for rasterization skyrockets, and the same operation must be repeated many times during iterative OPC flows. Even highly optimized CPU-based rasterizers struggle to keep up, turning rasterization into a dominant runtime bottleneck.

The Limits of Traditional Rasterization Approaches

Most traditional rasterization techniques rely on binary coverage models that work well for visualization but break down in lithography contexts. These approaches fail to capture subtle intensity variations and often introduce connectivity artifacts when dealing with thin lines or closely spaced features. At the same time, the sheer scale of modern layouts with billions of polygons and trillions of pixel evaluations places enormous pressure on memory bandwidth and compute resources.

This is where GPUs become attractive. Their massive parallelism is well suited to data-intensive workloads, but GPUs also present challenges, including irregular memory access patterns and sensitivity to numerical precision. Successfully using GPUs for lithography rasterization requires algorithms designed specifically for accuracy-first, massively parallel execution.

Rethinking Rasterization for GPUs

A GPU-optimized rasterizer for computational lithography starts with a fundamentally different mindset. Instead of sequentially processing polygons, the layout is spatially decomposed into independent regions that can be rasterized in parallel. Each region is mapped to GPU thread blocks, allowing thousands of threads to evaluate pixel coverage simultaneously.

Example of pixel classification and processing

Fractional pixel coverage is computed using floating-point arithmetic, not approximations, ensuring that boundary interactions are handled with nanometer-scale precision. Special care is taken to preserve sub-pixel connectivity so that thin features are not inadvertently broken during rasterization. Manhattan geometries benefit from simplified evaluation paths, while curvilinear shapes are handled using more general, yet still parallel-friendly, methods.

How the GPU Rasterization Pipeline Works

The rasterization pipeline begins with CPU-side preprocessing, where layout data is parsed and binned into spatial tiles. These tiles are transferred to the GPU in memory layouts optimized for coalesced access. On the GPU, each tile is processed independently: geometry is cached in shared memory, threads are assigned to pixels or small pixel groups, and each thread computes whether its pixel lies inside a polygon, outside it, or on its boundary.

Rasterization of L-shape using block of threads

Boundary pixels receive special treatment. Polygon edges intersecting a pixel are analytically evaluated, and the fractional area covered is computed precisely. Atomic operations ensure correct accumulation when multiple polygons affect the same pixel. This design achieves both high performance and deterministic accuracy, two properties that are rarely achieved together in large-scale parallel systems.

The implementation leverages the CUDA programming model and is particularly effective on modern data-center GPUs from NVIDIA, which provide the memory bandwidth and concurrency required for extreme-resolution rasterization.

Real-World Performance Results Using Nvidia H100 GPUs

Performance benchmarking paints a compelling picture. When compared with highly optimized CPU-based rasterizers, the GPU approach delivers dramatic speedups across a range of layouts. For designs dominated by Manhattan geometries, speedups of up to 290× have been observed. Even for more challenging curvilinear layouts, the GPU rasterizer achieves speedups of up to 45×.

Crucially, these gains do not come at the expense of accuracy. Across all test cases, absolute error remains below one percent relative to reference CPU calculations. This level of precision meets the stringent requirements of computational lithography and confirms that massive parallelism can coexist with nanometer-scale accuracy.

Why This Matters for EDA and Manufacturing

The implications of GPU-accelerated rasterization extend far beyond raw performance metrics. Faster rasterization shortens OPC and mask synthesis cycles, enabling more iterations within the same design window. This leads to better correction quality, improved yield, and reduced time to market. High accuracy and connectivity preservation ensure that these gains do not introduce new risks into manufacturing flows.

As designs increasingly incorporate complex, non-Manhattan geometries and as simulation fidelity continues to rise, the scalability of GPU-based rasterization becomes even more valuable. What was once a bottleneck becomes a scalable, future-proof component of the lithography pipeline.

Summary

Massively parallel GPU rasterization represents a significant shift in how computational lithography workloads are approached. As GPU architectures continue to evolve, offering more cores and higher memory bandwidth, the performance advantages of this approach are likely to grow. Future work will focus on deeper integration with existing EDA platforms, support for heterogeneous CPU–GPU workflows, and extensions to more advanced lithography models and three-dimensional effects.

You can download the entire whitepaper from here.

Also Read:

Formal Verification Best Practices

AI-Driven Automation in Semiconductor Design: The Fuse EDA AI Agent

Siemens Reveals Agentic Questa


Verification Analytics: The New Paradigm with Cogita-PRO at DVCON 2026

Verification Analytics: The New Paradigm with Cogita-PRO at DVCON 2026
by Daniel Nenni on 03-18-2026 at 8:00 am

The Cogita PRO Paradigm

Cogita-PRO, developed by Vtool, introduces a transformative approach to design verification by treating it as a big data challenge rather than a traditional debugging exercise. Released in February 2026, this tool shifts the focus from manual log and waveform inspection to advanced verification analytics powered by data processing, AI, and algorithmic insights.

In conventional verification flows, engineers write testbenches and tests, then spend considerable time running simulations, debugging failures with waveforms and logs, fixing bugs in RTL or testbench code, and chasing coverage closure. This process often proves inefficient, especially in the final stages where the last few percent of coverage consumes disproportionate effort. Checkers may miss subtle legal-yet-problematic corner cases, and the sheer volume of data from gigabytes of logs makes gaining a holistic view difficult.

Cogita-PRO redefines this second phase as Verification Analytics. After initial sanity checks, it ingests simulation outputs including UVM logs, software logs, VIP traces, and waveform databases. Input format remains agnostic thanks to flexible data processors. These feed into a central smart database where raw information transforms into structured occurrence tables.

Key concepts include nodes (recurring log messages or sampled waveform signals), data fields (variables like addresses, IDs, or priorities), and routes (sequences linking related nodes to represent transaction lifecycles). Users can perform data fabrication to derive new metadata, calculate values, or label entries without rerunning simulations. This enriched dataset enables powerful analytics.

The tool delivers multiple layers of insight. Visualization features show routes evolving over time or outstanding transactions per master, offering immediate clarity on system behavior. Blind combination algorithms detect anomalies and perform root-cause analysis by highlighting outlier routes, nodes, or data fields with anomaly probability scores. For instance, multiple methods might converge on a specific address causing a NoC deadlock.

Route shape analysis examines sequence patterns, durations, and field variations. Pass/fail modeling constructs profiles from known good tests, then flags deviations in failing runs, such as altered node orders or unexpected durations in NoC packet routes. These techniques uncover hidden bugs, performance issues, and unintended behaviors that traditional methods overlook.

Cogita-PRO supports three usage models. The first accelerates individual debugging and closure through a GUI, chat interface, or CLI, with optional LLM assistance for setup and exploration. The second scales to regressions, teams, and organizations by exporting understandings like processed data, models, and algorithms for reuse across tests, IPs, subsystems, SoCs, and future projects. The third embraces agentic AI, positioning Cogita-PRO as a debugging agent within multi-agent systems, potentially collaborating with RTL or testbench generative agents while maintaining human-in-the-loop oversight.

Overall, Cogita-PRO promises faster convergence toward tapeout with predictable readiness. It catches elusive logic and performance problems early, reduces reliance on manual sifting through massive datasets, and scales effectively across projects. Vtool encourages early adopters to conduct one-week on-site trials with real data to demonstrate measurable value and train initial users.

Bottom line: By applying visualization, anomaly detection, comparison, and analytics inspired by fields like fraud detection (where false positives are preferable to missed threats), Cogita-PRO empowers verification teams to achieve deeper understanding with less effort.

CONTACT VTOOL 

Also Read:

Formal Verification Best Practices

AI-Driven Automation in Semiconductor Design: The Fuse EDA AI Agent

Agentic AI and the Future of Engineering


Breker Hosts an Energetic Panel on Spec-Driven Verification

Breker Hosts an Energetic Panel on Spec-Driven Verification
by Bernard Murphy on 03-18-2026 at 6:00 am

Energetic panel on AI in verification

I was fortunate to be asked to moderate an evening panel adjacent to the first day of DVCon 2026, on AI-Driven SoC Verification starting from specs. You know my skepticism on panels, finding they rarely generate insights or controversy. This panel was quite different. Panelists were Shelley Henry (CEO, Moores Lab AI), Adnan Hamid (CTO, Breker Verification Systems), Deepak Manoharan (Senior Director of Engineering, Arm), and Michael Chin (Senior Principal Engineer, Intel Corp). If you want to know more about reality in AI deployment in functional verification, these guys have opinions. I summarize my takeaways below.

Why automate spec-driven verification?

The purpose of verification is to certify what is being built is (functionally) consistent with the design spec (or test spec, here assume design spec). This spec is generated by an experienced in-house architect, crossing what they currently know about customer requirements with what they know about available in-house baseline designs, IP options and expertise.

There are unavoidable challenges in specs. These remain moving targets some way into the design schedule. Architects deliver a first pass for design and DV teams to shift left, understanding that updates will continue. Customer(s) themselves may not yet have frozen their requirements as they continue to gauge market expectations. They too are shifting left to the architect. Add to this that neither writing, reading nor understanding are error-free.

If you have ever been on the review cycle for a document, you will understand how mistakes can happen. First pass review, diligently read and checked. Second and later passes skimmed with high chance of missing small but important changes. Revision tracking is an outdated solution for locating and understanding changes.

Extracting relevant updates is a perfect application for AI. Also perfect is dynamically discovering topic-relevant sections in the spec “Show me all mentions of fence in this spec”. A related challenge, similarly addressed, is dealing with specs which back-reference earlier specs.

Here I should acknowledge a good question from the audience, “What if you don’t have a spec?” This is startup territory: no baseline design and not enough time to create a spec. I’ve been in this position myself. A startup has a core differentiating idea and should be busy creating a proof of concept around that idea before they run out of money. Creating a spec is a very low priority. That said, pre-funding and in-flight they must create documents and mail/text threads to communicate internally. Perhaps these could be sucked into a spec generator (Shelly, any comments)?

Automation experiences in production design

How accurately can AI generate, from a raw spec, an intermediate representation, say a table of opcodes or a flow diagram of operation? The sense here is 90-95%, but that last 5% is hard. No ideas were shared on how to characterize this shortfall, though Shelly has thoughts on how the gap could be narrowed.

Good discussion around hallucinations and over-enthusiastic claims from AI, with general agreement that we should never accept early responses. Instead, repeat the question, eliciting different responses, pick your favorites and iterate to a good solution. An interesting perspective was the importance of figuring out where in the AI process is best to provide feedback, to guide/train the system onto a better path when it looks like it might be headed down an unproductive path. Live experience has shown this can evolve correctness from 40% on a first pass to 100% over successive learning passes. Impressive!

Why not automate this process setting different agents to work on an answer, judging between answers using a critique agent? Interesting idea though there were mixed feelings on how ready we are for that step (or whether we will be given the option).

Which brought us to trust. This boils down to decomposing tasks between checkpoints with easily human-checkable output. PSS generated from a spec is easy to read, therefore easy to catch errors. Going all the way from spec to UVM is a more challenging jump, though Shelly suggests there is a market for that too, perhaps more based on UVM familiarity than ease of checking.

Threat or opportunity for DV engineers?

Will DV engineers train AI and then be out of a job? One response was that AI will simply make us more productive. We are nowhere near maxing out appetite for new semiconductor devices. Using AI, more of these will be in reach and we’ll need all our engineers to satisfy that need.

A rather different viewpoint noted that design execs are now pushing for a shorter design lifecycle per chip, to be competitive on time to market and cost. AI will play a larger part in that lifecycle than we may find comfortable, but we may have to adapt. Engineers who are curious, who can ask good questions and have a learning mindset will thrive in an AI-centric process. Those who are stuck in their old ways will not do so well.

A third panelist told his kids that they should not plan to do what he does, because that job won’t exist when they graduate. Current DV roles will have been replaced by verification architects. (Shout out here also to Abhi Kolpekwar at Siemens who calls them “verification scientists”.)

In closing, we do indeed need to train the AI, just as we currently train junior engineers. I’m sure existing training collateral would be a good start. We also need to develop more systematized methods to assess the performance of AI verification. Today these may be captured in spreadsheets and communal know-how. Now we must define metrics which critique agents can check. And processes to support periodic human review and update.

Breker and MooresLab have partnered to create the first commercial AI-driven SoC verification solution, I assume addressing a number of these areas. You can learn more HERE, including a recording of the panel discussion.

Exciting times!

Also Read:

Verifying RISC-V Platforms for Space

A Principled AI Path to Spec-Driven Verification

Breker Verification Systems at the 2025 Design Automation Conference #62DAC