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Cybersecurity is getting more critical every day. Thanks to sophisticated AI attacks, the need for hardware chip-level security is greater than ever. To fortify hardware against these types of attacks is not easy. There are three key attributes of a successful strategy: a well-designed root-of-trust, collaboration to ensure a well-integrated solution and conformance with the latest security standards. Secure-IC and Silicon Labs recently released a press announcement that had all of these attributes. The result is Secure-IC and Silicon Labs raise the bar for hardware security. Here are some of the details.
What Was Announced
It was announced that Secure-IC’s Securyzr™ neo Core Platform served as the Root of Trust (RoT) at the heart of the Series 3 Secure Vault subsystem, enabling Silicon Labs’ SiXG301 SoC to withstand advanced threats. There is a lot to unpack in that statement, so let’s look at some aspects of this new collaboration to understand its significance.
Why It’s Significant
PSA Certified is a global standard enabling trust in connected systems for the electronics industry. PSA stands for platform security architecture. The standard defines clear, easy-to-understand levels of robustness and assurance for the Root of Trust (RoT) in SoCs. These specifications can be used by OEMs and cloud service providers for example.
This effort started with experts from seven founding companies, SGS Brightsight, CAICT, Riscure Keysight, UL, Arm, security consultancy Prove & Run, and TrustCB, who acted as the certification body. Today, the scheme is managed by GlobalPlatform, ensuring its continued growth and alignment with global security needs.
There are four levels of security certification available from PSA, Level 4 being the newest and most comprehensive. According to PSA, it is intended for chip vendors who use an integrated Secure Enclave or external Secure Element that provides a high level of robustness to physical and software attacks. The diagram below, sourced from psacertified by GlobalPlatform, illustrates the development of these standards.
Evolution of PSA standards
Level 4 is targeted at fortifying against hardware attacks, including resilience against the most advanced physical threats. This specification aims to validate resilience against sophisticated physical attacks such as laser fault injection, side-channel analysis, micro probing, and voltage manipulation. So, this joint announcement blazes an important trail as the first design that conforms to this standard.
With billions of connected devices expected to enter the market in the coming years, PSA Level 4 certification provides assurance that Silicon Labs’ and Secure-IC’s solutions will remain resilient against evolving cyber and physical threats.
More Details
Secure-IC’s Securyzr neo Core Platform is designed to address the diverse embedded security needs of various industries and applications. From chip-level hardware security to comprehensive chip-to-cloud solutions, the platform offers tailored configurations to meet different market security requirements, standards and certifications. Backed by over a decade of development and deployment in various industries, this platform delivers unmatched performance and versatility for the most demanding applications. The S100 neo series is tailored for general IoT and connectivity. The figure below illustrates the breadth of markets that the platform supports.
Comments About the Announcement
Executives from both Secure-IC and Silicon Labs weighed in on this important announcement.
Daniel Cooley
Daniel Cooley, CTO and SVP at Silicon Labs commented, “Our collaboration with Secure-IC has been essential to pushing the boundaries of security in connected devices. By integrating Secure-IC’s Securyzr neo Core Platform as the Root of Trust in our Series 3 architecture, we achieved the world’s first PSA Level 4 certification, delivering unparalleled protection today while building the foundation to keep our customers secure against tomorrow’s evolving threats.”
Hassan Triqui
Hassan Triqui, CEO and Co-Founder of Secure-IC commented, “This certification underscores the maturity of our Securyzr neo Core Platform and the strength of our long-standing partnership with Silicon Labs. By uniting world-class embedded cybersecurity with Silicon Labs’ leadership in secure and energy-efficient IoT solutions, we are shaping the future of trusted connected devices and reinforcing our shared commitment to raising the bar for the entire industry.”
Synopsys recently held a webinar session on this topic and Gustavo Pimentel, Principal Product Marketing Manager at the company led the webinar session. Going into the webinar session, I found myself wondering: why focus on PCIe 5.0, eight years after its release? With the industry buzzing about Edge AI, cloud computing, and high-performance applications, it felt like talking about “old news.” That curiosity turned out to mirror some of the audience questions during the webinar Q&A session. Another common question was whether it made sense to skip PCIe 5.0 entirely and jump straight to PCIe 6.0.
Gustavo offered clear answers. He explained why, for most applications today, migrating from PCIe 4.0 to PCIe 5.0 is the practical path. PCIe 6.0 is only warranted if a customer’s application absolutely demands it. The discussion delved into both design techniques and architectural integration strategies, demonstrating how PCIe 5.0 remains a highly flexible solution for balancing power, performance, area and latency tradeoffs across industries.
Edge AI: Driving the Next Cycle of Innovation
Edge AI is no longer a futuristic concept—it’s driving real change across devices and data centers. By processing data closer to the source, it improves privacy, strengthens security, and delivers faster, more personalized user experiences, all while reducing reliance on the cloud. AI workloads themselves are growing at an unprecedented rate. Estimates suggest that by 2027–2028, about 50% of data center capacity will be AI-driven, up from 20% today. AI model sizes double roughly every four to six months, far outpacing Moore’s Law, and processing demands continue to escalate dramatically.
To efficiently handle this explosion of data, devices and systems need interconnects that can keep pace. PCIe 5.0, with its high bandwidth and low latency, is ideally suited to enable edge SoCs to process AI workloads efficiently, while maintaining strict power and area constraints. Its role is particularly critical in applications where latency, power, and space are all highly constrained, such as autonomous vehicles, mobile devices, and embedded AI systems.
Why PCIe 5.0 Remains Relevant
At 32 GT/s per lane, PCIe 5.0 doubles the bandwidth of PCIe 4.0 while remaining backward-compatible with previous generations. Its maturity and interoperability make it a dependable choice for designers navigating complex, high-performance systems. PCIe 5.0 serves a diverse range of applications, from high-performance computing and data centers to mobile multimedia, consumer devices, and automotive Edge AI.
For automotive systems, latency-sensitive workloads demand PCIe 5.0’s high throughput, while consumer electronics often prioritize minimizing footprint and power. In data centers and HPC environments, designers focus on maximizing bandwidth and efficiency. PCIe 5.0 provides the flexibility to achieve the optimal tradeoff in each case, making it a practical, future-ready solution.
Design and Low-Power Techniques
One of the key themes of the webinar was low-power design, essential for both edge devices and energy-efficient HPC systems. PCIe 5.0 includes power states like P1.2, which reduces energy usage while maintaining responsiveness, and P1.2PG, which uses dynamic power gating to further minimize consumption, albeit with slightly longer transitions to active operation.
Channel length also influences performance. Shorter chip-to-chip and card-to-card channels reduce latency and improve signal integrity, enabling devices to fully exploit PCIe 5.0’s high-speed capabilities. Migration strategies from PCIe 4.0 illustrate the flexibility offered by PCIe 5.0: designers can choose to increase bandwidth while keeping area and power nearly constant, or reduce lanes and beachfront size to save area and energy without sacrificing throughput. These design options allow PCIe 5.0 to meet the highly variable requirements of modern AI and computing workloads.
Integration Considerations for Edge SoCs
Incorporating PCIe 5.0 into edge SoCs requires careful planning around cost, time-to-market, reliability, and readiness. The webinar highlighted how integration strategies, alongside careful design techniques, allow PCIe 5.0 to support demanding workloads efficiently. By optimizing lane configuration, channel length, and power management, designers can create systems that balance high bandwidth, low latency, and power efficiency, tailored to specific application domains.
Adoption and Real-World Use
PCIe 5.0 adoption has progressed steadily. The automotive market, in particular, has ramped up faster than others, driven by latency-critical AI workloads and strict reliability requirements. By the end of 2022, PCIe 5.0 was widely deployed in automotive applications. In high-performance computing, standard PCIe 5.0 continues to deliver maximum throughput, while low-power, short-reach variants are increasingly common in edge and embedded devices. Production-proven IP solutions, such as those from Synopsys, demonstrate broad interoperability and first-pass silicon success, proving that PCIe 5.0 is both mature and ready for next-generation AI applications.
Audience Questions: Key Insights
The Q&A session addressed several questions that clarified PCIe 5.0’s ongoing relevance. When asked why not skip directly to PCIe 6.0, the answer was clear: PCIe 6.0 requires major changes to PHYs and controllers, which increase area and power significantly. Adoption of PCIe 5.0 is already sufficient for the vast majority of use cases. Tradeoff decisions—whether to increase bandwidth while keeping area constant, or reduce area while maintaining bandwidth—depend entirely on the application. Standard PCIe 5.0 supports HPC workloads, while low-power, short-reach variants are increasingly deployed for edge and embedded systems.
Summary
PCIe 5.0 may have been released quite a few years ago, but it remains a critical enabler for Edge AI and high-performance applications. Its combination of maturity, interoperability, high bandwidth, and flexible design tradeoffs makes it a practical choice across markets, from automotive to consumer electronics and data centers. Far from being “old technology,” PCIe 5.0 allows designers to deliver high performance where it matters, while balancing power and area efficiently. For Edge AI, HPC, and embedded applications alike, PCIe 5.0 continues to be a versatile and reliable solution, helping to drive the next cycle of innovation.
Overview: Protecting ICs from costly ESD and latch-up failures
Electrostatic discharge (ESD) events cost the semiconductor industry an estimated $8 billion annually in lost productivity, warranty claims and product failures [1].
Ensuring the robust protection of integrated circuits (ICs) against various electrical phenomena, is a critical and often complex task in modern electronic design automation (EDA) verification, with even minor ESD incidents capable of triggering catastrophic latch-up events that can permanently damage sensitive components Preventing latch-up— a parasitic condition that can lead to device failure—is paramount, with guard rings playing a crucial role in its mitigation. ESD mitigation requires a multifaceted approach centered around robust guard ring implementation and comprehensive verification.
Different IC design companies employ diverse protection methodologies, design flows and verification tools, leading to potential inconsistencies. To establish a consistent, comprehensive and efficient verification flow for critical reliability aspects, the ESD Association (ESDA) provides recommended compliance checks. The Calibre PERC reliability platform from Siemens Digital Industries Software offers a suite of easy-to-use, pre-coded packaged checks for latch-up and the effective implementation of guard rings. This allows design companies to perform fast and efficient verification of ESD protections without the need to develop and maintain their own custom checks. By streamlining the design process. Calibre PERC helps design teams enhance overall device reliability. [4]
The pervasive threat of electrostatic discharge (ESD)
Electrostatic Discharge (ESD) is a rapid, uncontrolled transfer of static electricity between two objects at different electrical potentials. This static charge can accumulate on various surfaces or even human bodies through friction or induction. When a charged object comes into proximity or direct contact with a less charged or grounded object, the stored electrical energy discharges instantaneously, often generating thousands of volts and significant current pulses lasting only nanoseconds.
While static shocks are familiar phenomenon, in advanced manufacturing and electronic environments, ESD events pose a severe and costly threat. Even minor discharges can inflict critical damage on highly sensitive IC components. This damage can manifest in several ways:
Immediate catastrophic failure, where the device ceases to function
Latent damage, which may not cause immediate malfunction but degrades performance over time, leading to premature field failures
Parametric shifts, altering device characteristics without complete failure
Common failure mechanisms include gate oxide breakdown due to high electric fields, junction damage from excessive current and metallization burnout caused by localized heating. Such incidents directly translate into reduced manufacturing yields, increased warranty claims, costly product recalls, and significant financial losses for semiconductor companies. [3,6]
The challenges of latch-up
Complementing ESD as a paramount reliability concern in IC design is the phenomenon of latch-up. Latch-up refers to the inadvertent triggering of a parasitic Silicon Controlled Rectifier (SCR) structure inherent within the bulk CMOS (Complementary Metal-Oxide-Semiconductor) process. This parasitic SCR is formed by the interaction of adjacent p-n junctions, specifically the p-well, n-well, and substrate, creating a parasitic NPN-PNP bipolar transistor pair.
Under certain conditions, such as voltage transients, overvoltage events or current injection into input/output (I/O) pins, this parasitic SCR can be triggered into a low-impedance, high-current state. Once triggered, a positive feedback loop is established between the parasitic bipolar transistors, sustaining a large, uncontrolled current flow between the power supply and ground.
This sustained high current draw can lead to several severe consequences:
Complete functional failure of the circuit
Thermal runaway due to excessive heat generation
Permanent physical damage to the device (e.g., metal trace burnout, junction degradation)
Collapse of the system’s power supply.
Latch-up events can be initiated by various factors, including I/O overvoltage, power supply transients, or even an ESD event that injects sufficient current to trigger the parasitic structure. Once latch-up occurs, it is challenging to mitigate and typically requires the device to be powered off or physically reset to restore normal operation, highlighting the critical need for robust prevention mechanisms during the design phase.
Figure 1. The components of a latch-up event.
Latch-up prevention techniques
Latch-up prevention is a critical aspect of integrated circuit (IC) design, employing a multifaceted approach to mitigate the risks associated with parasitic current flow.
A cornerstone of latch-up prevention is the careful optimization of the IC layout. This involves strategic placement and spacing of components to inherently suppress the formation of parasitic thyristors—the PNPN structures responsible for latch-up. Central to this strategy is the implementation of guard rings—heavily doped regions strategically placed around sensitive transistors and circuit blocks.
Guard rings serve two key functions:
They absorb minority carriers, preventing them from reaching and activating the parasitic bipolar transistors that constitute the latch-up path.
They act as physical barriers, diverting excess current away from vulnerable areas and providing electrical isolation between different regions of the IC. [2]
This helps minimize unwanted interactions, maintain signal integrity, and enhance overall IC robustness by containing and dissipating potential trigger currents.
Beyond guard rings, other critical latch-up prevention techniques include:
Maintaining optimal spacing between p-wells and n-wells to physically increase the resistance of parasitic paths
Employing precise biasing techniques to control the substrate potential and keep parasitic elements in a non-conductive state [2]
The integration of robust ESD protection circuits also plays an indirect role by clamping and shunting transient overvoltages and overcurrents that could otherwise trigger latch-up.
Finally, advanced semiconductor processing techniques, such as using Silicon-On-Insulator (SOI) technology, significantly enhance latch-up immunity by providing intrinsic dielectric isolation between devices, dramatically reducing parasitic interactions and virtually eliminating bulk latch-up paths. Similarly, precise optimization of doping concentrations and profiles within the silicon substrate allows for better control over the electrical characteristics of parasitic elements, making them less prone to activation.
By integrating these comprehensive design and process techniques, IC designers can significantly minimize the risk of latch-up events, ensuring the reliable performance of integrated circuits across a wide spectrum of applications.
ESDA’s reliability guidelines for IC designers
ESD Association (ESDA) is a leading industry association dedicated to advancing the understanding, theory and practice of electrostatic discharge (ESD) avoidance. Recognizing the critical impact of ESD on IC reliability, the ESDA develops and publishes comprehensive guidelines, standards, and technical reports. These resources provide a standardized framework of design rules and corresponding compliance checks, serving as indispensable tools for both the electronic design automation (EDA) industry and the ESD design community. Their primary aim is to empower IC design teams to proactively protect their layouts from the damaging effects of ESD events and ensure overall device robustness. [2,3]
ESDA latch-up guard rings checks
Building upon these industry standards, EDA vendors strive to develop advanced verification solutions to address these critical reliability concerns. An example of such a solution is the Calibre PERC reliability platform from Siemens Digital Industries Software. This platform is designed to perform a range of complex design verification checks and can be integrated into existing design flows. It supports verification at various levels, including cell, block, and full-chip, and facilitates the implementation of reliability checks using both standard rules provided by foundries and custom rules defined by design teams.[5]
To effectively address these pervasive reliability threats, all potential sources of ESD and latch-up events within an IC design must be thoroughly evaluated and verified. In this context, Calibre PERC specifically addresses latch-up prevention by incorporating latch-up guard rings packaged check. This check support various critical verification aspects, encompassing 14 distinct checks, shown in figure 2, further categorized into five key areas:
Check guard ring existence
Check guard ring width
Check max spacing between Guard rings
Check victims in aggressor’s danger zone
Check guard rings connectivity
Figure 2. Latch-up guard rings checks.
By enabling the early identification and resolution of potential latch-up issues during the design phase, these advanced checks significantly reduce time-to-market for microelectronics designers and producers. This proactive approach prevents costly post-production failures, thereby improving yield, enhancing device reliability and compliance, minimizing field failures, and streamlining design iterations for faster, more efficient product development.
Guard rings existence checks
Verifying the existence of guard rings in a design is critical because these structures serve as a primary protective measure against latch-up phenomena in CMOS and mixed-signal circuits. Guard rings act as barriers that prevent injected minority carriers—generated during transient events, such as voltage spikes or substrate noise—from reaching sensitive device junctions and triggering parasitic thyristor paths. Without the presence of guard rings, the circuit is left exposed to increased risk of latch-up, which can lead to excessive current flow, functional failure, or even permanent damage. Therefore, confirming that guard rings are present wherever needed ensures that the foundational layer of latch-up protection is robustly in place. These rules verify the existence of the four types of guard rings (GR) illustrated in figure 3. The checks ensure that:
1st P type GR must enclose N+ aggressor
1st N type GR must enclose P+ aggressor
2nd P type GR must enclose P+ aggressor
2nd N type GR must enclose N+ aggressor
Guard rings’ width checks
The width of a guard ring strongly influences its ability to intercept and collect stray charge carriers before they reach vulnerable regions of the integrated circuit. If the guard ring is too narrow, it may not fully encompass the region it is supposed to protect, allowing some injected carriers to bypass the barrier and trigger latch-up. Adequate ring width ensures a greater area for carrier collection and improves the effectiveness of the ring as a protective shield. By rigorously checking that guard ring widths adhere to design rules and process requirements, engineers can significantly reduce the risk of latch-up and enhance the reliability and longevity of the chip.
The checks cover:
Width of P type Guard rings
Width of N type Guard rings
Guard rings spacing checks
The spacing between adjacent guard rings and aggressors plays a vital role in maintaining continuous protection across the chip. If guard rings are spaced too far apart, gaps appear in the protective network, leaving certain regions susceptible to carrier migration and latch-up initiation. Carefully monitoring and enforcing the maximum allowable spacing ensures full coverage of critical areas, creating a seamless defense system that blocks potential latch-up pathways. These checks help eliminate weak points in the design and boosts overall device robustness by maintaining the integrity of the guard ring network.
The checks cover:
max spacing between P type aggressor and 1st N type guard ring
max spacing between 1st N type guard ring and 2nd P type guard ring
max spacing between N type aggressor and 1st P type guard ring
max spacing between 1st P type guard ring and 2nd N type guard ring
Aggressor’s danger zone checks
Sensitive components, referred to as “victims,” located near regions with high-current drive or frequent switching activities—known as “aggressors”—are at particular risk for latch-up. In these danger zones, increased noise and carrier injection elevate the probability of parasitic conduction. By identifying and analyzing potential victims within these aggressive regions, engineers can prioritize additional guard ring protection and optimize layout strategies to mitigate risk. This targeted approach greatly enhances the effectiveness of latch-up prevention by focusing resources and attention on the most vulnerable spots within the circuit by check the non-protected victims in an aggressor’s danger zone, where the danger zone is marked by drawing a radius around the aggressors, as illustrated in figure 4.
The checks cover:
max spacing between P type aggressor and 1st N type guard ring
max spacing between 1st N type guard ring and 2nd P type guard
Figure 4. The victims in an aggressor’s danger zone.
Guard rings connectivity checks
Proper guard ring connectivity is essential to ensure that these protective structures are electrically functional and capable of steering excess charge to a safe potential, typically ground or VSS. If guard rings are not correctly tied to the designated bias, their ability to collect and divert injected carriers is compromised, undermining latch-up prevention. Connectivity checks involve confirming robust electrical contact and continuity through all relevant routes and layers. Ensuring reliable guard ring connections fortifies the overall defense against latch-up, preserving the operational integrity and safety of the integrated circuit throughout its lifecycle.
The checks cover:
N type Guard rings not connected to VDD.
P type Guard rings not connected to VSS
Simplifying ESD check implementation with packaged checks
However, the mere availability of ESDA checks is only the initial step; designers often face challenges in effectively setting up and executing these checks within their specific environments. To significantly simplify and standardize the application of ESDA guidelines, Electronic Design Automation (EDA) companies, such as Siemens EDA, encapsulate these checks into pre-coded, packaged solutions. These readily deployable checks can be seamlessly integrated into a design team’s existing reliability verification flow, eliminating the need for manually coded checks and the associated complexities. Designers can embed these Calibre PERC reliability checks directly into their current design flows, leveraging the integrated Calibre platform for comprehensive cell, block, and full-chip verification. This approach, which brings together rules coded in both standard verification rule format (SVRF) and Tcl-based Tcl verification format (TVF), provides designers with the flexibility and adaptability needed to meet evolving design requirements while ensuring compatibility across all major foundries. Furthermore, to provide consistent and accurate coverage of the ESDA rules, the Calibre PERC platform includes packaged checks tailored for each of the four ESD coverage categories, allowing designers to invoke them with either default parameters or customized modifications.[4]
Results debugging
Design teams can run any combination of Calibre PERC latch-up guard rings packaged checks, then analyze and debug the results using the Calibre RVE results viewer, as shown in figure 5.
These checks are accompanied by a comprehensive debug database, designed to facilitate the rapid identification and resolution of violations. Designers can effectively pinpoint issues by highlighting the results and debugging layers directly within the Calibre RVE. This visual approach streamlines the debugging process, as illustrated in the accompanying figure 6.[4]
Conclusion: Packaged ESD checks improve reliability and time-to-market
Electrostatic discharge (ESD) and latch-up verification using Electronic Design Automation (EDA) tools presents a significant challenge due to the varied protection approaches and diverse verification tools employed across integrated circuit (IC) companies. This paper has provided an overview of latch-up events, detailed effective prevention techniques, and illustrated how specific verification checks integrate into typical IC product and IP development flows. Focusing on the critical role of guard rings in robust latch-up protection, we introduced the Calibre PERC ESDA latch-up packaged checks. This innovative solution offers a user-friendly and efficient method to apply ESDA guidelines swiftly and accurately, enabling comprehensive latch-up verification across any technology node. By leveraging these Calibre PERC packaged ESDA latch-up checks, designers can achieve rapid and precise reliability verification, thereby significantly reducing time-to-market. [3]
The global semiconductor industry stands at a defining moment in its history. Having surpassed $600 billion in annual revenue, the path to a $1 trillion market is no longer a distant dream but an achievable milestone within the next decade. The annual 2025 Semi Industry Forum, organized by Silicon Catalyst, brings together the brightest minds and most influential players in the field to explore how this vision can become reality. More than a conference, the event serves as a collaborative platform where technologists, investors, and policymakers align on strategies to drive the next phase of semiconductor growth.
Silicon Catalyst has earned its reputation as the world’s leading incubator for semiconductor startups. Its mission to accelerate innovation by providing resources, mentorship, and access to a vast ecosystem of partners makes it uniquely positioned to guide the conversation toward sustainable industry expansion. The 2025 Forum, hosted at the Computer History Museum in Mountain View, California, focuses on the theme “On the Road to a $1 Trillion Industry.” This theme reflects both ambition and urgency: the semiconductor sector must evolve not only through technology scaling but also through business model reinvention, supply chain resilience, and new market frontiers such as artificial intelligence, automotive, and energy systems.
David French, Board Member, Silicon Catalyst. Ann Kelleher, Executive VP and GM Technology Development, Intel (retired). Ravi Subramanian, Chief Product Management Officer at Synopsys. Ralph Wittig, Corporate Fellow, CVP Head of Research & Advanced Development, AMD.
Reaching the trillion dollar mark will require more than continued demand for smartphones and data centers. The explosion of AI workloads, autonomous systems, advanced connectivity, and cloud-to-edge computing is driving unprecedented silicon consumption. Yet, this growth introduces formidable challenges. The cost of building leading-edge fabs now exceeds $20 billion and design complexity has risen exponentially. At the same time, global supply chains remain vulnerable to geopolitical friction and resource constraints. The Forum’s discussions aim to confront these realities head-on, proposing frameworks for collaboration between governments and industry to secure materials, expand talent pipelines, and sustain research at every node of the semiconductor value chain.
One defining characteristic of the Silicon Catalyst Forum is its commitment to integrating startups into the broader ecosystem. While large foundries and integrated device manufacturers dominate production capacity, innovation often originates from small, agile ventures exploring new architectures, sensors, and packaging technologies. By connecting these young companies with investors and strategic partners, the Forum creates pathways for disruptive ideas to scale a crucial ingredient in maintaining the industry’s momentum toward trillion-dollar valuation.
Equally significant is the Forum’s focus on sustainability and energy efficiency. As chips become more powerful, their energy footprint grows, posing environmental and economic challenges. The discussions emphasize the need for greener fabrication processes, smarter power management, and circular supply chains that minimize waste. These are not side issues but central to ensuring that semiconductor growth remains viable and responsible.
Bottom line: The 2025 Semi Industry Forum serves as both a reflection and a roadmap for the semiconductor world. It reflects an industry that has matured into a cornerstone of the global economy and a roadmap pointing toward the next stage of innovation and cooperation. If the conversations held at this year’s Forum translate into coordinated action bridging startups and giants, aligning technology and policy the trillion-dollar milestone will not be a question of if, but when. The Forum stands as a symbol of that collective determination: a gathering where the future of silicon is not merely discussed, but designed.
The U.S. House Select Committee on the Strategic Competition Between the United States and the Chinese Communist Party released a bombshell report titled “Selling the Forges of the Future” on October 7, 2025, detailing how the People’s Republic of China is stockpiling semiconductor manufacturing equipment from leading Western companies to fuel its military and technological ambitions. The investigation scrutinizes five dominant “Toolmakers” U.S.-based Applied Materials, Lam Research, and KLA; Dutch firm ASML; and Japan’s Tokyo Electron which control 80-85% of the global SME market. These tools are essential for producing advanced (≤16/14nm logic), foundational (16/14-40nm), and legacy (>40nm) chips used in everything from AI systems to weapons.
An ASML EUV lithography machine, a critical tool in advanced chip production, which the report highlights as being sold to China despite export controls.
The report’s key findings reveal alarming trends. In fiscal year 2024, the PRC spent $38 billion on Toolmakers’ products and services, accounting for 39% of their aggregate worldwide revenue—a 66% increase from 2022 and a 56% rise in market share. This surge occurred despite U.S. Bureau of Industry and Security export controls, which have gaps allowing sales of “node-agnostic” SME. Notably, restricted PRC entities, on the Entity List, NS-CMIC List, or DoD’s 1260H List, were top customers. Five such firms, including Semiconductor Manufacturing International Corporation (SMIC), Yangtze Memory Technologies Co., and Huawei affiliates like SwaySure and Shenzhen Pengxinxu, ranked in the top 30 for all Toolmakers from 2022-2024.
SMIC, China’s national chip champion, produces 7nm chips for Huawei’s AI processors, while YMTC supplies NAND memory for PLA weapons and surveillance tech like Hikvision cameras used in Uyghur repression. Sales to restricted entities comprised 45% of combined 2022-2024 PRC revenue for four Toolmakers. Non-U.S. firms ASML and Tokyo Electron saw revenues from these entities triple, selling $4.21 billion in 2024 alone, while U.S. Toolmakers’ sales dropped 56% to $786 million due to stricter controls. Lam Research derived a higher share (~4% of global revenue) from restricted sales and shifted $900 million to “substitute” entities later restricted in December 2024.
State-owned enterprises dominated, providing 69% of 2024 PRC revenue, with each Toolmaker doubling their SOE revenue share worldwide from 2022-2024. ASML sold 70% of its DUV immersion systems and 64% of dry systems to China in 2024, up sharply from prior years, enabling 7nm production. BIS granted permissive licenses to SMIC post-2020 Entity Listing, approving 110 of 196 applications for one Toolmaker.
The committee’s determinations underscore the risks: the CCP depends on foreign SME to advance “intelligentized” warfare, but entity-based controls fail against obfuscation, creating an unlevel field where non-U.S. Toolmakers profit billions from restricted sales. Country-wide bans only cover top-tier tools, allowing vast “non-advanced” inflows. With 69% SOE involvement, business with PRC chipmakers inherently aids CCP directives.
To counter this, the report offers nine recommendations: Align allied controls (I) via incentives; expand PRC-wide bans on advanced/foundational SME, including older DUV and 300mm wafer tools, using foreign direct product rules (FDPR) if allies lag (II); broaden restricted lists and prohibit allied sales with denial presumptions (III); prevent diversions through affiliate restrictions, end-user mandates, and tracking (IV); ban fabs mixing U.S./allied and Chinese SME via BIS/ICTS authorities, plus tariffs on PRC tools (V); restrict SME components with industry input (VI); boost BIS resources and hiring (VII); create whistleblower incentives (VIII); and support U.S./allied firms through training and talent attraction (IX).
A schematic of a semiconductor lithography system, illustrating the complex technology at the heart of the U.S.-China tech rivalry.
Bottom line: The report warns that unchecked sales accelerate China’s indigenization, backed by $100 billion+ in state funds, enabling self-sufficiency in AI chips like Huawei’s Ascend series (projected 200,000-800,000 units in 2025). Without swift action, the PRC could dominate semiconductors, eroding U.S. deterrence and enabling global authoritarianism. This bipartisan call urges closing loopholes to safeguard future tech leadership.
– First SEMICON in Arizona was great- should make it permanent
– Congress finally wakes up to China issues long after cows are gone
– Memory cycle in support of AI could be huge but scary at same time
– AI demand seems bottomless- but may distort chip industry dynamics
Phoenix SEMICON was wonderful!
The crowds and attendance were huge . Lots of good displays and a very energized crowd. The aisles were packed the first two days and calmed down on the third and final day.
The vibe was definitely better than the more recent SEMICON West shows held in San Francisco. It just felt better and more upbeat and not just because of the happy atmosphere in the industry but just overall nicer (maybe it was the weather)
We think that the move to Phoenix should be made permanent as it is certainly much more relevant when you are a short drive from both TSMC and Intel fabs.
Applied Materials kicks off first day of SEMICON with new products
Applied used the conference to announce three new products that all seem to be strong contenders.
The “Kinex” die to wafer bonding system which is critical to new packaging applications.
The “Xtera” EPI (epitaxial) system for void free epitaxial deposition, which harkens back to AMATs start in the industry decades ago with its first product being an EPI systems.
The third announcement was the PROVision E-Beam system which is clearly needed as the the industry gets down to low nanometer sized features.
We would point out the real winner behind the scenes is BESI , who are the real force behind the Kinex die to wafer bonding tool that AMAT is white labeling as their own. BESI gets the benefit of AMAT’s huge size pushing their product for them. But both companies obviously win.
We would also point out that the die to wafer bonding market is getting very crowded as we count at least 8 makers of similar technology. We would anticipate aggressive pricing in this area which is critical to multi-chip packaging.
Damning congressional report seems timed for maximum effect
We have been talking about the risks of selling China semiconductor equipment for over a decade now, far longer than any other analyst.
Congress is certainly way late to the game as the cows are long gone from the unlocked barn…but it is somewhat better late than never.
The report is quite damning as it chronicles what we have long known about the equipment industry profiting from the sales of tools that help the Chinese military against ourselves. As we have repeated “selling them the rope to hang us with” (Vladimir Lenin)
It mentions the top 5 players; AMAT, LRCX, KLAC, ASML and TEL
We think its going to be more difficult for the equipment players to up their tens of millions of dollars spent on K street lobbying firms in Washington DC to spread wealth around DC to keep export restrictions at bay. The report is direct , bi-partisan and hard to ignore and could prove embarrassing in a critical upcoming election cycle.
We have talked for many years about simply restricting any 300MM equipment from being exported to China. Anything short of that will have loopholes and work arounds and ways to skirt restrictions. All you need is a tape measure that can read 8 or 12 inches. It was somewhat interesting to see the congressional report finally talking about 300MM restrictions.
They obviously creates a further downside bias on sales to China which were already coming down. We would anticipate that we could see further downside revisions especially if current loopholes get closed. We think the majority of the negative impact will be on the named top 5 players. Second tier and smaller players will likely escape much of the scrutiny.
We also anticipate that China will try to slow their buying from the top 5 as they could get stuck with million dollar paperweights without service and spare parts.
We could be seeing the beginning of a super strong memory cycle driven by AI demand
We know very well what AI chip demand has done to the foundry business. A similar benefit is obviously underway on the memory side as well.
The recent 900K wafer starts/month deal between SK and OpenAI is beyond huge. Even if its only half that number its still huge…
We could see unprecedented ramp of memory capacity with the primary limiting factor being factory floor space.
AI is obviously memory hungry and a limiting factor.
While this could be great for the next couple of years as prices will remain high and equipment sales will be great the hangover after the party could also be devastating.
However, that’s too far in the future to care about now and the stocks won’t care either.
The stocks
The stocks have been on fire for quite some time and will likely need some cooling off and pull backs here and there as they are just so overheated.
Fighting the tape and positive news flow is pointless here.
We see no reason to sell or worse take a short position as you will only get crushed by the positive news.
Its best to just go along for the ride which seems to be quite thrilling right now.
We are still at the beginning of what could be one of the best up cycles the industry has ever seen. The upcycles just keep getting bigger and better……
PCs, the internet, mobile phones, now AI…..what’s next??? Quantum??? Maybe I’ll be retired by then……
About Semiconductor Advisors LLC
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specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies.
We have been covering the space longer and been involved with more transactions than any other financial professional in the space.
We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors.
We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.
Daniel is joined by Dr. Mark Burton, the General Chair for this year’s DVCon Europe. DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits.
Mark shares his long history of involvement in DVCon with Dan. He begins with a discussion of the importance of SystemC and the many diverse papers that will be presented at DVCon that illustrate the innovation it is spurring. He focuses on one application to automate the regulation of insulin in diabetics as an example of the impact these projects can have on the world around us.
He also discusses the concept of Federated Simulation, where diverse simulation models can be integrated and made available to a wide range of designers, creating a more efficient way to develop new technology. He explains that this work started at DVCon and Accelera now has a working group, Mark also discusses the impact open source is having on innovation. He explains that AI deployments based on open source typically have higher success rates. This work is also supported at DVCon.
Now that the dust has settled let’s talk more about TSMC’s Open Innovation Platform. Launched in 2008, OIP represents a groundbreaking collaborative model in the semiconductor industry. Unlike IDMs that controlled the entire supply chain, OIP fosters an “open horizontal” ecosystem uniting TSMC with EDA providers, IP developers, cloud partners, design centers, and value chain players. This network, now spanning over 100 partners, has invested trillions of dollars cumulatively to align around TSMC’s technology roadmap, enabling faster innovation and specialization. As of 2025, OIP continues to evolve with recent expansions like the 3DFabric Alliance accelerating 3D IC advancements for AI and HPC.
The ecosystem’s core strength lies in its comprehensive alliances: EDA Alliance for certified tools, IP Alliance for silicon-verified blocks, Cloud Alliance for scalable design environments, Design Center Alliance (DCA) for expert services, Value Chain Alliance (VCA) for backend support, and specialized groups like 3DFabric for advanced packaging. These components lower barriers, ensuring “first-time silicon success” and driving shared value. Below, we break down the primary benefits for customers (chip designers), partners, and the broader industry.
1. Accelerated Design and Time-to-Market
OIP drastically shortens the path from concept to production, addressing the semiconductor industry’s relentless pace. By integrating TSMC’s process technologies with partner tools and IP, it reduces design cycle times by providing pre-validated interfaces and flows.
For instance:
Cloud-Based Design: Through the Cloud Alliance (partners like AWS, Google Cloud, and Microsoft Azure), customers overcome in-house compute limits, enabling “design-in-the-cloud” for scalability and agility. This has cut time-to-market for complex chips by weeks to months.
AI-Assisted Flows: At the 2024-2025 OIP Forums, ecosystem demos showcased AI-optimized 2D/3D IC designs, boosting productivity for AI and 5G applications.
3D Innovation: The 3DFabric Alliance, launched in 2022, speeds silicon stacking and chiplet integration, as seen in AMD’s TSMC-SoIC-based CPUs, which achieved energy-efficient HPC breakthroughs.
Statistics highlight the impact: OIP has enabled over 1,800 chip tape-outs, with partners like Silicon Creations contributing to 1,000+ advanced-node designs. Testimonials from Synopsys emphasize how OIP’s multi-die tools deliver “powerful and efficient processing” for hyperscale computing.
2. Cost Reduction and Efficiency Gains
OIP minimizes financial risks by democratizing access to premium resources, allowing smaller firms to compete with giants.
Lower Barriers: Silicon-verified IP catalogs (the industry’s largest) and EDA certifications reduce R&D duplication, cutting development costs by up to 30-50% through reusable blocks like PLLs and SerDes.
Shared Investments: Ecosystem collaborations, backed by billions in annual spending, spread costs across partners. For example, Siemens EDA Calibre 3DThermal integration with TSMC processes provides thermal analysis without custom tooling.
Design Services: DCA and VCA offer outsourced expertise for testing and packaging, ideal for resource-constrained teams.
This efficiency has been pivotal for mobile and IoT innovations, where rapid prototyping via OIP’s Virtual Design Environment (launched 2018) avoids expensive iterations.
3. Enhanced Collaboration and Ecosystem Synergy
OIP’s “partner management portal” via TSMC-Online fosters seamless communication, turning competition into co-creation.
Supply Chain Alignment: Standardized interfaces (e.g., 3Dblox for chiplet packaging) ensure interoperability, as noted by Siemens EDA: “OIP has been pivotal to advancing certified flows.”
Global Forums: Annual events like the 2025 North America OIP Forum in Santa Clara unite 1,000+ attendees for multi-track sessions on AI, photonics, and RF, sparking real-time problem-solving.
Award-Winning Partnerships: 2025 honorees like Teradyne (for 3DFabric testing) and Silicon Creations (ninth straight Mixed-Signal IP award) exemplify how OIP drives mutual growth, with TSMC’s Aveek Sarkar praising their role in “energy-efficient AI chip innovation.”
4. Industry-Wide Innovation and Scalability
Beyond individual gains, OIP propels the sector forward by supporting emerging tech like 2nm nodes, UCIe standards, and silicon photonics. It has nurtured innovations in automotive, 5G, and edge AI, with partners like imec contributing R&D for low-volume prototyping. The result? A resilient ecosystem that shortens “time-to-revenue” while promoting sustainability through efficient designs.
Bottom line: TSMC’s OIP transforms semiconductor development from siloed efforts to a vibrant, collaborative powerhouse. As AI demands surge, its benefits of speed, savings, synergy, and scalability position it as indispensable, empowering innovators to outpace Moore’s Law. For deeper dives, explore TSMC’s OIP page and the most recent forum recap: TSMC’s Push for Energy-Efficient AI: Innovations in Logic and Packaging.
Artificial intelligence (AI) is transforming every layer of computing, from hyperscale data centers training trillion-parameter models to battery-powered edge devices performing real-time inference. Hardware requirements are escalating on every front: compute density is increasing, power budgets are tightening, and new algorithms arrive faster than traditional chip roadmaps can adapt.
The first wave of AI hardware was built on proprietary instruction sets and closed ecosystems. Those approaches are now straining under the pace of change. Designers need a way to innovate without constraints, to add custom acceleration where workloads demand it, and to build systems that scale from edge to cloud under a single software umbrella.
This is where RISC-V—an open, modular instruction set architecture—has moved from a promising alternative to a market imperative. The sections below show why the market is pivoting toward RISC-V, how it empowers next-generation AI chip designers, how AI-system builders can take advantage of it, and how companies like Akeana are converting opportunity into real silicon.
Why the Market Wants RISC-V
Global AI-processor revenues are expected to exceed $260 billion this year, but the diversity of AI workloads and the drive for energy efficiency expose the limits of fixed instruction sets such as x86 and Arm. RISC-V’s openness allows designers to integrate custom instructions—whether for matrix operations, tensor accelerators, or compute-in-memory features—without waiting for a single vendor to approve the roadmap.
RISC-V also provides greater flexibility and broader choice in IP availability, eliminating dependence on a single or limited number of sources, as is often the case with Arm or x86. For example, in multi-threaded processors within heterogeneous compute systems, if the incumbent supplier does not offer a solution, there may be no alternative available.
Governments and enterprises are drawn to the freedom from restrictive licensing. Hyperscalers and semiconductor companies see the chance to fine-tune performance per watt for a rapidly widening range of AI tasks. Together these factors create a powerful demand for hardware that is at once open, customizable, and future-proof.
How RISC-V Enables Next-Gen AI Chip Designers
For chip architects and product teams, RISC-V offers a blank canvas for differentiation. Its extensible ISA supports wide-vector units, matrix engines, and other domain-specific accelerators, all integrated within a coherent hardware–software stack.
Because the ecosystem is open and fast-moving, software support keeps pace with silicon. Open-source compilers, optimized libraries, and ratified vector and matrix extensions are ready when new chips arrive. Designers can focus on compute density, power efficiency, and time to market without sacrificing compatibility with industry-standard development tools.
How AI-System Builders Can Leverage RISC-V and Chip Designer Innovation
AI-system builders—whether they are assembling servers, edge devices, or specialized appliances—require platforms that merge heterogeneous compute resources without creating software silos. RISC-V’s unified ISA makes it possible to combine general-purpose CPUs with vector engines, general matrix-multiply (GEMM) accelerators, and customer-specific xPUs under a single software target.
This reduces integration complexity and ensures consistent performance across edge and data-center deployments. System architects can scale performance, tune energy efficiency, and incorporate custom accelerators while maintaining one toolchain and development flow, shortening the path from concept to production.
A Unique Window of Opportunity
The push for open, customizable AI hardware coincides with a moment when the RISC-V supply chain has reached maturity. Proven IP blocks, hardened design flows, and robust software stacks allow both chip vendors and system builders to move quickly from design to deployment.
Those who act now can capture customers looking for sovereignty and specialization while delivering next-generation AI performance that closed architectures may struggle to match. The alignment of market pull and technology readiness creates a rare but powerful window of opportunity.
What Akeana Offers
Akeana stands at the forefront of this movement with a full-stack portfolio of RISC-V–based IP and subsystems purpose-built for AI. In its recent webinar, “Leveraging RISC-V as a Unified Heterogeneous Hardware and Software Platform for Next-Gen AI Chips,” Akeana engineers described how SoC developers can meet aggressive compute-per-watt goals and heterogeneous system requirements using the company’s technology.
Akeana provides RVA23 compatible high-performance RISC-V processors, advanced vector and matrix accelerators, and powerful data-movement engines. Its flexible compute-subsystem interconnect links multi-core CPUs, partner accelerators, and custom hardware blocks into a seamless architecture. The company is uniquely able to deliver simultaneous multi-threaded (SMT) RVA23 compatible In-Order and Out-of-Order cores. The company also delivers a mature software environment—optimized compilers, AI performance libraries, and robust simulation tools—so developers can bring up operating systems and AI frameworks immediately.
For chip designers, these offerings shorten the path from concept to production while allowing fine-grained performance tuning. For AI-system builders, they provide ready-to-integrate compute subsystems that simplify scaling and reduce power consumption. Akeana’s technology enables customers to innovate aggressively while meeting stringent efficiency and time-to-market targets.
Summary
The AI industry is entering a new growth phase, and RISC-V is the architecture of choice for flexibility, efficiency, and long-term control. Chip designers gain freedom to create custom instructions and accelerators, while AI-system builders gain a unified platform for heterogeneous computing.
Akeana sits at the center of this transformation. By supplying RISC-V IP cores, powerful compute subsystems, and a complete software stack, the company helps both chip creators and system integrators capture the opportunity that today’s market demands. The combination of surging demand and a mature supply chain is compelling, and Akeana is ready to help partners seize it.
See Akeana at RISC-V Summit 2025
To experience Akeana’s innovations firsthand, visit them at Booth #P2 at the RISC-V Summit in Santa Clara, October 22–23, 2025. There you can explore live demonstrations of RVA23 cores that achieve Spec2K6/GHZ score >20, In-Order and Out-of-Order SMT cores, highly efficient data movement engine for sparse data and speak directly with their team about accelerating your own AI hardware and system designs.
RISC-V has emerged as a cornerstone of modern computing, offering an open-source alternative to proprietary designs like ARM and x86. Free from licensing fees and highly extensible, RISC-V powers everything from IoT devices to AI accelerators, with over 13 billion cores shipped globally. Annual RISC-V Summits, organized by RISC-V International, serve as vital hubs for innovation, fostering collaboration among engineers, academics, and industry leaders. In 2025, these events have spotlighted advancements in AI, automotive, and high-performance computing, with Andes Technology standing out as a key architect of the RISC-V ecosystem.
The year kicked off with the RISC-V Summit Europe in Paris (May 12-15), where attendees explored Europe’s burgeoning RISC-V landscape. Amid keynotes on industrial adoption and academic research, the summit emphasized single-track sessions blending invited talks, exhibitions, and hands-on demos. A highlight was the call for contributions, which prioritized topics like security frameworks and vector extensions, reflecting RISC-V’s push into edge AI.
Transitioning to Asia, the fifth RISC-V Summit China convened in Shanghai’s Zhangjiang Science Hall (July 16-19), focusing on supply chain integration and domestic innovation. With China’s massive semiconductor investments, sessions delved into scalable SoCs for 5G and smart manufacturing, underscoring RISC-V’s geopolitical resilience.
Expect deep dives into automotive-grade RISC-V, inspired by Infineon’s inaugural Automotive RISC-V Ecosystem Summit in July, which gathered stakeholders to tackle ISO 26262 compliance for ADAS systems. Collectively, these summits have accelerated ecosystem growth, with live demos of Linux-booting prototypes and certification initiatives ensuring interoperability.
Andes Technology, a founding Premier member of RISC-V International and a powerhouse in embedded CPU IP, hosts eight different activities this year including a keynote, talks, and poster sessions:
Since 2005, Andes has shipped billions of cores, blending proprietary AndeStar V5 enhancements with RISC-V compliance for optimal performance-per-watt. Their portfolio spans 32/64-bit processors: the D25F for low-power DSP tasks, the AX25MP for symmetric multiprocessing with L2 cache coherence, and the A25 for general-purpose efficiency. A standout is the NX27V, a 64-bit vector processor with a five-stage pipeline, tailored for AI workloads under the latest RISC-V specs.
Andes’ summit activities amplify their influence. At Europe 2025, they unveiled AI-centric demos, including RISC-V IP powering Meta’s accelerators and ASPEED’s 360-degree video processors—showcasing real-time spherical imaging for conferencing. In China, Andes collaborated with S2C on prototyping tools, accelerating SoC tape-outs. Their own Andes RISC-V CON series—debuting in Silicon Valley (April) and Seoul (September)—complements these, with sessions on security and application processors.
Looking ahead, Andes eyes the North America Summit for announcements on U.S.-designed high-performance cores via their Condor Computing arm, established for ultra-scalable IP with Linux emulation already validated and shipments imminent. Partnerships, like the tie-up with DeepComputing for QiLai SoCs featuring quad-core AX45MP clusters, further embed Andes in AI hardware.
Andes’ ethos democratizing compute through open standards mirrors RISC-V’s mission, driving adoption in EVs, data centers, and beyond. As summits evolve, expect Andes to lead on vectorized AI and secure extensions, propelling RISC-V toward trillion-core ubiquity. In an era of chip wars, these gatherings remind us: collaboration, not silos, fuels progress.
Bottom line: In my experience this conference is well attended, deep in content and provides excellent RISC-V networking opportunities. I hope to see you there, it would be a pleasure to meet you.
