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CEO Interview with Gopi Sirineni of Axiado

CEO Interview with Gopi Sirineni of Axiado
by Daniel Nenni on 12-21-2025 at 12:00 pm
Categories: AI, CEO Interviews

Gopi Sirineni Axiado

Gopi Sirineni is a Silicon Valley veteran with four startups and over 25 years of experience in the semiconductor, software and systems industries. As a senior executive, he has demonstrated exceptional skills in building highly efficient, cost-effective organizations, managing them in rapidly changing environments, and bringing industry-changing technologies to market.

Tell us about your company?

Axiado is a semiconductor company redefining the way modern platforms are secured and managed. We develop hardware-anchored security and control solutions that are designed specifically for the demands of today’s AI-driven infrastructure. Our mission is to stop cyberattacks at their earliest point: before they impact systems. By delivering platform security that begins at the silicon level, threats are identified instantly with our technology, platform reliability is strengthened, and organizations gain a scalable, future-proof foundation for secure compute.

What problems are you solving?

For years, the industry has depended almost entirely on software-only security at the port of entry. These tools work hard to filter threats, but once malware slips through, there is nothing left to stop an attack in progress. This gap leaves high-value infrastructure dangerously exposed. Axiado closes that gap with a hardware-based security architecture. Our Trusted Control/Compute Unit (TCU) Sits alongside the system hardware as a persistent, intelligent last line of defense. It collaborates with existing software solutions while independently detecting threats they may overlook. Inside the TCU, autonomous AI agents continuously analyze behavior against known attack patterns, enabling real-time detection before damage occurs. No other company currently offers AI-driven cybersecurity integrated directly into hardware in this way.

What application areas are your strongest?

Our strength lies in combining platform management, platform security, and hardware-resident AI. Some core focus areas include platform security and management control, data-center-grade infrastructure, especially AI infrastructure, and hardware-anchored AI agents that continuously monitor system behavior. In addition, we are in the process of strengthening our Dynamic Thermal Management (DTM) and Dynamic Voltage and Frequency Scaling (DVFS), which is driven by customized AI models. Because our AI agents operate beside the hardware, they can continuously learn normal behavior patterns, identify anomalies instantly, and act autonomously. Beyond security, these same agents improve system efficiency by reducing power consumption and optimizing thermal and performance characteristics in real time.

What keeps your customers up at night?

CISOs and infrastructure leaders worry most about zero-day threats, which are attacks that slip past software defenses and act invisibly until it is too late. Today’s data centers rely heavily on software-based port-of-entry tools that are unable to see what happens once malware bypasses them. Our customers want a trusted, proactive way to predict, detect, and stop these attacks before they unfold. Axiado’s hardware-level AI learning provides exactly that: we monitor systems continuously, learn their patterns, flag deviations instantly, and identify active attacks in real time. Today, we are the only solution in the market capable of detecting attacks as they are happening at the hardware layer.

What does the competitive landscape look like and how do you differentiate?

Axiado does not have any direct competitors building a unified hardware security and platform management architecture. Legacy solutions are currently fragmented, with one piece for management, another partial add-on for boot-time security, and none built with holistic AI-driven protection in mind. Axiado’s solution is different because it is architected from the ground up with security baked in, not bolted on. We have reimagined platform control, efficiency, and end-to-end protection to work together as a single silicon-anchored system. This integration, coupled with hardware-resident AI agents, sets us apart from any legacy or discrete offerings on the market.

What new features/technology are you working on?

We are expanding our autonomous AI agent framework, enabling even more intelligent detection, efficiency tuning, and infrastructure automations. Some of these new capabilities include various advanced AI agents, enhanced Dynamic Voltage and Frequency Scaling (DVFS, next-generation Dynamic Thermal Management (DTM), and continued growth of our hardware-anchored AI compute environment. These innovations strengthen both the security posture and operational efficiency of modern compute infrastructure.

How do customers normally engage with your company?

Customers typically reach us through our website, direct outreach from our sales team, and in-person discussions at industry events. We actively participate in major conferences and trade shows, such as SC25, AI Infra Summit, and OCP Global, where we have seen strong engagement from enterprises, hyperscalers and ecosystem partners. From there, we work closely with customers to integrate our hardware, software stack, and APIs into their existing platforms.

Also Read:

CEO Interview with Masha Petrova of Nullspace

CEO Interview with Eelko Brinkhoff of PhotonDelta

CEO Interview with Pere Llimós Muntal of Skycore Semiconductors

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Google’s Road Trip to RISC-V at Warehouse Scale: Insights from Google’s Martin Dixon

Google’s Road Trip to RISC-V at Warehouse Scale: Insights from Google’s Martin Dixon
by Daniel Nenni on 12-21-2025 at 10:00 am
Categories: Events, IP, RISC-V

Google RISC V in Datacenter 2025

In an engaging presentation at a recent RISC-V summit, Martin Dixon, Google’s Director of Data Center Performance Engineering, took the audience on a metaphorical “road trip” to explore the company’s vision for integrating RISC-V into its massive warehouse-scale computing infrastructure. Drawing parallels from Google’s successful transition to ARM-based servers, Dixon outlined the opportunities, challenges, and necessary ingredients for bringing RISC-V to data center scale.

Google’s journey with heterogeneous computing began with its roots in commodity x86 platforms, celebrating its 27th birthday amid evolving needs. In the mid-2010s, the company began experimenting with ARM architectures, following the 2014 ARM server specification. This led to the 2022 launch of Tau T2A ARM instances and, more recently, the custom Axion ARM-based processors. Today, Google’s data centers already mix x86, ARM, and emerging architectures, including early RISC-V components. Dixon emphasized that heterogeneity and specialization are essential to overcoming the slowdown in Moore’s Law, enabling greater efficiency and performance at scale.

RISC-V’s openness and customization potential make it exciting, but Dixon cautioned it’s a “double-edged sword” without standards. He highlighted the need for baselines like the RVA23 profile and an upcoming RISC-V server platform specification to ensure compatibility for warehouse-scale deployment.

Using the road trip analogy, Dixon outlined key “ingredients” for success:
  • A roadmap — Standardized specifications with mandatory features like branch recording (similar to Intel’s LBR or ARM’s BRBE), side-channel-hardened crypto, and MMU support for security.
  • A cool car — High-performance server-class SoCs with at least 64 cores and support for 4GB+ memory per core, prioritizing performance, reliability, and maintainability.
  • Beyoncé — A humorous nod to Google’s internal “Beyoncé Rule” (from Beyoncé’s “Single Ladies”: “If you liked it, then you shoulda put a test on it”). Dixon stressed that critical functionality must have comprehensive tests to ease multi-architecture porting.
  • Friends — Strong community collaboration for a robust software ecosystem that “compiles and runs out of the box.”

Reflecting on lessons from porting to ARM, Dixon shared that Google’s top workloads (including YouTube, Spanner, BigQuery) represent nearly half its compute. Porting isn’t just about big services—schedulers require a mix of large and small jobs for efficient packing. Google ported over 30,000 packages via central efforts, automation, and AI-generated changes, enabling self-service for the long tail of workloads.

Developers’ fears about toolchain breakage proved unfounded; issues were mostly “boring” like config files, build paths, and flaky tests. Rare potholes included floating-point precision differences (resolved by standardizing to float128) and minimal memory ordering bugs. Overall, the transition was smoother than expected.

Looking ahead, Google is collaborating via RISC-V International on standards like QoS and RVA23, and as a founding RISE member, accelerating upstream work on Linux and LLVM. To “autopilot” the process, Google applied its Gemini AI model to 40,000 ARM porting edits, categorizing them to automate future changes. An AI agent now handles safe, gradual rollouts, often unnoticed by teams.

For RISC-V, Dixon called for ratifying server specs, delivering capable SoCs, expanding test coverage, and embracing AI. Google, with RISE and RISC-V International, is funding academics with Gemini credits to advance AI-driven porting.

Dixon closed optimistically, quoting Jack Kerouac: let’s “lean forward to the next venture” with RISC-V at warehouse scale. His talk underscores Google’s commitment to open architectures, positioning RISC-V as a key pillar in the future of hyperscale computing.

Also Read:

Bridging Embedded and Cloud Worlds: AWS Solutions for RISC-V Development

The RISC-V Revolution: Insights from the 2025 Summits and Andes Technology’s Pivotal Role

Podcast EP309: The State of RISC-V and the Upcoming RISC-V Summit with Andrea Gallo

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Bridging Embedded and Cloud Worlds: AWS Solutions for RISC-V Development

Bridging Embedded and Cloud Worlds: AWS Solutions for RISC-V Development
by Daniel Nenni on 12-21-2025 at 6:00 am
Categories: Events, IP, RISC-V

AWS RISC V Summit 2025 SemiWiki

In a compelling keynote at the RISC-V Summit North America 2025, Jeremy Dahan from AWS explored the challenges of embedded systems development and how cloud technologies can bridge the gap between local hardware tinkering and scalable, shareable environments. Drawing from his experience as an engineer, Dahan highlighted the desire for desktop-accessible hardware for rapid prototyping, contrasted with the difficulties of sharing setups across teams, suppliers, and global collaborators. The cloud’s infinite compute and easy accessibility offer a solution, and AWS is positioned to combine these worlds for RISC-V developers.

Dahan framed virtualization as a key enabler, but one requiring a balance between time, cost, and performance accuracy. Over-investing in high-fidelity models can delay projects, while insufficient accuracy hinders progress. AWS addresses this through curated tools, partner solutions, and guidance to accelerate hardware-software co-development from initial models to real ECUs.

A standout example is the “virtual engine experience,” a cloud-based portal providing unified access to development tools. Users log in with credentials tied to Git repositories, accessing a consistent environment with pre-installed, RISC-V-supported tools from partners. This eliminates “it works on my machine” issues, speeds onboarding (from weeks to one day), and ensures version uniformity across teams, suppliers, and customers.

Dahan showcased partnerships, highlighting a recent two-hour workshop with ChipInvent demonstrating cloud-based EDA tools for rapid RISC-V design creation, something impractical with traditional setups.

Delving deeper into virtualization levels (referencing Synopsys slides), Dahan explained the spectrum from abstract models (fast but low accuracy) to real hardware (accurate but hard to scale). Engineers prefer the right side for confidence, but cloud shifts this leftward without sacrificing too much fidelity. Notably, 90% of Hardware-in-the-Loop (HIL) testing can shift to Software-in-the-Loop (SIL), avoiding procurement delays, power/cooling needs, and maintenance of physical farms.

For RISC-V, where native execution isn’t directly available like on ARM Graviton instances, AWS leverages FPGA acceleration. EC2 F1/F2 instances (with AMD Xilinx UltraScale+ FPGAs) provide scalable access to FPGA-based prototypes, marrying desktop board benefits with cloud sharing.

Developers use pre-packaged tools like Vitis and OpenCL, integrate custom IP, and generate Amazon FPGA Images (AFIs) snapshottable, shareable, and marketplace-listable. IP remains protected, enabling monetization (free, paid, or BYOL). Smaller RISC-V IP providers gain broader reach without field engineers troubleshooting physical boards. A workshop used an RV35I core this way for quick starts.

For remaining real-hardware needs, AWS Outposts bring data-center servers on-premises, connectable to custom boards (e.g., Infinitrial or user-specific for IO testing). Secure remote access allows suppliers/customers to debug without travel, scaling to multiple boards.

Hybrid setups connect on-prem HIL farms to cloud via Direct Connect for low-latency, with EKS Hybrid Nodes orchestrating workloads across emulation, FPGA, and physical hardware under one control plane.

Dahan concluded that AWS reconciles embedded and cloud paradigms, letting developers focus on IP while managed services handle infrastructure. Calls to action included workshops for FPGA development, Marketplace listing guidance, and EDA scaling solutions. AWS hosts meetups in Santa Clara for hands-on tinkering and demos.

Bottom line: This talk underscores AWS’s commitment to RISC-V, making high-fidelity, collaborative development accessible and scalable—transform local prototypes into globally shareable assets.

Also Read:

The RISC-V Revolution: Insights from the 2025 Summits and Andes Technology’s Pivotal Role

Podcast EP309: The State of RISC-V and the Upcoming RISC-V Summit with Andrea Gallo

Yuning Liang’s Painstaking Push to Make the RISC-V PC a Reality

Podcast EP323: How to Address the Challenges of 3DIC Design with John Ferguson

Podcast EP323: How to Address the Challenges of 3DIC Design with John Ferguson
by Daniel Nenni on 12-19-2025 at 10:00 am

Daniel is joined by John Ferguson, senior director of product management for the Calibre products in the 3DIC space at Siemens EDA. He manages the vision and product offerings in the Calibre domain for 3DIC design solutions.

Dan explores the challenges of 3DIC and chiplet-based design with John, who describes the broad range of tools Siemens offers to address these challenges. John focuses on thermal, power and mechanical stress as three key aspects of advanced designs that must be carefully analyzed and optimized early. He explains how Calibre’s knowledge of the design forms the foundation for much of this work, with the addition of technologies such as multiphysics analysis to expand the scope.

John describes many real word scenarios for 3DIC design that require additional focus and the consequences of not getting it right. He also comments on the benefits of AI for advanced design flows.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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How vHelm Delivers an Optimized Clock Network

How vHelm Delivers an Optimized Clock Network
by Mike Gianfagna on 12-19-2025 at 6:00 am
Categories: ClockEdge, EDA

How vHelm Delivers an Optimized Clock Network

In a prior post, I discussed how the clock is no longer just another signal at advanced nodes. Indeed, it is the most critical network on the chip. An optimized clock network can be the margin of victory for your next design. But extracting these benefits is challenging. The clock network is quite sensitive, and optimization can come down to finding a few picoseconds buried deep inside the design. ClockEdge has built a pioneering suite of tools to address these challenges.

I discussed the four elements of the ClockEdge Veridian platform in the prior post mentioned above. Timing, power, aging and jitter are all part of the solution. But integrating the massive information associated with these elements of the design to find the right balance is another hurdle. This is where the command center for the Veridian platform takes over, providing the required integrated perspective. Let’s examine how vHelm delivers an optimized clock network.

Unlocking Insights with a Shift-Left Strategy

Thanks to SPICE-accurate visibility and fast virtual ECO loops, clock optimization can now be done early with a shift-left approach. Moving clock optimization from a late-stage emergency to an early-stage process that improves PPA across the entire design can produce a substantial positive impact for any design team.

The full-network SPICE accuracy delivered by Veridian reveals timing distortion, duty cycle imbalance, jitter sensitivity, and aging drift that corner-based STA approaches fail to capture. There are many positive impacts as a result. Here are a few:

    • Early visibility into dynamic timing behavior. SPICE-accurate timing analysis exposes real rail-to-rail behavior, including degraded swing, coupling-driven distortion, and asymmetric PVT effects that STA routinely smooths over.
    • Jitter understanding, when it matters most. Clock jitter at advanced nodes is dominated by power delivery network (PDN) noise. Gate switching currents, bump-level voltage droop, and multi-domain noise profiles create sub-picosecond accurate jitter that only transient simulation can reveal.
    • Early power optimization. Clock networks consume a large share of total power. With a virtual ECO, designers can tune buffers, topologies, and sizing while there is still room to make changes without impacting the schedule.
    • Lower sign-off risk. Once early optimization is in place, sign-off stops being a hunt for surprises. Design teams arrive at the final stage with fewer iterations, tighter margins, and higher confidence.

vHelm Puts it All Together

What makes vHelm different? Here are a few examples:

Sign-off grade accuracy, available early: The Veridian platform traces the full clock network, generates a SPICE netlist, and runs transient simulation fast with patented technology that can scale to millions of gates..

Virtual ECO enables rapid iteration: Change a constraint, resize a buffer, or adjust topology and see the SPICE-accurate impact across the clock network. This replaces the slow trial-and-error cycle of late-stage ECOs with a tight optimization loop that actually fits the schedule.

One interface. One flow. One source of truth.

vHelm consolidates:

  • Timing visualization
  • Jitter margins
  • Power consumption
  • Rail-to-rail behavior
  • Aging impact

No patchwork of point tools or stitched-together STA, simulators, and debug utilities.. It is a unified flow by design.

Designed for early leverage, not late rescue: The goal is not just catching issues. It is reshaping architecture, buffering strategy, and margin allocation at a time when these choices still influence PPA.

And here are some reasons why early optimization directly improves sign-off:

Fewer surprises: Teams that shift left find that sign-off paths often validate changes, not expose them.

Tighter PPA: With accurate SPICE insights, designers remove unnecessary guard-bands and reclaim performance or power margin without increasing risk. 

Higher reliability over product lifetime: Aging-aware analysis reveals long-term drift in edge behavior. Fixing these issues early prevents latent field failures and improves yield.

Measurable schedule predictability: Virtual ECO replaces uncertainty with controlled iteration.

I have just touched on a few of the many capabilities vHelm offers design teams for early clock network optimization. Below is a screen shot of the interface, illustrating the many parameters on the left that vHelm is tracking and some of the analysis that can be applied to these parameters on the right to find the right path to an optimal clock network.

To Learn More

What is becoming clear is this: advanced-node clocks cannot be modeled accurately enough with abstractions alone. Teams can either continue treating accuracy as something addressed at the end or use it as an opportunity at the start of the design.

vHelm exists for teams who choose the second path. If you are responsible for clocking in an advanced SoC, vHelm can help to answer one question: how much margin am I leaving on the table? You can learn more about the ClockEdge Veridian platform and the impact of vHelm here.  And that’s how vHelm delivers an optimized clock network.

Also Read:

ClockEdge Delivers Precision, Visibility and Control for Advanced Node Clock Networks

CISCO ASIC Success with Synopsys SLM IPs

RISC-V: Powering the Era of Intelligent General Computing

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CEO Interview with Masha Petrova of Nullspace

CEO Interview with Masha Petrova of Nullspace
by Daniel Nenni on 12-18-2025 at 2:00 pm
Categories: CEO Interviews

Masha Headshot

Dr. Masha Petrova is CEO and co-founder of Nullspace Inc., a venture-backed company developing next-generation electromagnetic simulation software for RF and quantum computing applications. She brings 25 years of engineering software experience from executive roles at MSC Software, Altium, and Ansys, and several computational software start-ups. Dr. Petrova holds a Ph.D. in Aerospace Engineering from UC San Diego and a B.S. in Mechanical Engineering from the University of Delaware.

What is Nullspace?

Nullspace is rebuilding electromagnetic simulation from the ground up to handle the scale and complexity of modern RF systems. Nullspace makes software that helps engineers design and validate these systems, from satellite constellations and advanced platforms to 5G infrastructure and quantum computing hardware.

The core challenge Nullspace is addressing is that the simulation tools engineers have relied on for decades are 40+ years old and were created before parallel computing architecture even existed. These legacy tools were not built for modern computing.

As RF systems have grown exponentially more complex with dozens of antennas, phased array systems, or massive MIMO configurations, these legacy tools often crash or take weeks, or even months, to run when used on real-world applications that require highly-accurate physics simulations.

Nullspace has built a solver architecture to take full advantage of parallel computing, along with both CPU and GPU acceleration combined with a proprietary compression algorithm, delivering up to 25x faster performance for simulations that typically overwhelm traditional tools.

Nullspace was incubated inside a U.S. defense contractor for over a decade, where the technology was validated on mission-critical DoD products. The company spun out three years ago to bring this defense-grade reliability to commercial markets. The Python API architecture also uniquely positions Nullspace for AI-driven optimization workflows, not AI replacing physics, but AI automating the iterative design process.

What problems is Nullspace solving?

The fundamental problem is that legacy electromagnetic solvers can’t handle the scale and complexity of modern RF systems. Engineers consistently tell Nullspace their simulations run for two weeks, then crash before delivering results. When facing a satellite launch deadline or program milestone, these failures create significant bottlenecks that put entire projects at risk.

Legacy tools force engineers to oversimplify their designs just to get something that runs. For example, simulating entire RF systems like a complex network of antennas on a spacecraft, or a phased array installed on a platform, is beyond the capability of these tools. Engineers have to break up these problems into pieces, simulate each separately, and then integrate the results, which creates loss of accuracy and increases design risk.

Nullspace solves this by enabling engineers to simulate full RF system designs accurately and significantly faster. Nullspace employs a full-fidelity 3D physics solver based on the Method of Moments that combines CPU and GPU acceleration with a proprietary compression algorithm to deliver fast results without loss of accuracy. This means faster iteration, fewer prototype spins, and the ability to validate designs that were previously impossible to simulate.

Where does Nullspace excel?

Nullspace excels in three key areas that share a common thread: complex electromagnetic and electrostatic challenges in advanced, next-generation systems that push the boundaries of traditional simulation.

Defense, aerospace, and communications industries: This is Nullspace’s area of expertise, including antenna placement and co-site analysis, radar cross-section analysis, and complex phased-array design. Nullspace software can handle electrically large problems that overwhelm legacy tools, simulating entire RF systems of a spacecraft or aircraft with all antennas interacting, a capability that sets the company apart.

Wireless infrastructure: 5G systems, phased array antennas, and next-generation communication networks. As companies pack more antennas into smaller spaces with more frequency bands, electromagnetic interference becomes critical. While legacy tools take weeks for these simulations, Nullspace can deliver results in hours or days.

Quantum computing hardware: Nullspace also develops the world’s only commercial electrostatic solver for extremely large-scale, rapid, and accurate design and analysis of structures that support modern quantum computers and particle accelerators. Leading quantum computing companies rely on Nullspace because it’s the only commercial solver capable of handling large-scale ion traps. Nullspace technology has powered multiple quantum computing world records.

What challenges were engineers facing before Nullspace?

Three challenges consistently come up in conversations with customers.

First is simulation reliability on tight deadlines. When tools fail after extended runtime with a critical deliverable approaching, teams face serious project risks and need dependable, fast solutions they can count on.

Second is the growing complexity of modern RF systems. Today’s satellites carry dozens of antennas, creating electromagnetic challenges that legacy tools simply cannot model effectively, if at all. The problems are scaling faster than the tools, and RF engineering talent is scarce enough that valuable engineers shouldn’t spend weeks waiting for simulations to complete. When design iterations take days or weeks, innovation slows dramatically.

Third is the productivity constraint this creates. Engineers need tools that can keep pace with the complexity of the systems they’re designing, not tools that force them to compromise or wait.

What makes Nullspace unique?

Nullspace’s differentiation is architectural. While others modify decades-old code, Nullspace rebuilt from scratch for modern parallel computing, representing a fundamental advancement in electromagnetic simulation capability.

Performance leads the differentiation: over 25x faster, Nullspace software can solve problems that crash competitor tools entirely. Beyond speed, the Python API foundation enables AI-guided optimization and automation, allowing engineers to set up iterative design loops that run automatically, a capability that’s difficult or impossible with legacy tools.

Nullspace runs efficiently on both CPUs and GPUs, while many other solutions require one or the other, or force costly per GPU or CPU pricing on customers.

Finally, Nullspace’s decade-plus validation on real products that were designed and delivered to DoD provides proven reliability. When organizations need mission-critical accuracy, that track record speaks volumes.

How do customers normally engage with Nullspace?

Engagement typically starts when traditional tools fail. An engineering team hits a wall, whether it’s a simulation that won’t converge, a model too large to run, or deadlines that current tools can’t meet. They reach out, often through word-of-mouth in the RF engineering community.

Nullspace runs a technology transfer process where the team takes the customer’s actual problem, sets it up in Nullspace, and demonstrates the performance gain. When they see their two-week simulation complete in ten hours with equal or better accuracy, the value becomes clear.

For defense and aerospace customers, security and compliance are critical. Nullspace’s defense background means the company understands ITAR requirements, can operate in air-gapped environments, and has experience with the procurement process. Nullspace provides extensive hands-on support during onboarding, working closely with customers to ensure they can tackle problems no other tool can handle.

Also Read:

CEO Interview with Eelko Brinkhoff of PhotonDelta

CEO Interview with Haber Ma of ADCERAX

CEO Interview with Pere Llimós Muntal of Skycore Semiconductors

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Cost, Cycle Time, and Carbon aware TCAD Development of new Technologies

Cost, Cycle Time, and Carbon aware TCAD Development of new Technologies
by Daniel Nenni on 12-18-2025 at 10:00 am
Categories: Semiconductor Services, Synopsys, TechInsights

image001

Our good friend Scotten Jones wrote a paper on a product that has been in joint development with Synopsys and is now available. Scott is currently President Semiconductor Manufacturing Economics and Senior Fellow at TechInsights. Scott and I have discussed this product many times and I feel it is ground breaking technology for semiconductor design. Scott briefed me on it at IEDM and sent me the white paper. Here is my take on it:

The semiconductor industry is shifting from traditional Power, Performance, and Area (PPA) metrics to a broader PPACtE framework, incorporating Cost (C), Cycle Time (t), and Environmental impact via Carbon Equivalents (E). Synopsys’ DTCO suite has long facilitated TCAD-based PPA optimization. TechInsights’ Cost Explorer plug-in integrates into Synopsys Sentaurus Process Explorer, enabling full PPACtE analysis. This tool has been demonstrated by Tokyo Electron to assess CFET architectures, revealing a 15.3% cost premium for sequential over monolithic designs. With node development costs exceeding billions, Cost Explorer promises substantial savings in R&D and manufacturing by simulating CtE alongside PPA before physical prototyping.

Introduction

For decades, semiconductor advancements focused on PPA improvements, as seen in TSMC’s 3nm node offering 25-30% power reduction, 10-15% performance boost, and 70% density gain over 5nm. However, escalating costs, extended cycle times, and environmental concerns—highlighted by industry leaders like TSMC and Applied Materials—demand inclusion of CtE. With 3nm/2nm R&D nearing $10 billion per node, early simulation is crucial. DTCO co-optimizes design and process, but traditional tools like Synopsys’ suite lack CtE modeling. TechInsights’ Cost Explorer addresses this, enhancing Synopsys’ ecosystem for comprehensive PPACtE optimization, as proven in CFET studies.

New Technology Development

Semiconductor node development spans two phases: initial simulation-driven optimization of devices, models, and flows to meet PPA, followed by test chip fabrication and PDK refinement. TCAD minimizes costly wafers by iterating assumptions virtually. Synopsys DTCO excels here but omits CtE, limiting holistic optimization.

Synopsys DTCO Solution

Synopsys’ DTCO flow integrates tools like Proteus for patterning, QuantumATK for materials, Sentaurus TCAD for architectures, and Fusion Technology for design evaluation. Benefits include accurate pre-wafer simulations, realistic context feedback, and variation-aware modeling for reliable PPA. Collaboration with TechInsights adds CtE metrics, expanding design evaluation.

Synopsys Sentaurus Process Explorer

This tool enables interactive 3D visualization, process debugging, and metrology for advanced nodes like FinFETs and GAA. Features support yield analysis, anomaly detection, and TCAD integration, reducing cycle time and enhancing collaboration. It accelerates DTCO by identifying issues early, maximizing simulation ROI.

CtE Modeling Requirements

CtE estimation demands detailed fab and process modeling. Cost varies by fab capacity, location, and steps, calculated via equipment, labor, materials, and facilities. Cycle time uses ideal estimates (step-by-step processing) multiplied by an  Xideal factor for realism. Carbon footprint tracks material usage, emissions, and abatement. Cost Explorer computes these from process flows.

How Cost Explorer Works

Users define fab parameters (country, capacity, node) and build flows by selecting from 93 equipment types, parameterizing steps (e.g., film thickness). Pre-populated tables handle configurations, throughputs, costs, and materials. Algorithms compute equipment needs, costs (wafers, labor, depreciation), ideal cycle time, and carbon via GWP factors. Outputs include per-step breakdowns, as in Samsung 3nm GAA analysis.

Integration with Sentaurus Process Explorer

In Process Explorer, users assign equipment to steps, triggering Cost Explorer to auto-populate and calculate CtE. Results display per step and total, enabling iterative PPACtE refinement within the DTCO flow.

Use Cases

Tokyo Electron’s 2023 VLSI study used an early Cost Explorer to compare CFETs: monolithic (better performance, area) vs. sequential (3% lower performance, 6% higher power, 15.3% higher cost). Future work includes 2nm nanosheet evaluations with/without backside power, incorporating tE.

Bottom line: Cost Explorer’s integration into Synopsys DTCO empowers pre-wafer PPACtE optimization, slashing development costs and yielding efficient, sustainable processes. In a billion-dollar R&D landscape, this yields significant long-term savings in manufacturing, time, and emissions.

Download Paper Here

Also Read:

How PCIe Multistream Architecture Enables AI Connectivity at 64 GT/s and 128 GT/s

WEBINAR: How PCIe Multistream Architecture is Enabling AI Connectivity

Lessons from the DeepChip Wars: What a Decade-old Debate Teaches Us About Tech Evolution

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Quantum Computing Technologies and Challenges

Quantum Computing Technologies and Challenges
by Bernard Murphy on 12-18-2025 at 6:00 am
Categories: 3D IC, Quantum Computing
3 Comments

superconducting and trapped ion quantum computers min

There’s more than one way to build a quantum computer (QC) though it took me a while to find a good reference. I finally settled on Building Quantum Computers: A Practical Introduction. Excellent book but designed only for those who will enjoy lots of quantum math. I’m going to spare you that and instead describe a couple of the more popular technologies and the challenges they face. My summary of challenges here is highly selective in the interest of a quick read.

Superconducting QC

I touched on this topic a little in an earlier blog so I’ll add some new info here. Superconductivity emerges below relatively modest temperatures, >4 kelvin, but QCs are cooled to tens of millikelvin to reduce thermal noise. The volume a dilution fridge can economically drop to this temperature is quite small, not an issue for the chip but a big issue for control wiring/microwave guides. This can limit scaling qubit counts since qubit operations and readout are controlled by these signals.

Programming control depends on microwave resonances with qubits. Each qubit can be tuned in-situ to have a unique resonant frequency but put enough qubits near each other plus tuned microwave stimulus with finite frequency spread and it is easy for stimulus to stray beyond the intended target, triggering other qubits.

Physical constraints on-chip are challenging. Connecting an array of qubits is easiest through a grid of rather bulky waveguides but such topologies are significantly limiting for programmability options if only nearest neighbors can interact. As another way to increase densities, 3D stacking is an active area of research. IBM is already showing stacking in their Eagle processor family, qubits in one layer, resonators in a layer below that, allowing for higher densities. (Interestingly Eagle doesn’t aim for highest possible qubit densities, instead favoring reduced error rates.) IBM currently holds the record for (noisy) qubits on a chip on their Condor series at 1,121, though they don’t advertise area.

These technologies have quite short coherence times (~microseconds to milliseconds, the time before any carefully constructed quantum state collapses), though gate speeds are ~1000 times faster than in trapped ion technologies.

Trapped ion QC

Transitions between key energy levels in ions provide highly accurate time references. These have a long history (1950s) and are foundational in atomic time standards used in e.g. GPS support. Application to quantum computing was an obvious extension and first appeared around the mid 1990s, a little earlier than superconducting quantum computing.

The basic idea is simple. An ion with a single electron outside otherwise closed shells (e.g. Ca+) will exhibit energy levels roughly comparable to hydrogen, the simplest and most comprehensively understood atom in quantum theory and therefore an excellent basis for a qubit. A string of such ions can be captured in an ion “trap”, held in place by a combination of static and oscillating electric/magnetic fields. Contemporary traps are built using familiar microfabrication techniques, embedding control electrodes in a planar surface and floating the ions about 100um above the surface.

Qubit states are controlled by lasers or magnetic fields and are read by lasers, in either case structurally simpler than the waveguides so far exhibited in superconducting technologies. A single qubit gate is implemented by a pulse targeting an individual (localized) ion to excite transitions between ground and first excited states (|0> and |1> states in qubit terms). 2-qubit gates use 2 phase-coherent laser beams and additional quantized motional degrees of freedom in this technology to entangle two qubits (I don’t know the method for magnetic control).

There is a limit to how many ions can be held effectively in a single trap (tens of ions from what I have seen though records stretch to a few hundred), so scaling is accomplished by replicating traps and coupling them through photon exchange between traps. Highest counts I have seen (Quantinuum) are 56 qubits. Reported area for a chip is “thumbnail size”. IonQ is another trapped ion player, claiming a more scalable architecture, whereas Quantinuum claims superior accuracy and performance.

Trapped ion systems still use ultra-low cooling infrastructure (though they do not depend on superconductivity) and a vacuum chamber. Replicating this machinery many times would be expensive and likely would suffer reliability problems. On metrics, trapped ion technologies are ahead significantly in coherence times (up to seconds or even hours) and fidelity/accuracy of gate operations, which might (?) suggest less complex quantum error correction machinery. However, trapped ion system gate speeds are quite a bit slower than other technologies.

Quantum error correction

This topic could be differentiating between competing solutions. Here’s my take based on what I can find on IBM and Quantinuum in this area.

A common approach to address QEC is by entangling multiple physical qubits for a logical qubit. This had required 1000:1 physical to logical qubits in superconducting systems which IBM now admits was impractical. They recently published (see the link) a new method which reduces this requirement considerably. This method they claim should make a large-scale fault-tolerant quantum computer practical by 2029. The target system at that point, Starling, should feature 200 logical qubits and be capable of performing 100 million quantum operations.

Quantinuum with Microsoft have demonstrated an even lower required physical to logical qubit ratio in their ion-based system and anticipate that their target Apollo system in 2029 will support 100s of logical qubits with very low error rates. Interesting that IBM and Quantinuum carefully avoid side-by-side comparisons except on logical qubit counts 😀.

Takeaways

These technologies continue to advance though neither has yet reached production level based on their projections. However they have both pulled in their target date by a year, to 2029. There are some commonalities with semiconductor fabrication but how big an overlap remains to be seen. Still an interesting area to watch. Who knows what new breakthroughs will emerge in that window?

By the way, shout-out to Fred Chen for prodding me to go deeper in this area 😀

 

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3D ESD verification: Tackling new challenges in advanced IC design

3D ESD verification: Tackling new challenges in advanced IC design
by Admin on 12-17-2025 at 10:00 am
Categories: 3D IC, EDA, Siemens EDA

fig1 3d structures

By Dina Medhat

Three key takeaways

  • 3D ICs require fundamentally new ESD verification strategies. Traditional 2D approaches cannot address the complexity and unique connections in stacked-die architectures.
  • Classifying external and internal IOs is essential for robust and cost-efficient ESD protection. Proper differentiation enables optimized protection schemes, area savings, and reliable performance.
  • Industry-proven automation tools, like Calibre 3DPERC, are essential to meet evolving ESD verification needs in heterogeneous 3D designs.

Why is ESD verification critical for 3D IC designs?

Electrostatic discharge (ESD) remains one of the most persistent threats to integrated circuits at every step of the lifecycle—from manufacturing through operation. ESD events release a sudden surge of electrical current, which can melt metal, break down junctions, or destroy oxides, leading to costly failures. Effective ESD protection is therefore not just good practice—it is essential for reliability and product lifetime.

How do ESD protection circuits prevent damage?

Successful ESD protection hinges on choosing robust circuit architectures and ensuring that physical implementation matches the design intent. IC designers introduce specific ESD protection schemes at both the schematic and layout stages. Before manufacturing, ESD protection rules are verified to confirm enough safeguards are in place—addressing topology requirements and confirming that interconnects can handle ESD events. Verification at this stage is fundamental to design reliability.

What’s different about ESD protection in 3D ICs?

3D integration is revolutionizing IC design. In 2.5D architectures, dies sit side-by-side atop a silicon interposer. Micro-bumps (or Hybrid-bumps) connect each die to the interposer, and flip-chip bumps connect the interposer to the ball grid array (BGA) substrate. Full 3D integration stacks dies on top of each other, linked by through-silicon vias (TSVs). Designers often mix technologies and process nodes across dies, leveraging different vendor solutions for interposers, packaging and fabrication. Each integration method introduces unique benefits along with specific ESD challenges. Figure 1 demonstrates the main difference between 2.5D integration and 3D integration.

Figure 1: 2.5D versus 3D designs.

Why 3D ESD verification is more complex than 2D and 2.5D

Traditional 2D ESD verification considers all chip pads as interfaces to the outside world, and these demand robust protection against ESD events. In 3D designs, however, many pads serve only as internal die-to-die connections, not external IO interfaces (figure 2). This distinction is crucial:

  • External IOs face ESD events from package pins and require comprehensive protection.
  • Internal IOs are far less exposed and can use smaller, more efficient ESD devices—saving area and cost.

Figure 2: External IOs versus internal IOs.

External IOs are connected to the package pins and face more ESD events than internal IOs. Similar to 2D designs, external IOs are affected by both human body model (HBM) and charged device model (CDM) ESD events. However, internal IOs are affected by far fewer HBM and CDM events. This difference means internal IOs can use smaller ESD protection circuits, which in turn translates into significant savings in die area and cost without sacrificing overall ESD protection robustness.

Furthermore, in 3D ICs, protection needs to be evaluated at the system level—not on a die-by-die basis. This opens the door for exploring the minimum ESD protection needed to avoid the failure of the final 3D product. ESD devices can span multiple dies or reside on a die with a different process node than the signal they protect. Complex connection topologies mean that power clamps, resistors and other ESD components may be shared, increasing verification complexity. There are many ways to optimize your preferred ESD methodology to reduce the final cost for manufacturing the 3D design, but at the cost of ESD verification complexity. Add the challenge of integrating multiple process nodes and vendors, and verification must become architecture-driven, not just foundry-specific.

So to summarize some of the key challenges for 3D ESD verification:

  • Differentiating between ESD protection for external IOs versus internal IOs
  • Handling CDM and HBM constraints for die-to-die connections
  • Determining the minimum ESD protection needed to avoid failure of the final 3D IC product
  • Accounting for different technology nodes / foundries for the dies & handling interfaces
  • Determining how to source from multiple vendors and ensure consistent ESD protection
  • Dealing with different ESD design methodologies

Automating ESD verification for 3D IC designs

Modern ESD verification tools, such as Calibre 3DPERC, address these new challenges head-on The recommended workflow combines die-level and assembly-level analysis. Using Calibre PERC, designers first verify the ESD robustness of each die and interposer. Calibre 3DPERC then performs system-level checks, identifying point-to-point (P2P), topology and geometrical violations across the assembled stack. This robust approach ensures that ESD reliability is maintained throughout heterogeneous 3D architectures (figure 3).

Figure 3: 3D ESD verification methodology (using Calibre 3DPERC).

The bottom line on ESD verification for 3D IC

ESD protection is an essential element in IC design. 2D ESD verification is well-established, 3D architectures require a new mindset and advanced IP to address evolving threats. ESD devices can span multiple dies and need to be combined for correct evaluation. IO type (external vs internal) have different ESD requirements. Moreover, mixing different tech nodes from different foundries contributes to the 3D ESD verification challenges. Designers should consider adopting a newer automated ESD verification methodology to effectively and accurately address the challenges of ESD robustness in 3D designs. Ensuring accurate and consistent 3D ESD protection raises the reliability and product life of these products, ensuring they deliver the value and functionality the market demands.

Author

Dina Medhat is a principal technologist and technical lead for Calibre Design Solutions at Siemens EDA, a part of Siemens Digital Industries Software. She has held multiple product and technical marketing roles in Siemens EDA. She received her B.Sc., M.Sc., and Ph.D. degrees from Ain Shams University in Cairo, Egypt. She coauthored a book chapter in Reliability Characterisation of Electrical and Electronic Systems, (Jonathan Swingler, Editor—Elsevier, 2015). In addition to over 45 publications, she holds a U.S. patent.  Her research interests include reliability verification, electrostatic discharge, emerging technologies, 3D integrated circuits, and physical verification.

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Signal Integrity Verification Using SPICE and IBIS-AMI

Propelling DFT to New Levels of Coverage

AI-Driven DRC Productivity Optimization: Insights from Siemens EDA’s 2025 TSMC OIP Presentation

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Navigating SoC Tradeoffs from IP to Ecosystem

Navigating SoC Tradeoffs from IP to Ecosystem
by Daniel Nenni on 12-17-2025 at 8:00 am
Categories: Andes Technology, Events, IP

Building an SoC is Hard 2025

Building a complex SoC is a risky endeavor that demands careful planning, strategic decisions, and collaboration across hardware and software domains. As highlighted in Darren Jones’ RISC-V Summit presentation from Andes Technology, titled “From Blueprint to Reality: Navigating SoC Tradeoffs, IP, and Ecosystem,” the journey from conceptual design to functional silicon involves navigating numerous tradeoffs while leveraging intellectual property and a supportive ecosystem. This process is not just technical but also strategic, ensuring that the final product meets performance, power, and cost goals while incorporating unique innovations, what Darren calls the “Secret Sauce.”

The first step in SoC development is defining clear goals. Engineers must identify key metrics such as performance benchmarks, power efficiency, area constraints, and market timelines. Understanding the “Secret Sauce” that distinctive feature setting the SoC apart, like advanced AI acceleration or ultra-low power consumption is crucial. A realistic assessment of schedule, resources, and costs prevents overruns. For instance, underestimating integration time can derail projects, as SoCs often combine custom logic with third-party IP.

SoC architecture forms the foundation, deciding what functions are implemented in hardware versus software. Hardware handles time-critical tasks like signal processing, while software offers flexibility for updates. This partitioning affects everything from power usage to scalability. Darren emphasizes modeling the architecture early to simulate tradeoffs, using tools like SystemC for high-level abstraction.

Hardware design involves critical choices: make or buy. Developing custom blocks in-house allows tailoring but increases risk and time. Buying IP, particularly processor cores, accelerates development. Darren focuses on processor IP selection, stressing hardware considerations like Power, performance and Area (PPA). Bus interface compatibility ensures seamless integration, such as with AXI or AHB standards. Customization is key in RISC-V ecosystems, where extensions like vector processing or custom operations enable the “Secret Sauce.” Questions like “Can your vendor enable features you didn’t think possible?” underscore the need for flexible partners.

Proper IP deliverables are non-negotiable: RTL code, testbenches for verification, documentation, and IP-XACT for metadata. Models range from fast instruction-set simulators for software development to cycle-accurate ones for timing validation and SystemC for system-level simulation. Product support and quality silicon-proven designs from reputable vendors mitigate risks. Andes Technology, a leader in RISC-V IP, exemplifies this with their AndesCore CPUs, which support coherent multi-core setups with features like platform-level interrupt controllers and L2 cache managers.

Software considerations are equally vital, often overlapping with hardware choices. Development tools, compilers, and IDEs must support the architecture. Operating system availability, Linux for complex applications, RTOS for real-time systems, or bare-metal for simplicity affects portability. Legacy code porting requires compiler compatibility, while application and firmware development demands efficient toolchains. Third-party code integration, such as DSP or neural network libraries, enhances functionality. Debug tools, including JTAG interfaces and software profilers, are essential for troubleshooting.

Collaboration with IP vendors is a recurring theme. Engaging early facilitates architecture discussions, customization, and benchmarking. Vendors like Andes provide PPA data and models to validate designs. Deliverables empower success: run the testbench to verify IP, read docs thoroughly, and use models for co-simulation. Product support prevents wasted effort. Darren advises contacting vendors promptly and building relationships for ongoing assistance.

In practice, these elements form an ecosystem where tradeoffs are inevitable. Prioritizing power might sacrifice performance, or customization could inflate costs. Successful SoCs, like those in IoT devices or automotive systems, balance these through iterative modeling and vendor partnerships. Andes’ tools, such as their DNN use-case models for neural networks, illustrate how integrated ecosystems support applications from frame capture to AI inferencing.

Bottom Line: Navigating SoC development requires a holistic approach. By knowing goals, architecting wisely, selecting robust IP, addressing software needs, and fostering vendor collaborations, teams can turn blueprints into reality. As Jones concludes, this ecosystem-driven strategy not only mitigates challenges but unlocks innovation, ensuring competitive edges in a fast-evolving semiconductor landscape.

Also Read:

The RISC-V Revolution: Insights from the 2025 Summits and Andes Technology’s Pivotal Role

Beyond Traditional OOO: A Time-Based, Slice-Based Approach to High-Performance RISC-V CPUs

Andes Technology: Powering the Full Spectrum – from Embedded Control to AI and Beyond