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CEO Interview with Fabrizio Del Maffeo of Axelera AI

CEO Interview with Fabrizio Del Maffeo of Axelera AI
by Daniel Nenni on 03-14-2025 at 6:00 am
Categories: CEO Interviews

Fabrizio Del Maffeo CEO Co Founder (2)

Fabrizio Del Maffeo is the CEO and co-founder of Axelera AI, the Netherlands-based startup building game-changing, scalable hardware for AI at the edge. Axelera AI was incubated by the Bitfury Group, a globally recognized emerging technologies company, where Fabrizio previously served as Head of AI. In his role at Axelera AI, Fabriozo leads a world-class executive team, board of directors and advisors from top AI Fortune 500 companies.

Prior to joining Bitfury, Fabrizio was Vice President and Managing Director of AAEON Technology Europe, the AI and internet of things (IoT) computing company within the ASUS Group. During his time at AAEON, Fabrizio founded “UP Bridge the Gap,” a product line for professionals and innovators, now regarded as a leading reference solution in AI and IoT for Intel. In 2018, Fabrizio, alongside Intel, launched AAEON’s “AI in Production” program. He also previously served as the Country Manager for France and Sales Director for Northern, Southern and Eastern Europe at Advantech, the largest industrial IoT computing company. In this role, he also led the intelligent retail division. Fabrizio graduated with a master’s degree in telecommunication engineering from Milan Politecnico University.

Tell us about your company?

Axelera AI was founded in July 2021 with Evangelos Eleftheriou, emeritus IBM Fellow, myself and a core team from Bitfury AI, IMEC, researchers from IBM Zurich Lab, ETH Zurich, Google and Qualcomm.

Our mission is to rapidly provide access to advanced Edge AI-native hardware and software solutions for companies of all sizes across a range of market verticals and place AI in the hands of those who could not otherwise afford it. We do this by delivering faster, more efficient and easy-to-use inference acceleration while minimizing power and cost. To do this, our platform is purpose-built to support AI strategies across a wide-range of industries while seamlessly integrating with existing technologies.

With our team of brilliant engineers, developers and business experts, we are focused on building our solutions and ecosystem that together will drive the democratization of AI, enabling a green, fair and safe world.

In three years, Axelera AI has raised USD 120 million, built a world-class team of 190+ employees (including 60+ PhD’s with 40,000+ citations), launched its Metis™ AI Platform and is the largest AI semiconductor company in Europe.

The company is backed by major institutional investors, including Samsung Catalyst Fund, the European Innovation Council Fund, Innovation Industries Strategic Partnership Fund (backed by MN/Pension Fund for Metal and Technique), Invest-NL Deep-Tech Fund , along long-standing investors Verve Ventures, Innovation Industries, Fractionelera,the Italian sovereign fund CDP Venture Capital SGR, the Dutch Enterprise Agency (RVO), Bitfury,  Federal Holding and Investment Company of Belgium (SFPIM), imec andimec.xpand.

What problems are you solving?

Current iterations of AI technology have leveraged more general purpose acceleration and have delivered expensive, power-hungry solutions that prove to be inefficient for many use cases. In the cloud, with access to water-cooling and large power supplies, this architecture suffices, but it is poorly suited for the edge.

At Axelera AI, we are revolutionizing the field of artificial intelligence by developing an industry-defining hardware and software platform for accelerating computer vision and generative AI on edge devices. Our platform, built using proprietary in-memory computing technology and RISC-V dataflow architecture, delivers industry-leading performance and usability at a fraction of the cost and energy consumption of current solutions.

Power consumption is a critical factor both on devices and in data centers. Axelera AI offers leading compute density with exceptional core efficiency which means systems can easily crunch data without draining power or running hot, with a typical use case requiring just a few watts.

One of the biggest challenges for Edge AI is optimizing neural networks to run efficiently when ported onto a mixed-precision accelerator solution. Our platform includes advanced quantization techniques and mapping tools that significantly reduce the inference computational load and increase energy efficiency. By creating integrated solutions that are powerful, cost effective and efficient, Axelera is bringing inference to the edge with accuracy.

What application areas are your strongest?

Axelera AI is primarily focused on providing powerful AI inference solutions for edge computing and high-performance applications. The first generation of AI processing unit, Metis, focuses on primarily on computer vision and some of the strongest application areas include:

  • Security and Surveillance Axelera AI excels in real-time image and video processing for applications like campus management, safety, surveillance, access control
  • Automotive: autonomous vehicles and infotainment
  • Industrial automation: real-time high speed quality control, pick-and-place and general purpose robotics
  • IoT Devices: Their technology is well-suited for IoT applications, enabling smart devices to process data locally with minimal latency.
  • Smart Cities: AI-powered analytics for traffic management, public safety, and resource optimization can benefit from Axelera’s capabilities.
  • Retail: Providing a frictionless experience for customers with personalized recommendations, queue management, fast and efficient checkouts, and smart mirrors.
  • Healthcare: With nearly 10 million fewer health workers[1] than the world needs, bringing AI inference to the healthcare system will allow doctors to more quickly understand and diagnose patients.

We have been working on broadening our future product offerings from the edge to the enterprise servers to address the growing computing needs for generative AI, large language models and large multi-modal models.

What keeps your customers up at night?

Neural networks are getting bigger and they require more computations. Scaling performance using CPUs and GPUs are inefficient and extremely expensive. We are fully focused on tailoring our technology around the new emerging needs, efficiently offloading completely the AI acceleration from the CPU inside our AI processing unit.

We must also contend with the realities of the current chip market. These realities include the high cost of hardware, as well as ongoing shortages in the industry. A discrepancy in the demand and supply of chips, fueled by supply chain delays, the pandemic, natural disasters and labor market changes, is heavily impacting the global semiconductor space.

There is also the question of Moore’s Law and energy usage. Moore’s Law suggests that the number of transistors in an integrated circuit would double every two years, which played a driving role in modern tech development like computers. However, modern semiconductors are far more technologically complex and require significant energy to produce and progress. With our Metis AI Platform, we aim to overcome these challenges by delivering a product that packs the power of an entire AI server – all at a fraction of power consumption and cost of other solutions.

What does the competitive landscape look like and how do you differentiate?

Until now, AI systems and applications have relied on the computational performance of large, power hungry and expensive hardware. However, fully unlocking the potential of AI, especially at the Edge, requires a dramatic increase in FPS/$ which will enable complex AI applications to run on-device at the Edge. Running the industry-standard benchmark of ResNet, YoloSSD-Mobilenet families, the Metis PCI delivers high performance at a fraction of power consumption and price of today solutions. Furthermore, Metis excel in real application pipelines thanks to the possibility to run in parallel on different core multiple networks, delivering 5-10x higher throughput than existing solutions.

A major advantage of our  SRAM-based D-IMC technology is that it has been implemented in standard CMOS technology. Our  design uses proven, cost-effective and standard manufacturing processes, readily available in any silicon foundry which brings supply chain resiliency to system builders. Memory technologies are also a key driver for lower lithography nodes. So, Axelera AI will be able to easily scale performance as the semiconductor industry brings advanced lithography nodes into volume production.

We are also going beyond just the accelerator technology and chip development, building a fully interconnected ecosystem of support powered by a versatile and easy-to-use software stack: our VoyagerTM  SDK.

What new features/technology are you working on?

The full production-ready Metis AI platform is now in production delivering high performance and preserving 99% of the original model’s precision, indistinguishable from GPU-based inference models, while offering 4-5 times throughput, energy efficiency and cost savings.

We have a complete product portfolio including standard form factors like an M.2 card to PCI-E cards capable of handling the most demanding vision applications. We have a complete roadmap that scales from single digit watt usage to enterprise grade server usage.

Our platform includes advanced quantization techniques that enable customers to run out of the box state of arts neural networks and mapping tools that significantly reduce AI computational load and increase energy efficiency,

Finally, our software tool chain allows customers to build up a complete application pipeline in a matter of minutes, simplifying the deployment of artificial intelligence in any device and opening up unprecedented opportunities for mass deployment of AI solutions.

Nowadays we are working on expanding the neural networks zoo to support Large Language Models on Metis. We are also in advanced design with the new AI processing unit, complementary to Metis and more focused on generative AI workload. The product line will be announced later next year.

 How do customers normally engage with your company?

Whether you are a computer vision system developer or integrator, software vendor or OEM, our AI acceleration hardware has been built to meet your needs. Delivering leading AI acceleration hardware in a range of industry accepted form factors supported by our easy-to-use software stack, Metis simplifies development, integration and deployment of AI inference acceleration.

Valuation kits are available in six variations, each designed for industry-defining AI vision inference. The kits are equipped with the Metis AIPU integrated in an AI Acceleration card, and the Voyager Software Development Kit, allowing users to evaluation performance and vision systems using popular AI inference networks such as YOLOv7.

Customers use the SDK to bring their applications into the Metis AI platform and run it on Axelera’s powerful Metis AI Processing Unit (AIPU), whether the application is developed using proprietary or standard industry models. The VoyagerTM SDK offers end-to-end integration and is API-compatible with de-facto industry standards, unleashing the potential of the Metis AIPU, delivering high-performance AI that can be deployed quickly and easily.

The VoyagerTM SDK comes with a Model Zoo, a catalog of state-of-the-art AI models and turnkey pipelines for real-world use cases including image classification, object detection, segmentation, keypoint detection, face recognition and other Computer Vision tasks. Importantly, developers can easily modify any of the offered models to work with their own datasets or make them fit better to their application requirements.

We are working on creating a frictionless experience for our customers who soon will be able to buy online our products and get supported by an online developer community.

Contact Alexera AI

[1] World Health organization: Health workforce

Also Read:

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CEO Interview with Dinesh Bettadapur of Irresistible Materials

CEO Interview with Pierre-Yves Lesaicherre of Finwave CEO

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A Realistic Electron Blur Function Shape for EUV Resist Modeling

A Realistic Electron Blur Function Shape for EUV Resist Modeling
by Fred Chen on 03-13-2025 at 10:00 am
Categories: Lithography

EUV Image 4

Peak probability at zero distance actually makes no sense

In lithography, it is often stated that the best resolution that can be achieved depends on wavelength and numerical aperture (NA), but this actually only applies to the so-called “aerial” image. When the image is actually formed in the resist layer, it also depends on an additional factor, known as blur.

What blur does is reduced the image contrast, i.e., the difference between the maximum and minimum doses delivered for an image pattern. The range of doses delivered to the wafer is clustered closer to the threshold dose for printing. This inherently worsens the sensitivity to the stochastic effect of photon shot noise and random secondary electron yield per photon.

Blur can have multiple origins: flare [1], image fading [2], stage desynchronization [3], and photoelectrons and secondary electrons [4]. The EUV-induced plasma [5] provides further sources of unwanted remote exposure.

In order to quantitatively assess the impact of blur on contrast, it needs to be described mathematically. It is represented as a spatial distribution function, which is convolved with the optical image to produce the net image deposited in the resist. Commonly used functions for the blur shape are Gaussian functions [1] and exponential functions [4]. However, these functions peak at zero distance, which would indicate that ~80 eV EUV photoelectrons hardly move any distance. This is clearly a nonphysical representation. On the other hand, it is well-known that the 1/e attenuation length for these photoelectrons is ~ 1 nm [4]. Experimental data are consistent with probability of no reaction or scattering of electrons fitting an exponential decay function with decay constant of ~ 2 nm [4] for distances >1 nm. Such a function can be obtained by taking a difference of two exponential functions, as shown in Figure 1. There is a peak at ~ 1 nm, which reflects the scenario that most photoelectrons quickly move 1 nm distance in less than 0.2 fs before any scattering or reacting.

Figure 1. The exponential function (orange) has an unrealistic peak probability at zero distance. Subtracting an exponential function preserves the long-distance behavior but gives a more accurate representation of the photoelectron mean free path ~ 1 nm. Here the difference of exponential functions is shown in black. The orange exponential function is 0.25/nm exp(-x/2 nm), while the subtracted exponential function is 0.05/nm exp(-x/0.4 nm).

With this function, the next step is to convolve it with the sinusoidal optical image.

Some Necessary Math…

As a kind of lemma, we first derive the formula for integration of the product of an exponential function and a cosine function:

Then, we use this to get our formula for the convolution of an exponential function with a cosine function:

Basically, it states that the effect of convolving the exponential function with a sinusoidal function is to effectively reduce the amplitude of that sinusoidal function by a factor of 1/(1+(2 pi lambda/pitch)^2), where lambda is the decay distance of the exponential function. The convolution for the difference of two exponential functions is simply the difference of the separate convolutions of the individual exponential functions.

Example One: 15 nm Half-Pitch

First, we consider the impact of the new blur shape on a simple 15 nm half-pitch image, typically expected for the 5nm node family (including 4nm node).

Figure 2. The electron blur function of Figure 1 reduces the NILS for 15 nm half-pitch (0.33 NA system). The stochastic image of electrons/nm2 (right) assumes a 20 mJ/cm2 absorbed dose with a nominal electron/photon ratio of 8 (can vary from 7 to 9).

The first effect to note is the reduction of image contrast mentioned earlier. The normalized image log-slope (NILS) is consequently reduced from 2.84 to 1.85. The reduced contrast also worsened the stochastic influences on the electron density, compared to no blur. The main effect is degradation of the edge definition. There is also increased defectivity in the nominally exposed region, which can lead to shorts between metal lines when negative-tone metal oxide resists are used. This suggests insufficient dose.

The absorbed dose of 20 mJ/cm2 corresponds to 60 mJ/cm2 in 20 nm thick metal oxide resist. A higher dose would lead to increased exposure to the EUV-induced plasma, reducing the resist thickness [7]. This would in turn reduced the absorbed dose used to define the resist pattern, aggravating the stochastic effects.

Example Two: 8 nm Linewidth (16 nm and 32 nm Pitches)

Looking at post-2nm nodes, 8 nm metal half-pitch is specified by the IRDS 2022 edition [6]. A smaller pitch increases the flattening of the sinusoidal optical image, which reduces the contrast further. Figure 3 shows the 8 nm half-pitch, with a larger NILS reduction, and hence, substantially more stochastic defectivity, even affecting the nominally unexposed areas.

Figure 3. The electron blur function of Figure 1 reduces the NILS for 8 nm half-pitch (0.55 NA system). The stochastic image of electrons/nm2 (right) assumes a 20 mJ/cm2 absorbed dose with a nominal electron/photon ratio of 8 (can vary from 7 to 9). Note that two 16 nm pitches are shown here in the stochastic image.

A smaller linewidth is also naturally more sensitive to stochastic fluctuations of electron and photon density because NILS is reduced when the linewidth is reduced relative to the pitch. Figure 4 shows this for a 32 nm pitch with the same 8 nm linewidth.

Figure 4. The electron blur function of Figure 1 reduces the NILS for 8 nm linewidth on 32 nm pitch. Note that a two-beam image is used assuming maximal depth of focus. The stochastic image of electrons/nm2 (right) assumes a 20 mJ/cm2 absorbed dose with a nominal electron/photon ratio of 8 (can vary from 7 to 9).

The severe blur-aggravated stochasticity for both 8 nm half-pitch and linewidth means High-NA (0.55 NA) EUV systems cannot support either direct printing or double patterning for the 16 nm pitch, respectively. This goes back to the earlier point that electron blur, not NA, becomes the effective resolution limiter in EUV lithography [8].

References

[1] L. Sun et al., “Review of resist-based flare measurement methods for extreme ultraviolet lithography,” J. Micro/Nanolith. MEMS MOEMS 12, 042001 (2013).

[2] T. A. Brunner et al., “Image contrast metrology for EUV lithography,” Proc. SPIE 12292, 122920A (2022).

[3] D. Schmidt et al., “Characterization of EUV image fading induced by overlay corrections using pattern shift response metrology,” Proc. SPIE 11147, 1114713 (2019).

[4] O. Kostko et al., “Evaluation of Electron Blur for Different Electron Energies,” J. Photopolymer Sci. & Tech. 37, 315 (2024).

[5] Y-H. Huang et al., “A study of hydrogen plasma‑induced charging effect in EUV lithography systems,” Discover Nano 18:22 (2023).

[6] https://irds.ieee.org/editions/2022/irds%E2%84%A2-2022-lithography

[7] F. Chen, Resist Loss Model for the EUV Stochastic Defectivity Cliffs.

[8] F. Chen, Why NA is Not Relevant to Resolution in EUV Lithography.

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Also Read:

Rethinking Multipatterning for 2nm Node

Resist Loss Model for the EUV Stochastic Defectivity Cliffs

Stochastic Effects Blur the Resolution Limit of EUV Lithography

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Siemens Fleshes out More of their AI in Verification Story

Siemens Fleshes out More of their AI in Verification Story
by Bernard Murphy on 03-13-2025 at 6:00 am
Categories: AI, EDA, Siemens EDA

AI maximizing verification productivity min

While Cadence and Synopsys were sharing a lot of detail over the past few years about what they were doing in AI, Siemens EDA seemed content to offer a very general picture about their intentions without getting into a lot of detail. At DVCon 2025 they finally pulled back the curtain. Why wait until now to announce?

Darron May (Director of AI Product Management at Siemens Digital Industries) hosted the session and pointed to the depth Siemens can already boast in AI – 1400 AI experts, nearly 4000 patents – developed over many years working with large enterprises. Also note Darron’s title – he stressed that Siemens is now one tech company, not Siemens plus Siemens EDA. The Siemens centralized AI team have been building a platform for the EDA guys, who have been integrating with and building on this broader expertise to develop and roll out their broader AI gameplan. Makes sense to me. Takes a little longer to get to announcement but ensures they can start from a proven base.

A quick recap on why AI in EDA

Darron opened with the obligatory marketing nod to chips becoming more complex (in part thanks to AI content), together with projections that the industry is going to be short 27,000 expert designers by the end of the decade.  All true but I’d like to add my own thoughts. The highly visible part of this growth, around AI accelerators from Nvidia, AMD, and the hyperscalers, is the tip of the iceberg. The real volume is in AI applications: wearables, smart homes, transportation, smart offices, medical, industrial, utilities, etc. IoT applications alone are expected to top 6 billion units by 2030. Those are going to be built on embedded designs customized with sensing, AI, and communications components to differentiate and be super cost and power effective.

These “applications” companies/business units have design and AI expertise, but they can’t build giant teams of experts because there aren’t enough experts. They must rely even more heavily on EDA, IP, even packaging technologies to meet their goals. You start to see why the industry needs to spin up more designers, including AI-assisted designers, to keep pace with demand.

Siemens advances in AI for verification

Siemens are broadly leveraging three types of AI in this domain: analytical based on unsupervised learning (ML), predictive based on ML and statistical analysis to predict future behaviors, and generative/agentic support based on LLMs. This is quite in-line with similar effort from big EDA companies.

The announcements aren’t groundbreaking in this industry but bear in mind that Siemens are catching up. I’ll start with their ViQ (Questa verification IQ) platform. The Coverage Analyzer already offers (in production) analysis to predict patterns and holes in coverage, provide root cause analysis and suggest solutions. For Debug, they have early adopter engagements in bad commit prediction, root cause prediction and signature prediction. And in regression navigation they have early adopters in smoke test prediction.

QCX (coverage acceleration), PSS Assist (GenAI for PSS) and Doc Assist (auto-generating docs) are all in early adopter engagements.

For creation, they are promoting Property Assist (GenAI assertion generation with extensive checking through static and formal tools to validate correctness) – this is the early adopter stage, whereas CDC Assist and RDC Assist (massively distilling crossing violations) are already in production.

There are multiple other capabilities planned but in the interests of avoiding future-looking statements I will leave those out 😀.

In summary, several capabilities in production and more on the way through early deployment. One thing that stuck with me – Siemens has that central AI team as a potential differentiator over others in the design and verification world. Worth watching. You can explore Siemens capabilities in EDA HERE.

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CEO Interview with Dinesh Bettadapur of Irresistible Materials

CEO Interview with Dinesh Bettadapur of Irresistible Materials
by Daniel Nenni on 03-12-2025 at 10:00 am
Categories: CEO Interviews

D. Bettadapur photo IM

Dinesh Bettadapur serves as the Chief Executive Officer of Irresistible Materials Ltd. Dinesh has over 20 years of executive management experience in the semiconductor industries and has held significant leadership roles encompassing general management, P&L management, sales, business development, strategic alliances, and operations. He has worked at industry leaders such as ASML, Intel, and Lam Research as well as multiple Silicon Valley startups and led them toward a significant degree of business growth including 3 successful exits.

Tell us about your company?

Irresistible Materials is an innovative electronic materials company that has developed a novel EUV resist material to help meet the unique and significant challenges of EUV lithography. It was founded in 2010 as a spinoff from the University of Birmingham and has developed other production worthy materials such as spin-on carbon for hardmasks and e-beam resists. But we are now purely focused on the development and commercialization of our high-performance EUV resist, which is called Multi-Trigger Resist (MTR™) and represents a new class of resist material.

Our MTR platform has been designed from the ground up specifically for EUV lithography, and addresses the limitations of legacy resist materials. It is up to two times faster than competing resists, which has the potential to result in annual cost-of-ownership (CoO) savings of approximately US$10-15 million per EUV scanner operating in a production fab.

Our team is a multi-disciplinary team comprised of world-class technologists with significant industry experience and strong academic background in multiple disciplines, including chemical engineering, lithography, material science, and synthetic chemistry.

What is the vision and strategy for the company?

Our vision is to be the pre-eminent supplier of EUV resist materials to the semiconductor industry through the market adoption of our innovative MTR photoresist platform. Our strategy is to collaborate closely with our customers across the industry’s leading integrated device manufacturers (IDMs) and foundries and offer customized resist materials to address their unique needs. In addition, we intend to strengthen our existing partnerships with key players in the ecosystem while also establishing a set of new partnerships. We are also taking a solution-oriented approach to ensure that our resist material becomes a plug-play material within the overall EUV lithography process.

What problems are you solving?

We are addressing the unique challenges and requirements of EUV lithography (both low NA and High NA). Traditional photoresists like chemically amplified resists (CAR) and metal oxide resists (MOR) cannot fully meet the requirements for higher resolution, low defectivity, and improved throughput. The need for specialized EUV photoresists will only become greater as chip manufacturers push the limits of EUV lithography to further reduce the size of chip feature sizes. Specifically, we are developing novel formulations of our resist material that can meet the key requirements of absorbance, defectivity, etch resistance, line width roughness (LWR), resolution, and sensitivity. There are multiple tradeoffs that have to be made in order to balance all of these requirements in order to generate optimum resist formulation.

What application areas are your strongest?

Our EUV resist material is highly applicable across both logic and memory devices as well as patterned layers corresponding to FEOL and BEOL processes (lines & spaces, contact holes, pillars, etc.).

What does the competitive landscape look like and how do you differentiate?

Our main competitors are those offering CAR and MOR resists. Our MTR technology is a new approach that combines the best of both worlds with additional unique features, which has the potential to offer the highest levels of performance. It uses a catalytic mechanism based on a photoacid generator similar to a CAR and is an organic compound, which makes it compatible with existing track solutions. But unlike a CAR, it is a controlled catalytic reaction based on unique proprietary molecules, which significantly limits or eliminates the acid diffusion resulting in high sensitivity and low LWR. Similar to MOR, it is a small molecule with high opacity, which delivers high resolution. But unlike a MOR, it is non-metallic and avoids metal contamination issues in the fab. Above and beyond all of this, it is a faster resist compared to both CAR and MOR and therefore offers the potential for significant CoO savings in a production fab. Finally, it is PFAS/PFOS-free, which makes it very environmentally friendly.

What new features/technology are you working on?

Broadly speaking, there are two categories of features and capabilities we are working on. The first category is related to improved formulations that can meet the specific short-term needs of customers. Examples of these are higher resolution (tighter pitches), lower linewidth roughness (LWR), and minimizing defectivity.

The other category is related to developing brand new formulations that can address medium-term and long-term industry needs. Examples of these are better delay tolerance, improved process compatibility, and higher absorption/depth of focus (particularly for high-NA EUV).

How do customers normally engage with your company?

Customers will typically ask us to provide a resist sample for testing based on a set of target performance requirements (e.g., resolution, LWR, sensitivity), operating conditions (e.g., bake temperature, post exposure delay) and the target pattern (e.g., lines and spaces, contact holes, pillars). We will then come up with an appropriate custom formulation, which is aimed at meeting their target requirements and perform internal testing before delivering it to the customer. Based on their testing, the customer may ask us to tweak the formulation for further optimization of one or more parameters. Once the customer is satisfied that our formulation meets their key requirements, they will move on to the next phase of material qualification which can eventually lead to a specific material becoming selected as a process of record (POR) material in preparation for high volume manufacturing (HVM).

Contact Irresistible Materials 

Also Read:

CEO Interview with Pierre-Yves Lesaicherre of Finwave CEO

CEO Interview with Matt Desch of Iridium

CEO Interview with Mike Noonen of Swave Photonics

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RISC-V’s Privileged Spec and Architectural Advances Achieve Security Parity with Proprietary ISAs

RISC-V’s Privileged Spec and Architectural Advances Achieve Security Parity with Proprietary ISAs
by Jonah McLeod on 03-12-2025 at 6:00 am
Categories: IP, RISC-V

Security Article Intro ART

Because of its open and modular nature, RISC-V has faced recognizable security challenges stemming from fragmentation, performance inefficiencies, and inherent vulnerabilities. Fragmentation across implementations leads to inconsistencies, making it difficult to enforce uniform security measures. Performance inefficiencies can introduce timing side-channel attacks, where attackers exploit execution time variations to extract sensitive data. Additionally, security vulnerabilities such as Jump-Oriented Programming (JOP) attacks and buffer overflow exploits have demonstrated RISC-V-based systems weaknesses. Addressing these risks has been a crucial focus in the ongoing development of the RISC-V Privileged Specification and supporting architectural innovations.

Recent Architectural Innovations

RISC-V’s privileged specification has faced challenges related to fragmentation, performance inefficiencies, and security vulnerabilities—factors that impact OS support, virtualization, and memory protection. However, recent progress in the RISC-V Privileged Specification has addressed many of these issues, bringing it closer to the robustness of proprietary ISAs like ARM and x86. In parallel, new architectural innovations are further strengthening RISC-V’s capabilities by introducing improvements in memory management, scheduling, and execution efficiency.

As of March 6, 2025, the RISC-V Privileged Architecture Specification version 1.13 has successfully completed its public review process and has been ratified. The 30-day public review period, which started on September 3, 2024, and concluded on October 1, 2024, allowed stakeholders to provide feedback and suggest improvements. Following this review, the specification underwent necessary revisions and was officially ratified. This ratification marks a significant milestone in addressing previous challenges related to fragmentation and security vulnerabilities within the RISC-V ecosystem. With a more stable foundation for operating system support, virtualization, and memory protection, the updated specification enhances RISC-V’s position in modern computing.

Connections Between v1.13 and Recent Patented Innovations

The RISC-V Privileged Architecture Specification v1.13 introduces refinements to privilege levels, memory protection, hypervisor support, and exception handling to strengthen security and performance. One of the most significant refinements in v1.13 is improvements to Hypervisor Mode (H-Mode), which enables more efficient virtual machine (VM) scheduling and reduces execution delays in privileged mode. A related patented innovation, Time-Based Scheduling for Extended Instructions, enhances this feature by optimizing how privileged instructions are scheduled, ultimately reducing context-switch latency. The direct connection between these two advancements is clear: while v1.13 provides the foundation for better hypervisor management; time-based scheduling ensures that hypervisor instructions execute more efficiently. A hypervisor running on a v1.13-compliant RISC-V processor would benefit from reduced instruction stalls and improved VM performance, allowing for smoother virtualization workloads.

Another area where v1.13 and recent innovations align is in memory protection. The specification expands Physical Memory Protection (PMP) and refines virtual memory management to improve access security. Together, these improvements ensure that while v1.13 enforces stricter security policies for memory access, load prediction ensures that privileged memory operations execute efficiently within those constraints. This is particularly important for real-time operating system (OS) environments and security-sensitive applications, where low-latency memory access is crucial to performance and stability.

Additionally, v1.13 introduces refinements to Machine Mode (M-Mode) and Supervisor Mode (S-Mode) execution, making privileged execution more predictable and structured. These updates align with another patented innovation, Out-of-Order Execution for Loop Instructions, which allows the CPU to process system-critical loops more efficiently. The v1.13 spec defines the rules for privileged execution, while out-of-order execution enhances performance within those guidelines. A v1.13-compliant OS kernel running on a CPU that implements out-of-order execution will experience faster privilege mode loops, reducing interrupt handling delays and improving overall system efficiency.

Enhancing RISC-V Performance with Architectural Innovations

Beyond the advancements in the privileged specification, recent patented innovations are further strengthening the RISC-V ecosystem. These enhancements improve memory efficiency, scheduling, and overall execution performance, providing the level of system protection currently enjoyed by proprietary ISA offerings. One such advancement is Time-Based Scheduling for Extended Instructions, which optimizes execution timing for complex privileged instructions. This mechanism ensures smoother operating system performance and reduces bottlenecks in system-level task execution. By lowering the latency in context switching between guest virtual machines, hypervisors can operate more efficiently, leading to better virtualization performance.

The RISC-V Privileged Specification defines a hierarchical privilege model that supports different execution environments. The figure below illustrates the layering of these privilege levels, including OS, SBI, and hypervisor support.

The RISC-V Privileged Specification defines a hierarchical privilege model that supports different execution environments. The figure below illustrates the layering of these privilege levels, including OS, SBI, and hypervisor support.

The introduction of Out-of-Order Execution for Loop Instructions has also significantly improved OS-level and hypervisor performance. This enhancement allows loop instructions to execute non-sequentially, making privileged task handling more efficient. Context switching and interrupt processing benefit greatly from this approach, as it minimizes execution stalls and increases hypervisor responsiveness.

Conclusion

By combining the ratification of the RISC-V Privileged Specification version 1.13 with architectural innovations in memory management and execution efficiency, RISC-V is making significant strides in overcoming past limitations. These advancements position it as a more competitive alternative to proprietary ISAs, paving the way for wider adoption in high-performance computing, cloud infrastructure, and secure enterprise environments.

Also Read:

Harnessing Modular Vector Processing for Scalable, Power-Efficient AI Acceleration

An Open-Source Approach to Developing a RISC-V Chip with XiangShan and Mulan PSL v2

Relationships with IP Vendors

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CEO Interview with Pierre-Yves Lesaicherre of Finwave Semiconductor

CEO Interview with Pierre-Yves Lesaicherre of Finwave Semiconductor
by Daniel Nenni on 03-11-2025 at 10:00 am
Categories: CEO Interviews

Pierre Yves

Tell us a little bit about yourself and your company. 
I am the CEO of Finwave Semiconductor and joined the company in June 2023. I have close to 40 years of experience in the semiconductor industry, and I have worked in France, Japan and the United States. I have been in Silicon Valley for the last 27 years. After 14 years at Philips Semiconductors and NXP, rising up to the executive level, I was the CEO of Lumileds, one of the leading LED companies, for 5 years, and then the CEO of Nanometrics, a Nasdaq-listed semiconductor equipment company, for 2 years.

Finwave Semiconductor is a fabless semiconductor company, born out of MIT research, developing and commercializing proprietary GaN-on-Si technology for the RF communications market. Working with foundry partners in the U.S. and Taiwan, and utilizing the Finwave proprietary epitaxial structure, process technology and device architectures, we manufacture and commercialize high-power RF switches and RF power amplifiers for the cellular handset, telecom infrastructure and aerospace and defense markets, among others.

What was the most exciting high point of 2024 for your company?

The key highlight for Finwave Semiconductor in 2024 was the signing of a strategic technology development and licensing agreement with GlobalFoundries (GF), the world’s leading specialty foundry with a rich history of RF leadership. This partnership merges Finwave’s cutting-edge GaN-on-Si technology with GF’s US-based high-volume manufacturing capabilities and long legacy of RF innovation. The collaboration is focused on optimizing and scaling Finwave’s innovative enhancement-mode (E-mode) MISHEMT technology to volume production at GF’s 200mm semiconductor manufacturing facility in Burlington, Vermont. Finwave’s advanced 200mm GaN-on-Si E-mode MISHEMT platform, which was presented in a technical paper at the CS Mantech industry conference in May 2024, offers exceptional RF performance, delivering excellent gain and efficiency at sub-5V voltages, while ensuring high uniformity across 200mm wafers. Leveraging Finwave’s technology, GF’s comprehensive 90RFGaN platform will deliver high-power density and efficiency, enabling high-performance, optimized devices that save on footprint and cost. This partnership presents a compelling solution for high-efficiency power amplifiers in applications where traditional GaAs and Si technologies fall short, including new higher frequency 5G FR2/FR3 bands, 6G and mmWave amplifiers, and high-power Wi-Fi 7 systems, where superior range and efficiency are critical.

What are the biggest challenges you are seeing in the industry?
As a startup company introducing products in a new and innovative technology (GaN-on-Si), the biggest challenge we face is the willingness of customers to accept these new solutions. Many potential customers for our technology and products tend to prefer using proven technologies, even with inferior performance, rather than adopt our innovative technology and higher performance products. We are partnering with distributors to market our innovative products to as many customers as possible and are starting to gain traction. The partnership we announced last year with GlobalFoundries has created more visibility for Finwave Semiconductor and for GaN-on Si as the promising technology for RF power amplifiers going forward, and our efforts are starting to bear fruit.

How is your company’s work addressing this biggest challenge? 

With the evolution of RF communications systems to higher frequencies for Wifi-7 or 6G communications, there is a need for new solutions to replace several existing semiconductor technologies that are running out of steam as required frequencies increase to the 6 – 20 GHz range. With our 200mm GaN-on-Si low-voltage E-mode MISHEMT platform, we are developing the next generation of RF power amplifiers to replace GaAs HBTs, with a solution that can operate at higher frequencies, with higher power density and efficiency and higher linearity.

In the RF switch market, we are introducing high-power RF switches in the 10-40 W range, with very fast switching and settling times in the hundredths of nanoseconds, broadband operation and significant lower cost that GaN-on SiC solutions, for example.

What do you think the biggest growth area for 2025 will be, and why?
In the RF communications space, architectures are continuing to evolve. We see the adoption of multiple antennas in telecom infrastructure as a very favorable development, and with the power requirements for RF power amplifiers coming down, this should accelerate the adoption of GaN-on Si at the expense of much more expensive GaN-on-SiC solutions, that are more suitable for very high-power applications. With spending increasing in the aerospace and defense markets, we see the need for high-power RF switches increasing in application such as drones, radars and satellites.

How is your company’s work addressing this growth? 
Since the first products we are bringing to market are our GaN-on-Si high-power RF switches, this is where we will experience the highest growth in 2025. We are working with a well-known distributor to market these products to a large array of customers in the telecom infrastructure and aerospace and defense markets. For one of our potential space customers, we recently demonstrated very good radiation hardness performance of our high-power RF switches, which saw no degradation in performance following exposure to a high level of radiation.

The second area of growth for Finwave Semiconductor in 2025 will be the introduction of our first high voltage GaN-on-Si RF power amplifiers for infrastructure applications.

What conferences did you attend in 2024 and how was the traffic?
Finwave Semiconductor participated in Mobile World Congress (MWC) in Barcelona in February 2024 and we were also present at the International Microwave Symposium (IMS) in Washington, DC, in June 2024. We had a very busy MWC last year, with meetings with customers, potential partners, suppliers, the press and industry analysts. With the sampling of our first high-power RF switches, IMS was more focused on potential customers and partners. Traffic was very good at our booth, and we had very fruitful discussions with many interested parties.

Will you attend conferences in 2025? Same or more?
We will attend the same conferences this year, MWC in Barcelona in March 2025 and IMS in San Francisco in June 2025. At MWC 25, we will give progress updates on the transfer of our technology for handset Power Amplifiers to GlobalFoundries, as well as provide an update on the performance and availability of our first RF switches.

How do customers engage with your company?
Today, most of our customers engage with Finwave directly, either by meeting with us at conferences, through mutual contacts or by contacting us through our web site (https://finwavesemi.com). With the signing of a worldwide distribution agreement with one the leading RF distributors, we expect that customers will increasingly engage with our distribution partner, who has offices and sales representatives around the world.

Any final comments?
With our first products being qualified and released for sale, 2025 will be a very exciting year for Finwave Semiconductor. After more than 10 years of technology development, the company is evolving from a technology-focused company to a product and customer centric company, focusing on releasing products to market, engaging with customers and growing revenues.

Also Read:

CEO Interview with Matt Desch of Iridium

CEO Interview with Mike Noonen of Swave Photonics

CEO Interview with Pradyumna (Prady) Gupta of Infinita Lab

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Accellera at DVCon 2025 Updates and Behavioral Coverage

Accellera at DVCon 2025 Updates and Behavioral Coverage
by Bernard Murphy on 03-11-2025 at 6:00 am
Categories: Accellera, Semiconductor Services

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As usual I check in on Accellera activities each year at DVCon. Lu Dai (chair) gave an opening talk at the Accellera lunch, with contributions from other speakers on a few topics. In the afternoon I heard an update on PSS 3.0. What follows is a quick summary with my own musings on behavioral coverage.

Notable non-PSS topics

Karsten Einwich received the Accellera Technical Excellence award for his contributions to SystemC AMS. Interesting to me because an upcoming Innovation blog is based on a paper using SystemC AMS. Pulling AMS verification closer to mainstream verification is a popular theme these days and SystemC AMS adds a complementary system-centric angle.

The Federated Simulation Standard Working Group released a white paper and continues to look for more contributors/participants to help develop ideas. I’m excited to learn more as this evolves, given the ambitious scope of that coupled multi-domain simulation goal, folding in system-wide electronics (aircraft, cars, etc) together with mechanical, fluid dynamics and many other factors that full system OEMs must consider.

The UVM-MS group announced their 1.0 release, aiming to move us closer to a unified verification standard across digital and analog components. This is a very important step, given the increasing contribution analog is making in modern systems, from PLLs and power management, to sensing, to RF.

PSS 3.0

I consider myself fairly technical, though these days primarily in understanding why something is important and the broad strokes of how it is accomplished. I attended the PSS workshop at DVCon knowing quite a bit of the detail would go over my head but in hope that I would pick up a little insight and color. Unfortunately, and perhaps unsurprisingly I wasn’t even a little bit in their target audience. This was very much a hands-on session for practicing PSS users. I can’t blame them. But it did get me thinking more about a cornerstone feature introduced in the 3.0 release – behavioral coverage.

I write quite a bit these days on system verification, as in a big subsystem or SoC, not so much yet on (functional) verification for multi-chiplet systems because published material there is still very thin. However one inescapable fact holds: the bigger the design you need to verify, the more challenging it becomes to develop any sense of verification completeness. Which comes down to coverage, not just “how much testing is enough” but also “what kind of testing is needed”.

Code coverage tells you that you touched every line of code in your RTL. Property checks test for specific state conditions you know you must hit (or not hit). PSS sequences start to probe some paths through the design – initialize an interface, read some data from the input, write that data to the DMA, etc.

But how do you define coverage at the system level? Testing single thread paths through the design is a necessary baseline, but insufficient to account for the concurrency which delivers the main advantage of hardware over software implementations. IO, memory and cache controllers all aim to manage traffic between multiple hosts and multiple targets. As concurrency increases, competition for resources rises adding new complications: latency induced errors, deadlocks, incomplete initialization, prematurely reset flags, memory consistency errors, etc., etc.

Which hints at the kinds of coverage you need to be able to express. Take the memory consistency problem through caching as just one example. You want to check that you have covered all cases where two (or more) threads have successively accessed a cache line through all permutations of read/write and cache flags. If you find this cover has not been exercised, you can bias PSS test generation to make sure it will be exercised. Now extend the same line of thinking to IO subsystem coverage, DDR subsystem coverage, safety and security coverage, anything that spans across the design. A sufficiently expressive way to represent system-level concepts of concurrency-aware coverage is essential to support these needs.

For the more technically able, you can read the detailed spec HERE.

Also Read:

Accellera 2024 End of Year Update

SystemC Update 2024

Notes from DVCon Europe 2024

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CEO Interview with Matt Desch of Iridium

CEO Interview with Matt Desch of Iridium
by Daniel Nenni on 03-10-2025 at 10:00 am
Categories: CEO Interviews

Matt Desch Headshot

Matt Desch is the Chief Executive Officer of Iridium Communications Inc., the only satellite communications company that offers truly global voice and data coverage. He has more than 40 years of experience in telecommunications management, and more than 30 years in the global wireless industry. Joining Iridium in 2006, Desch has been responsible for leading the innovation and growth of Iridium, which includes taking the company public on Nasdaq (IRDM) in 2009, completing the financing and development of Iridium® NEXT, the company’s $3 billion investment in upgrading the Iridium network with powerful new satellites, and launching Iridium Certus®, a multi-service broadband platform enabled by the upgraded constellation.

Tell us about your company?

Iridium is the “OG” LEO satellite company. We’ve been providing critical connectivity to the farthest regions of the world for over 25 years and are still the only mobile voice and data satellite communications network that spans the entire globe. People may know us if they’ve used a satellite phone, but our primary business these days is enabling reliable connections through services like Internet of Things (IoT) that connect people, ships, aircraft and other assets to and from anywhere, in real time. Together with our ecosystem of over 500 partner companies, Iridium delivers an innovative and rich portfolio of reliable solutions for markets that require truly global communications.

What problems are you solving?

Whether it’s in the air, on land, or at sea, Iridium’s satellite network provides weather-resilient, reliable connectivity when and where it matters most. Iridium is first and foremost a safety service. Our unique network and our position in the radio frequency band allow us to serve many markets that struggle to adequately communicate with far away Geostationary (GEO) satellites, or where cellular towers do not reach. Due to the fixed nature of GEO satellites, signal blockages between a user and satellite can easily occur, whereas Iridium’s LEO satellites that are interconnected to each other in space enable uninterrupted communication anywhere in the world – even for ships sailing at high latitudes, adventurers in remote regions, or transoceanic planes far from land.

Our technology continues to get smaller and easier to deploy, such that it’s now able to be in programmed into chips that go directly into consumer devices like smart phones, smart watches and other small devices. Additionally, we are revolutionizing the Position, Navigation and Timing (PNT) field with a solution that protects GPS from jamming and spoofing and provides digital timing signals inside buildings. Our satellite network also tracks airplanes and helps to improve air traffic control across the oceans and many other places.

What application areas are your strongest?

Iridium is the solution for anything that needs reliable two-way connectivity. Cell phone towers – after almost 40 years in operation – only cover about 15% of the worlds surface. People and assets to be managed or tracked stray well beyond that coverage, and Iridium has become the choice for connecting the other 85% of the world, particularly for critical applications and where safety is paramount. You’ll find our technology utilized in all kinds of industries, including maritime, aviation, agriculture, energy, transportation, science and exploration, autonomous systems, first responders and government/military uses. We’re also seeing increasing interest from the automotive sector and everyday consumer devices.

What keeps your customers up at night?

Most of our customers are up at night, because that’s often when disasters strike! Because our network is so reliable, it is mandated in all kinds of safety applications both in the cockpits of airlines and helms of ships and is used to provide first responders with a connection in remote places of the world when it’s needed most. We are proud to provide safety of life services with high reliability, which can alleviate such concerns to our customers.

What does the competitive landscape look like and how do you differentiate?

Iridium’s satellite network and business is quite unique in the satellite industry. For example, Starlink is an exciting new service that focuses on broadband connections, while Iridium focuses on connections to people and assets. We scale down very effectively to very small devices that can even run on battery power, and thanks to our unique spectrum, we operate in any kind of weather and anywhere in the world.

There is also lot of buzz in the industry around D2D (Direct to Device) and NB-IoT. Iridium is positioning our new D2D service as complementary to many of these new emerging services.  Many companies seeking to provide D2D services are still seeking out spectrum and funding and need to launch their satellite networks or need to replenish their satellites frequently to stay in service. Iridium does not face any of these hurdles. Our network is completely global and fully operational – we have a dedicated, global spectrum allocation and already provide millions of customers with uninterrupted and dependable service in every environment. Additionally, our fully programmable network allows us to update our satellites in space to comply with 3GPP standards. Once we turn the switch on, Iridium’s NTN service will be fully operational and truly global from day one. This makes Iridium the ideal solution for chipmakers, MNOs, and customers.

What new features/technology are you working on?

Satellite communications has traditionally been proprietary amongst the various carriers, but that’s starting to change rapidly. Iridium is implementing the 5G narrowband IoT standard connections that are being adopted by smartphone and IoT processing companies to make it even easier for cellular customers to roam onto our network when they’re outside cell coverage. We’re also adapting our Satellite Time and Location® (STL®) service by shrinking it down to a single chip to make it even easier to deploy in cellular base stations, data centers, and other critical infrastructure that depends on GPS timing signals. This gives Iridium the edge to become the de facto global alternate PNT technology to augment other GNSS systems and protect users from the effects of jamming or spoofing.

Additionally, we launched our next generation satellite IoT device – the Iridium Certus™ 9704 Module and Development Kit. This new module is the smallest and most powerful created by Iridium and is ideal for creating new satellite IoT applications, including what we’ve dubbed satellite Artificial Intelligence of Things (AIoT) that require real-time data analysis, analytics and automated decision-making. The Iridium Certus 9704 delivers data, picture, and audio messages for industrial IoT, machine-to-machine applications, and remote personnel use cases – providing two-way IoT services anywhere in the world. It can help our partners make fast and reliable connections to a broad array of applications like predictive maintenance, diagnostics, telemetry monitoring, remote asset tracking, and command and control for uncrewed aircraft, vehicles and vessels.

How do customers normally engage with your company?

As a wholesale operator, we go to market through licensed technology and distribution partnerships. We’re always looking for new channels to market and new technology suppliers to embed our network into their customers’ applications. To learn more, visit: www.iridium.com

Also Read:

CEO Interview with Mike Noonen of Swave Photonics

CEO Interview with Pradyumna (Prady) Gupta of Infinita Lab

Executive Interview: Steve Howington of the Protective, Marine & High Performance Flooring Division of Sherwin-Williams

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Speeding Up Physical Design Verification for AMS Designs

Speeding Up Physical Design Verification for AMS Designs
by Daniel Payne on 03-10-2025 at 6:00 am
Categories: EDA, Siemens EDA

mismatch min

Custom and analog/mixed-signal IC designs have some unique IP and symmetry checking requirements for physical design. Waiting until the end of the IC layout process to verify IP instances for correctness or proper symmetry will cause project delays, so an approach to perform earlier physical verification makes more sense. I’ll share what I learned from reading a recent technical paper from Siemens on the Calibre Pattern Matching tool.

IP reuse is common for SoC design, but what if your IP block has a placement error like the one shown below in a memory cell array?

Symmetry of layout for many analog and mixed-signal designs is critical to achieve the specifications and for reliable operation. Doing manual symmetry checking with measurement tools is a slow and error-prone process. Applying cell mirroring or cloning are great design techniques but still needs to be validated. Circuit symmetry requirements could necessitate that new rule checks be created and may take too much development time.

Calibre Pattern Matching

There’s a tool from Siemens called Calibre Pattern Matching with new capabilities designed for early-stage physical verification of layout. Here’s the flow for when to run the tool.

Shift-left verification with Calibre Pattern Matching

Layout engineers can now verify layout symmetry interactively, saving time by using Calibre Pattern Matching with Calibre RealTime, all without coding specialized rules or resorting to measuring manually. Here’s what interactive symmetry checking looks like in the Cadence Virtuoso layout editor.

Symmetry Checking

When an IP block is instantiated in a layout the placement or alignment issues can be automatically caught with Calibre Pattern Matching, as shown next where two IP instances are verified and one is a 100% match, but the second instance has, what looks like, two metal routes crossing over it resulting in two XOR differences.

IP Mismatch

Your layout designers can ensure that critical IP blocks are placed consistently and verified early in the design. To find a particular layout pattern through a project, the designer can use the “Find Pattern” feature by selecting a layout area, then the Calibre Pattern Matching tool goes to work, all without any coding.

Find Pattern feature

Layout verification errors can overwhelm a designer, so there’s a feature to organize and manage verification data through the Results DataBases (RDB) Classifier, using layout context and groups for similar results, so that repetitive errors like cell arrays are quickly identified.

Example

An unnamed customer had issues with an IC showing audio distortion, and by using Calibre Pattern Matching they were able to quickly find symmetry violations. Manual measurements and cell mirroring weren’t sufficient to find these violations. Early identification improved design quality and reduced layout rework. IP placements were verified early in the design, instead of late, saving time. Less time was required for physical verification, so a shift-left approach really worked.

Summary

Custom and analog mixed-signal designs are complex to layout and can take much engineering time to meet the specifications. By using a methodology of early IP placement verification and interactive symmetry checking, designers can more quickly find and fix issues, cutting down time to market.

Read the technical paper online, Shift Left with Calibre Pattern Matching: Trust in design practices but verify early and frequently.

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Podcast EP277: How Arteris FlexGen Smart NoC IP Democratizes Advanced Chip Design with Rick Bye

Podcast EP277: How Arteris FlexGen Smart NoC IP Democratizes Advanced Chip Design with Rick Bye
by Daniel Nenni on 03-07-2025 at 10:00 am

Dan is joined by Rick Bye, director of product management and marketing at Arteris with responsibility for the FlexNoC family of non-coherent Network-on-Chip IP products. Rick joined Arteris from Arm where he was a senior product manager in the Client Line of Business, responsible for a demonstration SoC and compression IP. Rick has extensive product management and marketing experience in semiconductors and embedded software, having enjoyed roles at Texas Instruments, Broadcom, Silicon Labs, NXP and Foundries.io (now Qualcomm).

Dan explores the capabilities and impact of the new Arteris FlexGen Smart NoC IP with Rick. This revolutionary product uses cutting-edge AI heuristics and machine learning to automate NoC generation. Rick explains this technology allows the development of optimized NoC architectures in minutes to hours without the need for a NoC design expert. Current approaches require substantial NoC expertise and can take days to weeks.

Rick reviews the broad range of applications which benefit from the use of an optimized NoC. Essentially all advanced designs can utilize this technology to reduce time to market while optimizing latency, power and performance with less expert resources. Rick gets into the details of how Arteris FlexGen Smart NoC IP delivers these significant improvements.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.