SemiWiki – Page 2 – The Open Forum for Semiconductor Professionals

July 11, 2025July 17, 2025

CEO Interview with Carlos Pardo of KD

CEO Interview with Carlos Pardo of KD
by Daniel Nenni on 07-11-2025 at 4:00 pm
Categories: Automotive, CEO Interviews

Carlos Pardo has a distinguished career as a manager in the microelectronics industry, excelling in leading R&D teams. He possesses extensive expertise in the high-tech silicon sector, encompassing both hardware and software development. Previously, he served as the Technical Director at SIDSA, where he managed R&D departments, product development, production, and customer support, among other responsibilities. Mr. Pardo also contributed significantly at Hewlett Packard SA Spain as an R&D engineer, handling various business functions, and at DS2 (Design of Systems on Silicon SA).

Tell us about your company

Fabless semiconductor supplier KD provides innovative high-speed optical networking solutions for harsh environments. Founded in 2010 in Madrid, Spain, KD offers its cost-effective technology as fully qualified automotive-grade ASSP, integrating electronics, photonics, and optics in a single IC.

KD’s technology makes use of information theory, innovative digital adaptive algorithms, and analog mixed-signal design to maximize the receiver’s sensitivity. KD innovates in optical coupling and packaging design, which enables integration of optical communications ports in electronic control units using standard printed circuit assembly processes. Together, these offerings allow KD to support high-yield and reliable optoelectronics production in low-cost automotive-grade bulk CMOS deep submicron nodes, and to deliver products to carmakers with low risk, low cost, and short time-to-market.

KD made gigabit communications for step-index plastic optical fiber (SI-POF) a reality for automotive and is now developing its multi-gigabit optimized solution for use with Glass Optical Fiber (GOF) as well.

What problems are you solving?

Data transfer in harsh environments, such as vehicles, presents unique challenges compared to data center environments, including stringent environmental conditions, reliability demands, cost constraints, and high production volumes. These factors have prompted the development of specialized specifications for optical links tailored to automotive applications.

More and more, seamless connectivity of sensors, such as cameras, radar, and LiDAR with central Artificial Intelligence (AI) units, plays a key role in sensor fusion, an integral part of Advanced Driver Assistance Systems (ADAS) and Autonomous Vehicles (AV). Therefore, an optical solution is required as copper communications do not meet these needs.

Optical Ethernet connectivity perfectly solves in-vehicle challenges and electrical interference thanks to its unbeatable electromagnetic compatibility, reliability, and low cost. Fiber is inherently immune to electromagnetic interference and does not emit interference, thus saving an immense amount of additional development time and cost. Regarding temperature, fiber cables withstand extreme temperature ranges from -40 ºC up to +125 ºC for operation ambient. A simpler channel allows for a lower power consumption than copper, thanks to a simpler DSP/equalization and no need for echo cancelling.

For reliability and durability, the selection of the 980 nm wavelength allows VCSEL devices to comply with automotive reliability standards and lifetime. As no shielding is needed, connectors are smaller and mechanically more robust. In contrast to copper, up to 4 inline connectors for a speed of 25 Gb/s and 2 inline connectors for 50 Gb/s can be inserted over a length of 40 meters. With copper, it is only possible to insert 2 inline connectors with a maximum length of 11 meters and 25 Gb/s. In addition, the lower diameter of the OM3 fiber results in significant cost efficiency.

What application areas are your strongest?

KD provides semiconductors for high-speed optical networking for harsh environments. Applications in automotive, home, small and home offices (SOHO), and industrial benefit from KD’s future-proven system solutions for connectivity over fiber optics.

Automotive

Optical fiber technology enhances the automotive industry by improving data transmission speeds, reducing weight, and increasing reliability. It enables high-speed communication between vehicle systems and is immune to electromagnetic interference. Additionally, its lightweight nature improves fuel efficiency and performance. Optical fibers advance vehicle connectivity, safety, and efficiency. Automotive use cases include: communications backbone, smart antenna link, infotainment, Battery Management Systems (BMS), ADAS, cameras, radar, and displays.

Industrial

Optical fiber technology benefits the industrial sector with high-speed, reliable data transmission over long distances, immune to electromagnetic interference. This supports advanced automation, real-time monitoring, and control systems, enhancing operational efficiency. Their durability and low maintenance reduce downtime and operational costs, improving connectivity, safety, and efficiency in industrial applications.

Consumer

KD delivers non-visible 1 Gb/s optical wired connectivity for homes and SOHO. Plastic optical fiber is not electrically conductive and its cross section and bending radius allows its routing through in any duct or collocated next to any wire, even electrical cabling avoiding the use of expensive new ducts or visible trucking inside walls.

What does the competitive landscape look like and how do you differentiate?

Since 2014, with the launch of the first transceiver, KD has led high-speed optical communications for the automotive industry. At present, KD is the only company offering transceivers that comply with the Ethernet standard IEEE Std 802.3cz, which is the standard suitable for gigabit and multigigabit optical communications in automotive.

In addition, we’re evolving from being a fabless IC supplier to component assembly and testing of fully integrated optoelectronic components. We’re setting up a high-volume production site for semiconductors close to our headquarters in Tres Cantos, Spain.

What new features/technology are you working on?

Our R&D is working on two fields, all of them focused to produce high-volume low-cost single-component optical multigigabit automotive transceivers. The first field is the integration of all the electronics – i.e. optoelectronics, analog and mixed signal, digital signal processing, high speed digital interfaces, microprocessors, dependability monitors, etc. – in a single die made in an automotive-qualified bulk CMOS process.

The second field is the development of hybrid packages that can be produced in automated way, where the CMOS die is integrated with VCSEL die, PIN PD die, optical lenses, and mechanical interface that accept the optical fiber ferrules. This hybrid package is very innovative, because it requires of high precision positioning of photonics and lenses, in short cycle times, and all the materials and assembly recipes must be chosen to support reflow temperatures without affecting performance degradation.

In addition, we’re developing a new and innovative optoelectronics packaging technology. It will be applied for the first time to produce the new transceiver IC KD7251 for high-speed automotive optical communications. In setting up several automated pilot plastic packaging lines for optical transceivers, we’re working with other companies on the automated line. The aim is to develop fully automated lines from the wafer, with dicing and backgrinding, with automated transfer between machines and high precision automated alignment in plastic packaging. At this time, we’ve installed a prototype line starting its first prototype assemblies. The final production line with high volume capacity is planned to start production in 2026.

How do customers normally engage with your company?

In the ecosystem with key industry partners, we provide a system solution for optical in-vehicle data transfer. Instead of various port components, customers benefit from the single, complete package.

Gigabit Integrated FOT

For 1 Gb/s optical communications over POF, the integrated KD9351 Fiber Optic Transceiver (FOT), in combination with the proven KD1053 IC, reduces the cost for optical in-vehicle networks at 1 Gb/s, compared to STP (shielded twisted pair of copper wires). Incorporating the transmit and receive optoelectronics into one single component, the KD9351 is an optical transceiver for 100 Mb/s up to 1 Gb/s with a small footprint, enhanced efficiency and flexibility.

Multigigabit Transceiver

The KD7251 is KD’s new ASIC that implements the BASE-AU physical layers, compliant with the IEEE Std 802.3cz™ specification for automotive multigigabit optical communications links over multi-mode glass optical fiber OM3. It‘s a single-chip solution with on-chip optical interface, supporting 2.5, 5, and 10 Gb/s. It includes bridging functionalities to enable the connectivity of MIPI sensors, as cameras and radar (CSI-2®), displays (DSI-2℠), or AI processors (PCIe®) in the vehicle.

Evaluation Boards

For a quick and easy project start, KD delivers various evaluation boards and kits. The EVB9351-SFP is an automotive optical 1000BASE-RHC small form factor pluggable (SFP) module, based on the KD1053 PHY and KD9351 FOT transceivers. The EVB9351AUT platform provides all the functional and performance evaluation capabilities requested by automotive OEMs, TIER-1s or test houses, enabling product designers to successfully evaluate KD’s technology and to shorten the time to market. Based on the NXP SJA1110A switch part, the EVB9351-AUT-SW board is an automotive Ethernet switch with five optical 1000BASE-RHC ports. The EVB7251 is an evaluation board for the new KD7251, allowing optical communications links up to 10Gb/s. It operate as a media converter between the optical BASE-AU port and the SFP+ module.

Contact KD

Also Read:

CEO Interview with Peter L. Levin of Amida

CEO Interview with John Akkara of Uptime Crew

CEO Interview with Dr. Naveen Verma of EnCharge AI

Podcast EP297: An Overview of sureCore’s New Silicon Services with Paul Wells

Podcast EP297: An Overview of sureCore’s New Silicon Services with Paul Wells
by Daniel Nenni on 07-11-2025 at 10:00 am

Dan is joined by sureCore CEO Paul Wells. Paul has worked in the semiconductor industry for over 25 years including two years as director of engineering for Pace Networks, where he led a multidisciplinary, 70 strong product development team creating a broadcast quality video & data mini-headend. Before that, he worked for Jennic Ltd as VP operations, successfully building the team from scratch as the company transitioned to a fabless model. Prior to that, he was responsible for the engineering team and before that he led a team for Fujitsu Microelectronics supporting ASIC customers in Europe and Israel.

Dan explores the recent addition of silicon services to sureCore’s offerings. Paul explains that the memory design skills developed at sureCore create a rich set of core competencies in analog and mixed-signal design, low-power and low-voltage design, characterization and EDA flow development that are well-suited to help customers to develop cutting-edge applications by addressing complex design requirements.

Paul describes the broad range of skills required to develop ultra-low power memory solutions and how these capabilities can directly benefit design teams. He describes example design projects and the impact sureCore was able to make for projects such as edge AI. You can learn more about sureCore’s new silicon services here.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

July 11, 2025July 17, 2025

CEO Interview with Darin Davis of SILICET

CEO Interview with Darin Davis of SILICET
by Daniel Nenni on 07-11-2025 at 6:00 am
Categories: CEO Interviews

With over 30 years of diverse industry experience, Darin leads SILICET, a semiconductor IP licensing firm. He spearheaded a strategic pivot to focus on a seamless LDMOS innovation that delivers unmatched cost, performance and reliability advantages – backed by a robust global patent portfolio. Prior to co-founding SILICET, he held business development roles at Coventor and VLSI Technology.

Tell us about your company?

Silicet develops and licenses IP for semiconductors. The current focus is delivering a scalable source-side LDMOS architecture that minimizes on-resistance for a given breakdown voltage, while simultaneously enhancing Safe Operating Area, mitigating fast-transient EOS and boosting HCI reliability.

Silicet’s IP transparently integrates with any existing BCD node, providing increased device performance at a lower total production cost. With a global IP patent portfolio in the United States, Taiwan, China, and Europe, Silicet’s IP has already been integrated in mature BCD technology offerings.

What problems are you solving?

All MOSFETs have an inherent parasitic bipolar, which can cause catastrophic snapback in Lateral DMOS devices, where the traditional mitigation approach complicates source/body engineering. Silicet’s source-side engineering provides LDMOS designers with several simultaneous advantages:

+ provides the lowest specific on-resistance (RSP)

+ virtually eliminates the parasitic NPN

+ enhances SOA and reliability mechanisms

+ avoids punch through of self-aligned body

+ enables a new Retrograde Body to boost breakdown voltage

+ seamlessly fits into any BCD process

Silicet’s comprehensive solution provides new design trade-offs which are not available from existing device architectures, enabling LDMOS designers to leverage their know-how to optimize LDMOS devices for lowest Rsp at a given BVdss, with increasing benefits as operating voltage decreases from 16V to 5V.

This innovation seamlessly integrates with existing lithography techniques and silicidation process flows, enabling ~25% cost/performance benefits while enhancing reliability – thereby extending the useful life of existing BCD processes and associated installed process equipment.

What new features/technology are you working on?

Silicet’s innovative IP provides multiple “knobs” where LDMOS designers can leverage their know-how to optimize devices for demanding circuit applications.

There are three key aspects to Silicet’s novel BCD technology innovation.

First, Silicet’s Hybrid Source solution minimizes poly-to-poly pitch on the source side, enabling lowest on-resistance for devices at 5v to 28V operating voltage over their conventional counterparts, while providing performance advantages inaccessible from conventional LDMOS devices, opening new opportunities to minimize gate capacitance, leverage high drive current and faster switching speed to optimize GPU/CPU power conversion devices.

A second element is using the Retrograde Body to manipulate the source e-field, providing a new knob to minimize on-resistance for a given drift length, while simultaneously enhancing HCI reliability; which dramatically improves performance and reliability for 5V to 16Vop devices.

The third element takes advantage of novel mobility/carrier injection to provide unique transconductance and very high-drive current benefits – boosting unity gain ~3X. This breakthrough device enhancement avoids the process complications (deep S/D, Halo, LDD, etc.) which are required to overcome short channel effects; significantly simplifying the LDMOS architecture for 28/40/55/65nm BCD solutions.

What does the competitive landscape look like and how do you differentiate?

The primary market for power conversion devices includes systems requiring low on-state resistance and efficient power management, such as servers (DC-DC converters & integrated modules), automotive (motor drivers & load switches) and power management ICs (PMICs) for portable consumer electronics and Class-D audio applications.

Foundries and IDMs are using existing approaches to incrementally refine LDMOS device performance. Our source-only innovation provides a generational leap in benefits, simultaneously delivering superior electrical performance, increased reliability and smaller die size on any BCD node.

“ Silicet doesn’t create the LDMOS design,

we dramatically enhance the LDMOS you design! ”

While our innovation provides more compelling benefits at lower operating voltage and shorter BCD nodes, high voltage (40V to 100V operation) devices can still leverage the enhanced SOA and fast-transient EOS benefits in circuit applications that demand robust and reliable operation – including RF-LDMOS applications.

Silicet’s IP is a gamechanger for LDMOS designers, enabling semiconductor firms to dramatically differentiate performance, cost, and reliability.

Performance Edge: Readily differentiates products in competitive markets
Lowest Rsp, Lowest Gate Capacitance, Highest Drive Current
Faster Time-to-Market: Transparently integrates with any BCD node
Realize “next node” benefits from existing lithography (no capex required),
while reducing technical risks and lowering adoption barriers.
Enhanced Reliability: Ensures robust device operation in challenging applications
The architecture improves Safe Operating Area (SOA), mitigates fast-transient
Electrical Overstress (EOS), and boosts Hot Carrier Injection (HCI) reliability.
Maximize ROI : Leverage Know-How to target diverse LDMOS applications
(e.g. – DC-DC, PMICs, motor drivers, and RF devices)
Achieve higher margins in demanding, cost-sensitive market applications
Optimize resource utilization (device/process/design expertise)

These factors collectively empower semiconductor companies to rapidly achieve distinct competitive advantages, positioning them to quickly capture new opportunities and improve profitability from a single, source-side innovation.

Final comments?

Not only has X-FAB been an instrumental development partner, but also they leveraged their process/device know-how to commercialize 2^nd generation ultra-low Rsp devices in XT018, X-FAB’s leading 180 nm BCD-on-SOI technology platform. This simple solution offers customers Rsp reductions of 50% (5.5V) to 30% (28V), while also enhancing robust operation and reliability in challenging automotive and industrial applications.

X-FAB’s XT018 MV Gen 2

How do customers normally engage with your company?

Silicet is actively engaging strategic partners who either want to uplift an existing BCD process or future-proof an advanced BCD node. Let’s work together to leverage your LDMOS device/process know-how to enable breakthrough solutions.

Contact SILICET

Join the LDMOS evolution!

Also Read:

CEO Interview with Peter L. Levin of Amida

CEO Interview with John Akkara of Uptime Crew

CEO Interview with Dr. Naveen Verma of EnCharge AI

July 10, 2025July 9, 2025

Altair SimLab: Tackling 3D IC Multiphysics Challenges for Scalable ECAD Modeling

Altair SimLab: Tackling 3D IC Multiphysics Challenges for Scalable ECAD Modeling
by Kalar Rajendiran on 07-10-2025 at 10:00 am
Categories: 3D IC, Altair, Chiplet, EDA

The semiconductor industry is rapidly moving beyond traditional 2D packaging, embracing technologies such as 3D integrated circuits (3D ICs) and 2.5D advanced packaging. These approaches combine heterogeneous chiplets, silicon interposers, and complex multi-layer routing to achieve higher performance and integration. However, this evolution introduces significant challenges in modeling, simulation, and reliability assessment due to the massive size and complexity of ECAD data.

A webinar addressing this very topic was recently offered by Altair. Iyad Rayane, senior technical specialist at the company delivered the webinar session.

The Growing Complexity of Modern ECAD Models

Modern IC packages feature thousands of nets across multiple routing layers and use a variety of materials with different physical properties. This results in extremely large ECAD datasets that are difficult to manage and analyze. High-density routing and compact layouts in 3D memory cubes and stacked-die packages also lead to increased power densities and mechanical stresses. Designers face issues like thermal stress, delamination, chip warpage, and solder fatigue, which can severely impact package reliability. Traditional simulation tools struggle to handle these detailed models efficiently, often requiring prohibitively long runtimes and limiting early-stage design exploration.

Challenges in Multiphysics Simulation

Several challenges complicate multiphysics simulation of large-scale 3D IC packages. The volume and complexity of ECAD data strain the capacity of existing tools to import and process models quickly. Accurate analysis requires coupling thermal, mechanical, fatigue, and electromagnetic effects, all while managing heterogeneous materials and thin-layer geometries. Applying fine mesh detail throughout the entire model is computationally expensive, yet necessary in critical regions. Moreover, the shift to system-level floorplanning and heterogeneous integration demands new workflows that traditional EDA tools do not fully support.

Altair SimLab’s Innovative Solution

Altair SimLab addresses these challenges by providing a paradigm-shifting multiphysics environment tailored for large-scale ECAD models. It drastically reduces import times—from hours to minutes—enabling detailed simulation on common desktop hardware. Its metal-mapping technology computes equivalent material properties based on volumetric metal and dielectric content, simplifying fine routing into effective continuous materials without sacrificing accuracy. The software supports hybrid modeling, where signal layers are represented as sheet bodies, vias as wire bodies, and insulating layers as solids, allowing flexible and efficient meshing strategies.

SimLab also incorporates submodeling, allowing designers to run fast global simulations with trace mapping to identify critical areas for detailed local analysis. Displacement and other boundary conditions are transferred from the global model to the detailed submodel, balancing speed with accuracy. Furthermore, the platform integrates thermal, thermal stress, solder fatigue, and package reliability simulations within a single, user-friendly environment. It also interfaces with third-party solvers to extend multiphysics capabilities, providing a comprehensive solution for advanced packaging analysis.

How Altair SimLab Helps Engineers

By combining scalable import, flexible modeling approaches, and multiphysics coupling, Altair SimLab enables engineers to accelerate simulation turnaround and improve prediction accuracy. Designers can quickly explore “what-if” scenarios early in the design cycle, making better-informed decisions about process nodes and package configurations. The efficient data handling allows for detailed reliability analysis of solder bumps, vias, and interconnects, helping identify potential failure points before manufacturing. This approach reduces costly redesigns, shortens development cycles, and ultimately leads to more robust semiconductor products.

Test Case Results: Significant Time Savings

The power of Altair SimLab is evident in real-world test cases. One example involves a large PCB measuring 42 cm by 34 cm with 14 routing layers and over 7,500 nets. SimLab reduced the import runtime from more than four hours on a high-performance computing system to just five minutes on a standard laptop. Another case features a 66 mm by 66 mm silicon interposer with 12 routing layers and over 3,000 nets. Import time was cut from one hour to three minutes. These results demonstrate how Altair’s efficient ECAD data handling enables complex multiphysics simulations to be performed quickly and cost-effectively on everyday hardware.

Summary

As semiconductor packaging continues to evolve toward 3D ICs and heterogeneous integration, simulation tools must keep pace with increasing complexity. Altair SimLab delivers a scalable, integrated platform that bridges the gap between massive ECAD datasets and accurate multiphysics analysis. Its innovative modeling techniques and efficient workflows empower designers to accelerate innovation, optimize reliability, and confidently address the challenges of advanced packaging technologies. By transforming how large-scale ECAD models are imported and analyzed, Altair SimLab plays a critical role in advancing the next generation of semiconductor devices.

Learn more at https://altair.com/simlab

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Altair at the 2025 Design Automation Conference #62DAC

Who Are the Next Anchor Tenants at DAC? #61DAC

Navigating the Complexities of Software Asset Management in Modern Enterprises

July 10, 2025July 11, 2025

AI Booming is Fueling Interface IP 23.5% YoY Growth

AI Booming is Fueling Interface IP 23.5% YoY Growth
by Eric Esteve on 07-10-2025 at 6:00 am
Categories: IP, IPnest, Semiconductor Services

AI explosion is clearly driving semi-industry since 2020. AI processing, based on GPU, need to be as powerful as possible, but a system will reach optimum only if it can rely on top interconnects. The various sub-system need to be interconnected with ever more bandwidth and lower latency, creating the need for ever advanced protocol like DDR5 or HBM memory controller, PCIe and CXL, 224G SerDes and so on.

When you design a supercomputer, raw processing power is important, but the way you access memory, latency and network speed optimization will allow you to succeed. It’s the same with AI, that’s why interconnects protocols are becoming key.

In 2024, the interface IP segment grew by 23.5% to reach $2365 million. Our forecast shows growth for years 2024 to 2029, comparable to 20% growth in the 2020’s. AI is driving the semiconductor industry and Interconnect protocols efficiency are fueling AI performance. Virtuous cycle!

The interface IP category has moved from 18% share of all IP categories in 2017 to 28% in 2023. In 2024, we think this trend will amplify during the decade and Interface IP to grow to 38% of total (detrimental to processor IP passing from 47% in 2023 to 41% in 2029). We forecast total IP to weight $15 billion in 2029 and Interface IP $5.4 billion itself.

As usual, IPnest has made the five-year forecast (2024-2028) by protocol and computed the CAGR by protocol (picture below). As you can see on the picture, most of the growth is expected to come from three categories, PCIe, memory controller (DDR) and Ethernet, SerDes & D2D, exhibiting 5 years CAGR of resp. 17%, 17% and 21%. It should not be surprising as all these protocols are linked with data-centric applications! If we consider that the weight of the Top 5 protocols was $2200 million in 2024, the value forecasted in 2029 will be $4900 million, or CAGR of 17%.

This forecast is based on amazing growth of data-centric applications, AI in short. Looking at TSMC revenues split by platform in 2024, HPC is clearly the driver. Starting in 2020, we expect this trend to continue up to 2029, at least.

Conclusion

Synopsys has built a strong position on every protocol -and on every application, enjoying more than 55% market share, by doing strategic acquisitions since the early 2000’s and by offering integrated solutions, PHY and Controller. We still don’t see any competitor in position of challenging the leader. Next two are Cadence and Alphawave, with market share in the 15%, far from the leader.

In 2025 and after, we think that a major strategy change will happen during the decade. IP vendors focused on high-end IP architecture will try to develop a multi-product strategy and market ASIC, ASSP and chiplet derived from leading IP (PCIe, CXL, memory controller, SerDes…). Some have already started, like Credo, Rambus or Alphawave. Credo and Rambus already see significant revenues results on ASSP, but we will have to wait to 2026, at best, to see measurable results on chiplet.

Also Read:

Design IP Market Increased by All-time-high: 20% in 2024!

AI Booming is Fueling Interface IP 17% YoY Growth

Semi Market Decreased by 8% in 2023… When Design IP Sales Grew by 6%!

July 9, 2025July 9, 2025

Building Trust in Generative AI

Building Trust in Generative AI
by Daniel Payne on 07-09-2025 at 10:00 am
Categories: EDA, Events, Perforce

AI technology was prevalent at DAC 2025, but can we really trust what Generative AI (GenAI) is producing? Vishal Moondhra, VP of Solutions Engineering from Perforce talked about this topic in the Exhibitor Forum on Monday, so I got a front row seat to learn more.

Vishal started out by introducing the four challenges and risks of using GenAI for semiconductor design:

Liability questions arise over who owns the IP in a new design, how the IP is being licensed, and whose data is being used to train an AI model. Companies need to know how AI models were trained, so that training is a traceable procedure. What if a new IP block was created by GenAI and it contains an error, lengthening the time to production and increasing development costs? When mixing both external IP with internal IP, are there data quality concerns?

Establishing trust for using AI to train models requires three pillars:

Clear and auditable data provenance for all training datasets
Complete traceability of IPs and IP versions
Secure and compliant use of both internal and external IP

With the Perforce methodology, a semiconductor team will use IP lifecycle management to provide the proper provenance for training datasets. Team members define their design in terms of IPs, establishing provenance for each IP, providing complete traceability down to the file level, along with its history. Data contamination of the dataset is avoided by adding and enforcing rules about IP usage. Incremental training is supported, giving users a history of what changed since the last training set. All of this reduces the risk of using GenAI to train models for semiconductor design.

Vishal spoke about what an IP object could be: processor, memory, register, library cell, PDK, chiplet, embedded SW, or firmware. Adding metadata to an IP block enables permissions to be set, technical specs to be added, properties to be defined, usage set, versions updated, and even bugs to be tracked. IP lifecycle management enables high-level abstract IPs to have dependencies, form subsystems and use hierarchy. Even the environment configuration is stored as workspace settings, documentation, startup files and scripts, or templates.

The AI training process was presented, showing the flow of how files are created and models formed by using scripts and actions. With Perforce, a completely traceable flow of data creates new training data, and the pipeline can be run multiple times.

With an IP Lifecycle Management (IPLM) flow, all data sources can be modeled as IPs. Each derived data source becomes the parent of the source, and the preprocessed data is the parent of raw data, while training data is the parent of the preprocessed data. Both the training and final models are also modeled as IPs. Each script that runs a data transformation and model training becomes an IP.

Using IPLM in AI/ML training pipelines allows semiconductor teams to manage all of their data and dependencies, creating a series of parent-child relationships. Data management can be mixed between tools like Perforce P4 and Git based on user preferences. Teams can quickly build new workspaces with the right data, scripts, and models each time. This whole ecosystem is fully traceable, so you always record the data source, know how the derivatives were assembled, have a record of all parameters, and ensure that all models are fully traceable and reproducible. Engineers learn how to add metadata to the training projects, like the training parameters, results, history of runs and runtimes. You can view and model the model lineage to see which project was derived or copied, and where it came from.

Summary

GenAI is sweeping across the EDA and IP landscape, so it’s worth questioning the integrity of this new paradigm. The software team at Perforce has thought about each trust challenge and come up with an approach to make GenAI model development and usage trustworthy. Learn more about Perforce and semiconductor design by visiting their website.

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Podcast EP296: How Agentic and Autonomous Systems Make Scientists More Productive with SanboxAQ’s Tiffany Callahan

Podcast EP296: How Agentic and Autonomous Systems Make Scientists More Productive with SanboxAQ’s Tiffany Callahan
by Daniel Nenni on 07-09-2025 at 8:00 am

Dan is joined by Dr. Tiffany Callahan from SandboxAQ. As one of the early movers in the evolving sciences of computational biology, machine learning and artificial intelligence, Tiffany serves as the technical lead for agentic and autonomous systems at SandboxAQ. She has authored over 50 peer-reviewed publications, launched several high-impact open-source projects and holds multiple patents.

Dan explores the foundation of the agentic and autonomous systems SandboxAQ is developing with Tiffany. She describes the impact of large quantitative models, or LQMs, particularly in drug discovery and material science research. Unlike LLMs that are trained on broad-based Internet data for text reasoning, LQMs are trained on first principles of physics, chemistry and engineering, This creates AI that can reason about the physical world. SanboxAQ aims to deploy this technology as an adjunct to existing research experts by simulating and predicting physical outcomes on a massive scale. This provides scientists with tools that are both grounded in physical science and generative, facilitating more targeted and efficient research,

You can learn more about this unique company and the impact it aims to have on advanced research here.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

July 9, 2025July 15, 2025

Insider Opinions on AI in EDA. Accellera Panel at DAC

Insider Opinions on AI in EDA. Accellera Panel at DAC
by Bernard Murphy on 07-09-2025 at 6:00 am
Categories: Accellera, AI, Events, Semiconductor Services

In AI it is easy to be distracted by hype and miss the real advances in technology and adoption that are making a difference today. Accellera hosted a panel at DAC on just this topic, moderated by Dan Nenni (Mr. SemiWiki). Panelists were: Chuck Alpert, Cadence’s AI Fellow driving cross-functional Agentic AI solutions throughout Cadence; Dr. Erik Berg, Senior Principal Engineer at Microsoft, leading generative AI strategy for end-to-end silicon development; Dr. Monica Farkash, AMD fellow, creator of ML/AI based solutions to reshape HW development flows; Harry Foster, Chief Scientist for Verification at Siemens Digital Industries Software; Badri Gopalan, R&D Scientist at Synopsys, architect and developer for coverage closure and GenAI related technology; and Syed Suhaib leading CPU Formal Verification at Nvidia.

Where are we really at with AI in EDA?

In 2023 everyone in EDA wanted to climb on the AI hype train. There was some substance behind the stories but in my view the promise outran reality. Two years later in this panel I heard more grounded views, not a reset but practical positions on what is already in production, what is imminent, and what is further out. Along with practical advice for teams eager to take advantage of AI but not sure where to start.

I like Chuck’s view, modeling AI evolution in EDA like the SAE model for automotive autonomy, progressing through a series of levels. Capabilities at level 1 we already see in production use, such as PPA optimization in implementation or regression optimization in verification. Level 2 should be coming soon, providing chat/search help for tools and flows. Level 3 introduces generation for code, assertions, SDCs, testbenches. Level 4 will support workflows and level 5 may provide full autonomy – someday. Just as in automotive autonomy, the higher you go, the more levels become aspirational but still worthy goals to drive advances.

According to Erik, executives in Microsoft see accelerating adoption in software engineering and want to know why the hardware folks aren’t there yet. Part of the problem is the tiny size (~1%) of the training corpus versus the software corpus, also a significantly more complex development flow. Execs get that but want hardware teams to come up with creative workarounds, to not keep falling further behind. An especially interesting insight is that in Microsoft teams are building more data awareness and learning how to curate and label data to drive AI based optimizations.

Monica offered another interesting insight. She has been working in AI for quite a long time and is very familiar with the advances that many of us now see as revolutionary. The big change for her is that, after a long period of general disinterest from the design community, suddenly all design teams want these capabilities yesterday. This sudden demand can’t be explained by hype. Hype generates curiosity, urgency comes from results seen in other teams. I know that this is already happening in implementation optimization and in regression suite optimization. Results aren’t always compelling, but they are compelling often enough to command attention.

Harry Foster added an important point. We’ve had forms of AI in point tools for some time now and they have made a difference, but the big gains are going to come from flow/agentic optimizations (Erik suggested between 30% and 50%).

Badri echoed this point and added that progress won’t just be about technical advances, it will also be about building trust. He sees agents as a form of collaboration which should be modeled on our own collaboration. While today we are allergic to the idea of any kind of collaboration in AI, he thinks we need to find ways to make some level of collaboration more feasible. Perhaps in sharing weights or RAG data. Unclear what methods might be acceptable and when, but more will be possible if we could find a path.

Syed offered some very practical applications of AI. Auto-fixing (or at least suggesting fixes) for naming compliance violations. At first glance this application might seem trivial. What’s important about a filename or signal name? A lot, if tools use those names to guide generation or verification, or AI itself. Equivalence checking for example uses names to figure out correspondence points in a design. At Nvidia, among other applications they use AI to clean up naming sloppiness, saving engineers significant effort in cleanup and boosting productivity through improved compliance. AI is also used to bootstrap testbench generation, certainly in the formal group.

Audience Q&A

There were some excellent questions from the audience. I’ll pick just a couple to highlight here. The first was essentially “how do you benchmark/decide on AI and agentic systems?” The consensus answer was to first figure out in detail what problem you want to solve and how you would solve it without AI. Then perhaps you can use an off-the shelf chatbot augmented with some well-organized in-house RAG content. Maybe you can add some fine-tuning to get close to what you want. Maybe you can use a much simpler model. Or if you have the resources and budget, you can go all the way to a customized LLM, as some companies represented on this panel have done.

Design houses have always built their own differentiated flows around vendor tools, often a mix of tools from different vendors. They build scripting and add in-house tools for all kinds of applications: creating or extracting memory and register maps, defining package pin and IO muxing maps and so on. In-house AI and particularly agentic AI could perhaps over time supersede scripting and even drive new approaches to agents for product team-specific tasks. EDA agents will likely also play a part in this evolution around their own flows. For interoperability in such flows one proposal was increased use of standards like MCP.

Another very good question came from the leader of a formal verification team who is ramping up a few engineers on SVA, while also aiming to ramp them up on machine learning. His question was how to train his team in AI methods, a challenge that I am sure is widely shared. Erik said “ask ChatGPT” and we all laughed, but then he added (I’ll roughly quote here):

“I’m 100% serious. I’ve had people complain, where’s the help menu? I said, just ask it your question. And if you’re having trouble with your prompts, give it your prompt and say, this is the output that I want. What am I doing wrong? It will be very frank with you. Use the tool to learn.”

Now that is a refreshing perspective. A technology that isn’t just useful for individual contributors, but also for their managers!

I’m not always a fan of panels. I often find that they offer few new insights, but this panel was different. Good questions and thought-provoking responses. More of these please Accellera. Benchmarking AI and agentic systems sounds like one topic that would draw a crowd!

See Replay: “Insider Opinions on AI in EDA: Accellera Panel at DAC”

Also Read:

Accellera at DVCon 2025 Updates and Behavioral Coverage

Accellera 2024 End of Year Update

SystemC Update 2024

July 8, 2025July 9, 2025

Revolutionizing Simulation Turnaround: How Siemens’ SmartCompile Transforms SoC Verification

Revolutionizing Simulation Turnaround: How Siemens’ SmartCompile Transforms SoC Verification
by Kalar Rajendiran on 07-08-2025 at 10:00 am
Categories: EDA, Siemens EDA

In the race to deliver ever-larger SoCs under shrinking schedules, simulation is becoming a bottleneck. With debug cycles constrained by long iteration times—even for minor code changes—teams are finding traditional flows too rigid and slow. The problem is further magnified in continuous integration and continuous deployment (CI/CD) environments, where each commit may trigger a full simulation cycle, consuming unnecessary time and compute resources. Siemens EDA’s SmartCompile aims to break this logjam.

SmartCompile: A Paradigm Shift in Simulation Workflows

Siemens EDA addresses this critical challenge with SmartCompile, a feature of its Questa One simulation environment. Rather than iterating on top of the traditional flow, SmartCompile introduces a fundamental redesign of the compile-optimize-simulate pipeline. It adopts a modular and highly parallel approach to managing design verification tasks, enabling faster turnaround times without compromising design integrity.

The foundation of SmartCompile’s innovation lies in its ability to break apart large, monolithic processes into discrete, manageable units. This divide-and-conquer philosophy allows each component—be it compilation, optimization, or test loading—to be performed independently and in parallel, dramatically improving simulation readiness and design iteration velocity.

Enhancing Performance through Incremental Workflows

One of the most significant advantages of SmartCompile is its incremental compilation and optimization strategy. By utilizing timestamp tracking and smart signature analysis, the system identifies precisely which parts of the design have changed and compiles only those. This targeted approach drastically reduces build times across repeated verification cycles and streamlines test and debug cycles for developers.

Furthermore, the introduction of separate test loading revolutionizes how simulation teams manage test scenarios. Instead of recompiling the entire testbench for each new test, SmartCompile allows users to reuse the base compilation and optimization while isolating and processing only the new or modified tests. This capability significantly accelerates the test development process and promotes faster feedback loops during debugging.

Tackling Design Scale with Intelligent Partitioning

As designs increase in complexity, optimization becomes one of the most time-consuming stages of verification. To combat this, SmartCompile introduces the concept of AutoPDU—automatically pre-optimized design units. This feature partitions large designs into smaller, manageable units that can be independently compiled and optimized. When changes are made, only the affected units need to be processed again, leaving the rest untouched. This approach not only reduces the time required for each optimization run but also allows the process to be distributed across multiple grid computing nodes. By enabling parallelism at the design unit level, AutoPDU transforms how large SoCs are handled, dramatically decreasing overall simulation setup time.

Boosting CI/CD Efficiency with SmartCompile

Questa One’s SmartCompile is uniquely suited to enhance CI/CD (Continuous Integration and Continuous Deployment) pipelines in hardware design. By enabling rapid, incremental builds and leveraging precompiled design caches, SmartCompile allows frequent code check-ins to be verified quickly without reprocessing the entire design. Its intelligent reuse of elaboration and optimization data significantly reduces turnaround times in automated workflows. This capability ensures that regression tests, triggered automatically by CI systems, execute efficiently, allowing development teams to scale their productivity while maintaining robust quality assurance throughout the design lifecycle. This feature is particularly valuable for large teams and distributed projects, where multiple engineers may need to reproduce simulation environments “on demand—without losing valuable time.”

Flexible Configuration for Advanced Use Cases

In many simulation environments, different abstraction levels—such as RTL, gate-level, or behavioral models—are needed for different verification tasks. Traditionally, switching between these configurations requires recompilation and re-optimization. SmartCompile’s dynamic reconfiguration capability removes this barrier by allowing blocks to be swapped in or out at simulation time. This feature lets users pre-compile various block configurations and select the appropriate one during elaboration, enabling greater flexibility and reducing redundant processing.

Additionally, debug data generation in SmartCompile is no longer tightly coupled with optimization. Engineers can generate debug files on demand, rather than each time a build is processed. This not only improves resource efficiency but also empowers teams to target their debugging efforts more precisely.

The Business Value of Smarter Simulation

The cumulative effect of these innovations is substantial. SmartCompile enables design teams to iterate faster, simulate more often, and reduce wasted compute cycles. With its support for incremental workflows, distributed optimization, configuration flexibility, and CI-friendly features, it presents a compelling solution for organizations looking to scale their design verification capabilities without scaling their costs. This means faster time-to-market, reduced operational expenses, and more reliable development pipelines. As competition in the semiconductor market intensifies, the ability to verify designs quickly and efficiently becomes a critical differentiator. By integrating SmartCompile into their verification strategy, companies can better manage complexity while maintaining agility and performance.

Summary

Simulation has always been a cornerstone of digital design verification, but as designs grow more complex and development timelines shrink, traditional flows no longer meet the needs of modern engineering teams. Siemens EDA has recognized this shift and responded with a comprehensive and intelligent approach in SmartCompile. It tackles the fundamental inefficiencies of traditional workflows, enabling faster, smarter, and more scalable verification from the ground up.

Also Read:

Siemens EDA Unveils Groundbreaking Tools to Simplify 3D IC Design and Analysis

Jitter: The Overlooked PDN Quality Metric

DAC News – A New Era of Electronic Design Begins with Siemens EDA AI

July 8, 2025July 7, 2025

Arteris Simplifies Design Reuse with Magillem Packaging

Arteris Simplifies Design Reuse with Magillem Packaging
by Mike Gianfagna on 07-08-2025 at 6:00 am
Categories: Arteris, Events, IP

Many know Arteris as the “network-on-chip”, or NoC, company. Through acquisitions and forward-looking development, the footprint for Arteris has grown beyond smart interconnect IP. At DAC this year, Arteris highlighted its latest expansion with a new SoC integration automation product called Magillem Packaging. The announcement focused on substantial new capabilities to simplify and speed up the process of building advanced chips used in everything from AI data centers to edge devices. I had an opportunity to visit Arteris at DAC and to speak with some of the executives there. Let’s examine how Arteris simplifies design reuse with Magillem Packaging.

The Announcement

The announcement made at DAC pointed out that chip design is becoming increasingly complex, with more components, higher performance demands, and tighter timelines. There is no argument there. The release states that Magillem Packaging helps engineering teams work faster and more efficiently by automating one of the most time-consuming parts of the design process: assembling and reusing existing technology.

Going deeper, Magillem Packaging enables IP teams to quickly and reliably package and prepare hundreds or even thousands of components for integration into a single chiplet or chip design, including new, existing, or third-party IP blocks.

Some of the key capabilities of this new product from Arteris are:

IP reuse with comprehensive IP, subsystem, and chiplet packaging in a reusable format, including configuration, implementation, and verification for incremental and full packaging with a proven methodology.
IEEE 1685-2022 generation is correct-by-construction without requiring any pre-requisite IP-XACT expertise. Standard compliance and data consistency are ensured by construction and assessed with a built-in Magillem checkers suite.
Scalable and fully automated generation of IP packaging for reused and new IP blocks, with support for legacy 2009 and 2014 versions of the IEEE 1685 standard, with intuitive graphical editors enabling fast viewing and editing of IP block descriptions.

Ecosystem Support

Arteris technology is agnostic and works across the ecosystem to ensure ease of integration for end customers. Among those voicing support for the new capability are:

Andes Technology

“Andes Technology is recognized for our comprehensive family of RISC-V processor IP and customization tools that empower customers to easily differentiate their SoC designs,” said Marc Evans, director of business development & marketing at Andes Technology Corporation. “The latest IP-XACT 2022 specifications enable structured automation, optimizing IP packaging and integration. Magillem Packaging complements Andes’ commitment to streamlined workflows, enabling faster and more reliable SoC development.”

MIPS

“The MIPS Atlas portfolio is engineered for high-efficiency compute in autonomous, industrial, and embedded AI applications, where rapid integration and design reuse are critical,” said Drew Barbier, VP & GM of the IP Business Unit at MIPS. “Arteris Magillem Packaging, with its automation of IP-XACT 2022-compliant packaging and support for industry standards, aligns with customer needs to accelerate SoC development. Together, we empower customers to streamline IP integration, reduce design complexity, and bring innovative silicon to market faster.”

More From the Show Floor at DAC

While visiting Arteris at DAC, I had the opportunity to discuss this announcement with two key members of the management team in more detail.

Insaf and Andy at the SoC Integration pod in the Arteris booth

Insaf Meliane is a product management and marketing director at Arteris. Before joining the product team, she was a field application manager, supporting customers with complex SoC design integration. She holds an engineering degree in microelectronics option system-on-chips from École Nationale Supérieure d’Electronique et de Radioélectricité de Grenoble.

Andy Nightingale is the VP of product marketing at Arteris. Andy is a seasoned global business leader with a diverse engineering and product marketing background. He’s a Chartered Member of the British Computer Society and the Chartered Institute of Marketing and has over 35 years of experience in the high-tech industry.

We began by discussing the overall reaction to Magillem Packaging at DAC. Interest was high, and reactions were quite positive. There has been an increase in momentum for IP-XACT. The features of the latest IP-XACT 2022 version have helped. Arteris has been a major supporter of this standard, and the new capabilities delivered by Magillem Packaging have helped as well.

Insaf explained that Magillem Packaging leverages the Arteris Magillem Platform by integrating parts of Magillem Connectivity and Magillem Registers to create the new product. The figure below provides an overview of the platform and how the pieces fit together. Insaf described the significant benefits this new product delivers. The image at the top of this post includes a summary of the key benefits.

Arteris SoC Integration Automation with the Magillem Platform

She went on to explain the significant automation provided by Magillem Packaging. Keeping track of a complex system’s connectivity and interface requirements is a daunting challenge. With Magillem Packaging, these details are automated and verified as correct. She described how the new version of IP-XACT 2022 delivers substantial new capabilities, and Magillem Packaging leverages all these capabilities in an automated way. There is no need for the user to learn all those details.

She summarized some of the key benefits of the new tool as follows:

Effortless, scalable automation: handles both legacy and new IPs for a smoother assembly, faster scaling for large designs with less risks, reducing the potential for human error, and increasing efficiency
Single source of truth specification: ensures consistency across various uses, bringing up immediate collaboration across the relevant teams, and catching errors before they become costly roadblocks.
Safely, easily, and quickly adapt to changes: with a robust, rapid, highly iterative design environment. It reduces effort and rework to focus on core business, leverage technical expertise, and dream up what comes next.

She also pointed out that Arteris is working with various IP providers to ensure full support for IP-XACT 2022 so customers can fully enjoy its benefits.

I then explored the bigger development programs at Arteris with Andy. He described some of the joint efforts between the NoC and Magillem Connectivity teams. This work improves the target system’s overall connectivity management and helps with the complex verification tasks, thanks to the consistent views created across simulation, FPGA, emulation, synthesis, and fault injection.

Andy couldn’t disclose too many details about upcoming enhancements, but this is an area to observe going forward, and Arteris is leading the charge.

We concluded our discussion with a broader view of multi-die design requirements. On SemiWiki, you can learn more about how Arteris responds to these challenges. Some eye-opening statistics about Arteris technology include that over 200 customers have completed 860 design starts and shipped about 3.75 billion units.

To Learn More

Managing all the information associated with the new heterogeneous semiconductor systems under development can be a considerable challenge. One error can jeopardize the entire project. If these issues keep you up at night, you want to learn more about what Arteris is doing with its Magillem technology. You can read the press release announcing Magillem Packaging here. And you can learn more about this new product here. And that’s how Arteris simplifies design reuse with Magillem Packaging.

Also Read:

Arteris Expands Their Multi-Die Support

How Arteris is Revolutionizing SoC Design with Smart NoC IP

Podcast EP277: How Arteris FlexGen Smart NoC IP Democratizes Advanced Chip Design with Rick Bye