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Tanner EDA at DAC

Tanner EDA at DAC
by Daniel Payne on 06-14-2011 at 2:40 pm
Categories: EDA, Tanner EDA

Intro
For 22 years now Tanner EDAhas been in the business pf offering tools for AMS and MEMS designers. I learned what’s new at DAC on Tuesday morning.

Notes
Nicholas Williams – Director of Product Management

Tanner EDA front end: S-Edit integrates with Berkeley Fast Analog Simulator
W-Edit – is the waveform viewer

Who is Tanner – full suite for custom IC design
– 22 years in industry
– AMS focus
– First on Windows (also Linux)
– 20K licenses, 67 Countries

S-Edit – Schematics (Import Mentor and Cadence legacy data)
– Cross probe between schematics and layout
– Checking
– Launch simulation, make measurements

Berkeley Analog Fast Spice (AFS)
– About 5 to 10X faster than SPICE
– 10M element capacity

W-Edit – setup measurements
– Scripting for sophisticated measurements
– Built in measurement functions

Layout editor – L-Edit

SDL – schematic driven layout

HiPer DevGen – layout generators

HiPer Verify – Netlist extraction tool (Takes Calibre or Assura decks as inputs)

HiPer PX – parasitic extraction
Why choose Tanner?
– Economic price
– Installed base
– PDKs

Why not your own Fast SPICE?
Easier to partner with a leader already.

John Zuk

Last year – Hiper DevGen (Dublin based, IC Mask)
– This year added: Resistor arrays for matching, adding mosfet array generators, adding current mirrors
– Focus is on analog blocks

SDL – read in netlist analyze it, find current mirrors, use Hiper Devgen automatically

Interactive DRC – close enough to final rules, then HiPer Verfiy in batch to complete the layout verification

Open Access – in integration now, L-edit is first, S-edit is next. PC –based we donated technology that they didn’t even have.
– Took more effort than anticipated.
– Working with Si2 to define what OA should be
– iDRC and iLVS are in the future, after L-edit and S-edit, waiting to be embraced
– IPL Constraints – looking at that as well, designer notes, will be part of S-edit
– V16 is due in October and will be the first to support OA

iPDK – Looks more practical than Open PDK
– In V17 this would be supported in 2012, beta by June 2012

Resell BDA tool – 1st line of support,

OEM – parasitic extraction tool (Tuo Delft in Netherlands, HiPer PX extraction)
– Hiper devgen

Tanner version – scaled down version limited by processors and total elements, lighter version, token based
– Worldwide sales agreement
– First copy to be sold very soon

Fiscal Year – 140 new customers in 2011

Greg

3D field solver as an upgrade

V16 – multi user now available

OA – realtime collaboration on the same database

ClioSoft – what is the cost of this?

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Blue Pearl at DAC

Blue Pearl at DAC
by Daniel Payne on 06-14-2011 at 1:03 pm
Categories: Uncategorized

Intro
It’s all about analyzing RTL and creating timing constraints at Blue Pearl, so I stopped by their booth on Tuesday morning to get an update on what’s new for 2011.

Notes

What’s New in 2011 at Blue Pearl Software

New designer experience, ease of use. Brand new GUI.

Work with RTL to synthesis tools to get best timing in your layout.

GUI – windows 7 and Linux, same look and feel.
–All new in 2011
–Inline help

Blue Pearl Analyze – Linting, race checks,
–Demo: support languages: verilog 1995, 2001, 2005, System Verilog, VHDL 2008
–Read your libraries
–Modules can be grey box or black box
–Clocks can be automatically identified or manually setup
–Schematic view auto generated based on your source code
o Cross probe between RTL and schematic view
o Quick browsing of hierarchy
–About 250 checks are run on the source code
o LInting
o Low power
o Timing constraints
o DFT
o CDC
o Etc
–Visual Verification
o 200K gate design
o Lint, structural checking, CDC analysis, CDC identification,
o Using FlexLM for licensing
o False path, multicycle paths
o Only 45 seconds needed on a laptop
o Faster than others who synthesize to gates, instead of staying at RTL level
o About 10X faster than other approaches (Atrenta)
o Run the tool from the bottom up
o All the CDC unsynched paths are shown in text list, clicking creates a schematic view
o Designer decides what to do with the violations to accept or ignore
o User can filter the messages, warnings, errors (Use rules, patterns, modules, names, severity)

Blue Pearl Create –
–Creates an SDC file automatically
–All false paths are displayed in a tree view and schematic view
–Assertions are shown for each false path
–An audit trail explains why the control values are creating a conflict
–The SDC file will help other tools (STA, Synthesis, ATPG) to reduce their run times
–Can save weeks of time compared to manual SDC constraint generation
–200K design run in minutes
–Customers: Microsoft, KLA, Cypress Technologies

Usage: Block level designs, run on PC or Linux boxes

Users: IC (Constraint generation), FPGA (Help on large designs like Virtex with 10M gates, PC and Windows. Find Clock Gating opportunities), IP (want more tool flexibility)

Version 5.0 (Blue Pearl Software Suite)

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Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 2 of 2)

Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 2 of 2)
by Daniel Payne on 06-14-2011 at 12:43 pm
Categories: Uncategorized

Dipesh Patel, VP Engineering, ARM Physical IP

Consumer demand for smart devices, short life cycles (SmartPhone, Tablets, Internet screens)

Processor speeds: 1GHz to 1.5GHz
SOC Memory: 600MHz to 1.2 GHz
How power efficient?
How is the layout density?

Standard Cells: multi-channel, multi-vt (4) libraries

Memory Compilers: single port, multi port, ROM
7 families to choose from

28nm libraries nominal VDD of 1.0V

Processor Optimization Package (POP)
–Physical IP
–Reference flow, documentation, guidelines
–ARM certified benchmarking

Cortex A9 – 1.3GHz performance now

Silicon Validated – created Test Chips for GLOBALFOUNDRIES and Samsung at 32nm and 28nm nodes

Fab Synch – migrate any design from one fab to another one

Ready to Start – http://designstart.arm.com/

Andy Potemski – Director of Global Technical Services, Synopsys

Lynx Design System – About 2 years old, design system of silicon realization tools
–Off the shelf productivity
–A core flow for building an ARM Cortex A9
–Configure Flow with High Performance Libraries and IP
o Use DesignWare or 3[SUP]rd[/SUP] party IP
–Optimize the methodology for design specific needs
–Optimize the design floor plan in the context of the full chip
o Quad core A9 floor plan
o Explore and optimize
–Optimize performance and power
o Detailed routing
o Trend analysis of design metrics like power, area, speed
–Optimize the design flow turn around time
o Track execution of all tools
o Analyze the profile of each tool
o Identify tool bottlenecks

Q: The ARM brochure says up to 25% higher performance or 80% less power. Can I get both?
A: That’s very difficult. It’s really a tradeoff that you have to choose between.

Q: How will work on 28nm help 20nm, especially in light of litho effects?
A: We’re collaborating early in the development of 20nm to learn from our Common Platform partners. Double patterning is needed for 20nm. Expect to see a 50% improvement in density going from 28nm to 20nm node. Computational lithography required on 20nm. Another level of litho complexity make architectural exploration a challenge. Trying to minimize the number of double patterning layers required.

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Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 1 of 2)

Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 1 of 2)
by Daniel Payne on 06-14-2011 at 12:26 pm
Categories: Uncategorized

Intro
The 28nm nodes is ready with foundry silicon, IP and EDA tools. Tuesday morning at the DAC breakfast I learned more about the 28nm eco-system.

Notes
Why 32/28nm
–Lower power, high integration requirements, mobile applications

What is Ready?
–IP is qualified (ARM, Memories, Foundation IP, SNPS IP, PDKs)
–August 2010 SNPS and GLOBALFOUNDRIES at 28nm
–June 2011 SNPS and ARM at 28nm (A15 core)
–June 2010 Samsung at 32nm with SNPS tools
–Common Platform – Lynx tool flow is ready, January 2011
–June 2011 GLOBALFOUNDRIES ready at 28nm
–Samsung qualifies 28nm
–Samsung at 35 tape outs at 32nm to date

Anna Hunter, VP Samsung
Technology Roadmap
–32nm LP: ready, HKMG process
o SRAM at .149um*um, tiny size
o Good yield at 86%
o Matches SPICE results
–28nm LP: ready
o Same HKMG as 32nm node
o Works with ARM IP and SNPS tool flow
–28nm LPH: under development (low power, plus higher performance modules)
o Will be up to 50% faster (with more leakage, 2.3X)
o Same HKMG
o Added strain to silicon
o Shuttles starting now
–20nm LPM: in development, PDK evaluation now. Ready by end of 2012.

Lynx – flow of SNPS tools and IP management, used by Samsung internally too

ARM CPU – 45nm >1GHz on Cortex A9
–32/28nm >1.35GHz on Cortez A15
–28nm LPH, >2.0GHz Cortex A15

IP Portfolio – High Speed, Memory, Mixed Signal
–ARM, SNPS<

Going from 45nm to 32nm more than 50% improvement in SRAM bit cell size

Turn key solutions from Samsung
–Design, Fab, Wafer Sort, Assembly, Final Test
–Working on TSV technology for higher integration on packaging

MPW – Run every quarter for 32nm and 28nm
–Will start 20nm in September

Fab sites – Korea( 20nm), Texas (40K wafers per month)

Jim Ballingall, VP Marketing at GLOBALFOUNDRIES
–AMD lead product used HKMG technology, quad core CPU with GPU integrated, 500GFlops, for notebooks
–Llano powered laptops later in June

Super Low Power – 28nm SLP (doesn’t use stressing), about 2.3GHz

High Performance Plus – 28nm HPP (uses stressing), about 3.1GHz

Global Solutions – Design Solutions, Technology, Design Infrastructure<

IP – in place

Fabs – New York, Germany, Singapore

MPW – 4 shuttles in 2011

20nm – working with Common Platform partners, area scaling of 50% from 28nm

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A Birds-Eye Overview of DRC+

A Birds-Eye Overview of DRC+
by Daniel Nenni on 06-13-2011 at 10:57 pm
Categories: EDA, Foundries, GlobalFoundries

The GlobalFoundries DRC+ platform is one of the most innovative DFM technologies and was well represented at #48DAC. In case you missed it, here is a reprint of a DRC+ overview from GFI just prior to #48DAC:

DRC (Design Rule Constraints) are the fundamental principles in constraining VLSI (Very Large Scale Integration) circuit designs to standardized physical and electrical manufacturability criterion.

Today’s component miniaturization and density technologies require continual reassessment of best practice applications to keep design geometries aligned with realistic manufacturing capabilities. Two-dimensional DRC layout patterns may prove to be mathematically and layout rules compliant. But, when they are applied at the extremes of the manufacturing process tolerances, lithographic printability issues still arise. DRC+ is a new methodology that can be implemented in identifying the issues around complex process methods.

DRC+ pattern based rule deck provided by GLOBALFOUNDRIES is a cutting-edge application that can not only identify the 2D pattern anomalies early on; it can efficiently identify these anomalies during the all stages of the design flow. DRC+ functions in the same fashion as traditional design constrained applications. However, it adds the function of associating a 2D pattern with each constraint which acts as a filter to localize where the constraint is applied.

The result of this functionality is that the DRC tool, running a DRC+ rule deck, will enforce tighter constraints only where the anomalies occur. For this discussion tip-to-side patterns are the subject.

An example of this implementation is shown in Figure 1, which enforces a tighter min-space +20nm line-end space constraint where the U-shaped pattern is found. DRC+ operates strictly on design geometries without any intrinsic understanding of the underlying manufacturing technology process. Therefore, the effectiveness of DRC+ depends heavily on the quality of the rule deck.

A Brief Overview
Figure 2 is an example of how DRC+ applies a “preferred” rule constraint to tip-to-side geometry. Each DRC+ rule includes a specific tip-to-side pattern, and a preferred rule, which has a more stringent constraint to be applied in that pattern situation. This example uses tip-to-side patterns that vary due to the surrounding context. In this case, the standard DRC rule specifies a constraint of ≥ 60nm, while the DRC+ rule deck adds a more stringent constraint of ≥ 80nm. A patterns that does not pass the standard DRC rule, will have the DRC+ rule applied.

One way to create DRC+ rules is to identify hotspots using printability verification simulation. Once identified, a DRC+ rule is crafted to disallow the problematic pattern in design. The DRC+ methodology employs an algorithmic approach to creating rules. Rather than using a hotspot as a starting point, it approaches the hot spot from the perspective of design, design style, and design variability to establish at the outset which patterns should be considered for DRC+ rules1. The result of DRC+ analysis is hot patterns rather than hotspots. This provides effective screening while enabling much higher efficiency and throughput than litho simulation of an entire chip.

A Bit More Detail
DRC+ uses a series of steps to identify pattern configurations. The first step is to develop situation classes. These are determined by extracting patterns from representative designs (see Figure 3) and developing a histogram of the situation classes. These classes can then be evaluated based upon permutations and occurrences.

The next step is to determine which of these situation classes have lower than average printability. These are the classes that, based upon the required constraint to ensure printability, become candidates for DRC+ rules (In the above graphic, it happens to be the tip-to-side distance). Then, a metric called Design-Induced Edge Printing Variability (DIEPV) is used to determine the printability of each class. DEIPV essentially represents printing error over the process window for a given situation—the greater the magnitude of DIEPV, the more printing error is likely.

Now, one must determine which situation classes are candidates for DRC+ rules. In the above case, a simple threshold algorithm can be implemented comparing the DIEPV statistics of each situation class to the values of the overall layout. Once the algorithm has been applied the data can be displayed graphically for analysis (see Figure 4).

Tool Implementation
DRC+ is compatible with both traditional and cutting-edge generation of EDA (Electronic Design Automation) tools. For this article, we will use Calibre® as an example. Figure 5 shows the error makers, DRC+ rule in question and its context (i.e., its situation). The equation-based DRC capability of Calibre® also provides specific hints on how to fix the violation. Where the physical verification platform is integrated into the physical design environment, most of the repairs can be done automatically by the physical design tool itself, such as the router.

Conclusion
DRC+ is a new methodology that algorithmically characterizes design variation through pattern classification. A traditional design rule is used to identify all design structures that share a common configuration. Then the 2D geometric situations (pattern variations) around the configuration are extracted and classified. Since all such classes share a common configuration, each situation class represents design variations of the basic configuration.

DRC+ uses statistics derived from measurements of the situation classes as an alternative to simple CD (critical dimension) or EPE (edge placement error) thresholds used in classic printability verification. By identifying which situation classes have bad printability statistics, we can algorithmically find DRC+ rules.

The benefits of DRC+ are gaining tremendous industry momentum as the world’s leading EDA suppliers are already releasing development tools that support GLOBALFOUNDRIES DRC+ rule sets in 28nm.

Tools that provide fast pattern matching capabilities make implementation of DRC+ straightforward. For the user it is mainly a matter of updating the standard DRC rule deck with the expanded DRC+ pattern-based rule deck provided by GLOBALFOUNDRIES. Performance is on a par with traditional DRC runs.

The GFI Concurrent Newsletter is HERE. There is a video presentation of DRC+ HERE.

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CyberEDA adds a Transistor-Level Debugger

CyberEDA adds a Transistor-Level Debugger
by Daniel Payne on 06-13-2011 at 6:34 pm
Categories: Uncategorized

Intro
I met with CK Lee, founder of Cyber EDA at his booth on Monday evening in San Diego. Last year I learned about their new SPICE circuit simulator named PCSIM, this year the new product is called ADDS-Debugger.



Notes
2010 – Announced a debugger

2011 ADDS Debugger – trace at the transistor level your design
– Signal tracing
– Post-layout debug

o Tracing – which signal triggered that net that rose or fall?
o Trace back to a Primary input
o Cross-probe between auto-generated Schematic and the waveforms
o Pricing: $50K per year
– ADDS Wave
o Pricing: $2K per year
– PCSim
o Pricing: $25K per year
o Post-layout simulation speed improved, 3X
o True SPICE simulator, flattened
o Compete with HSPICE, SPectre, ELdo

Customers – Ali (Taiwan)
– Extreme DA

Based: Santa Clara, CA

Employees: 10

Next Year: Double revenues

Sales: Direct mostly, some distributors

Summary
ADDS Debugger reminded me a lot of what Concept Engineering has been offering for several years now in a transistor-level debugger. What makes this different is that you’re inside of a circuit simulation run when you can visualize the netlist as a schematic and see the node voltages and branch currents.

The SPICE circuit simulator market is crowded with many EDA vendors (Synopsys, Mentor, Cadence, Magma, Berkeley, Tanner EDA), so Cyber EDA has to do something special in order to make PCSIM stand out from the crowd (speed, accuracy, capacity, features).

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QuickCap for IC Extraction at DAC 2011

QuickCap for IC Extraction at DAC 2011
by Daniel Payne on 06-13-2011 at 6:08 pm
Categories: Uncategorized

Intro
John and Ralph from Magma gave me an update on QuickCap at DAC on Monday afternoon in their demo suite.

Notes
John Schritz – Sr AE
Ralph Iverson, Ph. D. (wrote QuickCap)

John Schritz
– Digital Signoff, extraction
– QCP: 2.5D RC for full ASIC designs
– QuickCAP NX: 3D field solver
– QCP:

Demo – 1.5 million instance design, 1.59 million nets, fully P&R, three libraries
– QCP: Gate Level (Star RC competitor)
– QuickCapNX: 3D field solver (Raphael competitor)
– QCP TX: Transistor Level (RC XT competitor)
– QCP
o 10X faster than Star RC
o 20X faster with multi-corner extraction
o Accuracy: +-2% of QuickCap NX
o TSMC qualified at 28nm
o Inputs: LEF, DEF, GDS II
o Scaling: can add multiple corners using only 20% run time, can be distributed across more boxes
o Capacity: 50M instance designs, memory efficiency
o Accuracy (vs Star RC)
o Example: TSMC 40nm, 38K nets
o 1 corner at 5 hrs, 12 corners at 8.4 hours (27X faster than Star RC), using 3.3GHZ CPU, 148GB and 12 CPUs
o One license per four cores (after that add a multi-core to add up to 32 cores)
o 16 Synopsys licenses for a runtime of 60 minutes, vs 2 licenses in 34 minutes
o ½ the run time, ¾ the HW, 1/8 the licenses (compared to Synopsys with 80% market share)
o 3D on demand (add QuickCap NX), name the nets you want best accuracy on
– Tekton – a STA tool
o Reads SPEFS
o Fast STA in minutes
o Concurrent MM/MC
o Accurate with SPICE integration
– Old flow
o Implement, output a GDS II
o Extract, output SPEF
o STA
– New Flow
o Implement
o QCP and Tekton
– QuickCap NX: Industry Golden 3D Field Solver
o Same run time independent on
o Three methods:
 Finite Element (Slowest)
 Boundary Integral (Slow, what Mentor 3D XACT uses)
 QuickCap (Fastest)
o Field-solver accuracy (within 1% of Silicon)
o Good for library characterization, custom, analog
o Flow Inputs: ITF or iRCS from foundary, GDS II layout
o Industry standard solver at IDMs, Foundries
o Edge effects
o Qualified by TSMC
– QCP TX – transistor level extraction
o Millions of transistor capacity
o To be released in 6 months
o For: Custom design, memory, AMS
o CCI – Calibre Connectivity Interface, stress parameters, well proximity
– QCP Demo
o 18 million nets extracted per hour on 8 threads

Summary
Star RC (Synopsys) has plenty of competition from Magma, Mentor and Cadence for IC extraction. I also learned more about 3D Field Solvers on Tuesday at the Pavilion Panel session.

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HSPICE gets Faster, better Convergence

HSPICE gets Faster, better Convergence
by Daniel Payne on 06-13-2011 at 5:53 pm
Categories: EDA, Synopsys

Hany El Hak – Product Marketing Manager

Frederik Iverson – AE

Scott Wetch – HSPICE Architect

HSPICE – 5 years ago convergence was not so good, while 95% of analog circuits today converge out of the box, no options are required.

Synopsys AMS Portfolio – wide range of tools
– Custom Designer: IC schematic and layout tools
– HSPICE – circuit simulation
– CustomSim – full chip circuit simulation
– IC Validator/Star RC – extraction, DRC, LVS

HSPICE – Golden SPICE standard for about 30 years now, the same tool the foundry used to create their cells
– Used in IC, AMS, PCB for SI

Issues – Long run times, could be days to cover all of the corners required, more runs

Improvements in HSPICE – 5X faster than 2007 on a single core, averaged over 100’s of circuits
– Precision Parallel, 7X faster when using 8 cores compared to a single core
– 10X more capacity, about 10 million elements
– New Analysis added: High Frequency, Statistical Eye Diagrams, Transient Noise, Loop Stability
– Convergence, 95% out of the box, no settings required
– Distributed Processing (MC, Corners, Sweeps) – distribute over the network (17X on 20 CPUs)

HSPICE Precision Parallel – run times reduced from days to hours
– Up to 7X faster on 8 cores (use –hpp option)
– PLL runs now reduced to 4 hours instead of days
– PLL example with 7K MOS and RC, 12.5 hours (148 hours, competitor)
– Clock Tree with 10M elements, 7 hours (108 hours, competitor)
– Sigma Delta Converter, 7.7 hours (16 hours, competitor)

HSPICE Distributed Processing – divide and conquer (MC, corners with .ALTER, sweeps)
– 10 CPUs at 8.7X faster
– 20 CPUs at 17.3X faster (some overhead to collect all that data)

Post-layout – selective net back-annotation (use parasitic only where needed)
– Check and find only the active nets for extraction (automatic or manually identified)
– Apply parasitics only to critical nets that are identified

Transient Noise Analysis – Include noise in time domain simulations (about 2X to 3X slower than transient)
– Full nonlinear analysis of noise effects in the time domain
– All devices are taken into account (thermal noise, channel noise, flicker noise)
– Today a single CPU, in September see the parallel version

Custom Designer (Schematics and Layout)
– HSPICE integrated within

Frederick Iverson, demo of Duty Cycle Corrector (40nm node, Used in IP group for USB 3.0, 450 analog designers at SNPS)
– Custom Designer uses OA for a db. Any circuit simulator can be added to Custom Designer.
– Normal simulation is 5 minutes to complete, Precision Parallel completes in about 1 minute
– Command line has Tcl, so it’s easy to save and re-run commands.
– Si2 is showing how to run tools with many languages: Tcl, Perl, Ruby, etc.
– Plot of simulation results shown in WaveView tool, measurement tool to show % duty cycle.
– HSPICE uses one license for two threads, so use it at no extra cost
– Back annotate a full netlist or a partial netlist (used a DSPF file from Star RC)
– Names in HSPICE are the pre-layout names even with back-annotated values
– Transient noise demonstrated, the output does show jitter, wave view shows jitter versus time, histogram shows standard deviation on jitter values

Summary
HSPICE has to continually improve in order to stay current with Berkeley DA, Eldo, Spectre and FineSIM circuit simulators.

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Physical IP Group at ARM

Physical IP Group at ARM
by Daniel Payne on 06-13-2011 at 5:45 pm
Categories: Arm, IP

After lunch on Monday I met with John Heinlin, Ph.D. – VP Marketing of Physical IP Division

Back in the day I knew the founders of Artisan (VLSI Libraries) when we worked together at Silicon Compilers (Mark Templeton, John Malecki, Scott Becker).

Q: Do you favor any EDA tools for creating your IP?
A: No, we don’t really endorse a specific EDA vendor tool or flow.

Q: What’s new at ARM for 2011?
A: Just started Process Optimization Packs. Linking IP that is tuned for ARM cores.

Artisan – Generic cells. Used to wait for a node to become stable.

ARM – Focused on leading edge cells, now at 28nm nodes. Now doing test chips quite early to tweek and optimize cells, as requirements into the process.

2010 – 32nm last year announced.

2011 – 28nm IP is now ready as soon as announced. TSMC, SMIC, Samsung, IBM, GlobalFoundries (CP), TSMC.

Q: How to reach Power Performance and Area for your design?
A: We have a User Guide on how to get best results.

Q: Any preference for PDKs?
A: Support whatever PDK is available, no preference.

Synopsys – renewed tools agreement for a period of time.

Cell Library – about 1,000 cells to choose from, with about 100 different functions. Simple gates, flip-flops (power saving modes)

Q: What is your royalty model?
A: Royalty Model – same as always, no upfront costs. Foundries pay for library development.

Memory compilers cells – Standard RAMS, then lower VDD RAMs for an extra price. Typically 5 to 7 compilers per node.

Foundries – Some are offering their own libraries.

ARM Artisan IP (re-using)

Memory Compilers – Virage (Synopsys) has a piece of it. ARM invests heavily in these at leading edge nodes. Area efficient nodes too.

SOI – French based (SOISIC), acquired about 5 years ago, used at IBM.

Physical – GP IOs, 40nm Low Power. Will add DDR libraries soon. Have controller, PHy and IO in one piece.

Q: What do you think of Intel’s TriGate?
A: FinFET – At 20nm planar CMOS still works, 14nm then FinFET looks viable.

Q: What is success for ARM?
A: Success – We think rich solutions across a wide range of foundries at 28nm now, 20nm soon (test chips with Samsung).

Q: How do you use RDR?
A: RDR – We’ve been dealing that for a few nodes now (20nm needs double patterning). We work closely with foundries for all nodes.

Common Platform – ARM is the IP you get.

Q: Where do I find out more?
A: Visit our SOC Design Community