Ciranova Update at DAC

Intro
Ciranova offers you an alternative for analog layout automation besides Cadence Virtuoso. Mark Nadim provided me an update at DAC last Wednesday.

Notes
New in 2011
– New GUI with schematic, layout and constraints
o Cross probing between all three windows
– Schematic for constraint entry
o Can start with a blank schematic, enter new design
o Read any native OA schematic
o See all the MOS instances in a tree, define layout constraints very quickly
o Drag and drop constraints
o Cross probe between MOS list and Schematic view
o Hierarchy supported
– Helix First Look
o Schematic and Analog constraints in, layout out
o Find in netlist common bulks, get placed together
o Easy way to create initial layout constraints, does auto grouping of layout
– New customers: Marvel
– 28nm migration is important, Helix is an easier way to conform to new design rules
o Auto placement helps on minimum rules
o Read design rules for density and Helix can push transistors apart to reach the rules
– Create many alternative layouts, Extract a netlist, use Calibre parasitics, create fully extracted netlist ready for Berkeley AFS
– Users: Initially the Circuit Designer starts, then handed off to the Layout Designer for completion
– Routing Example: pattern based constraints used, then autoroute between all the rows and columns of placed Devices
– New way to create layout constraints, based on patterns or Python scripts (mostly CAD or Circuit Designers create scripts)

Summary
Ciranova Helix is a tool that can create analog layout using PyCells very rapidly by a Circuit Designer. Demanding IC designers from the largest semiconductor companies in the world use these tools.