*Work Email Required for Registration*
For packaging, thermal, and mechanical engineers who need trusted warpage insight before stackup, material, and package architecture decisions are locked — and want to see what becomes possible when a full design study fits in an afternoon.
In advanced packaging, warpage is rarely a modeling… Read More
COMPANY EMAIL REQUIRED FOR REGISTRATION.
Studies show that nearly 20% of the verification cycle is spent on assertion generation, debugging, and methodology integration — work that remains largely manual today or is delegated to general-purpose LLMs that hallucinate more than 30% of the time and produce incorrect assertions.… Read More
Agentrys recently launched a new category of design technology, Agentic Design Automation (ADA). The approach promises to revolutionize AI deployment for chip design with technology that facilitates the building of targeted agentic design flows that get better with every run. There is a lot of information available on the … Read More
Featured Speakers:
- Madhumita Sanyal, Sr. Director of Technical Product Management, Synopsys
- Varun Agrawal, Director of Product Management, Synopsys
As SoC complexity climbs, traditional verification can’t keep pace — and system-level bugs surface late, when they’re hardest to fix. By pairing Hardware-Assisted… Read More
Designing AI inference hardware for edge applications often requires building custom hardware accelerated solutions to meet the demands for ultra-low power consumption and strict real-time response requirements. This webinar introduces Catapult™ AI NN, which provides an automated flow that starts with a Python neural… Read More
MUST USE COMPANY EMAIL TO REGISTER
A purpose-built multi-agent system for chip design shouldn’t be a quarter-long project. On the Agentrys Studio Platform, the initial build takes about 30 minutes—plus however much customization your flow and data require.
In this hands-on session, we’ll build a working end-to-end… Read More
How Will You Manage Power, Performance, and Reliability in the Chiplet Era?
Chiplet-based architectures, 2.5D integration, and system-in-package (SiP) designs are unlocking new levels of performance, scalability, and design flexibility. But moving beyond the monolithic SoC also introduces complex interactions among… Read More
COMPANY EMAIL REQUIRED FOR REGISTRATION
Full-chip SoC debug has become one of the most expensive bottlenecks in modern verification. A single production issue can pull multiple engineers away days as they chase a failure through waveforms, logs, and across hundreds of thousands of lines of code.
In this webinar, we will demonstrate… Read More
Discover Synopsys ParagonX, a powerful tool for intelligent analysis, debugging, simulation and visualization of IC layout parasitics. This webinar demonstrates how ParagonX accelerates root-cause analysis for top-level analog, custom digital and mixed-signal designs.
What You Will Learn:
- Assess and quantify the effects
…
Read More
