VirtuaLAB protocol solutions offer a full-stack testing environment with seamless connectivity and stimulus traffic generation for designs under test. It operates autonomously, adapting to scenarios without requiring protocol knowledge from the user. VirtuaLAB significantly reduces test and compliance suite regression… Read More
As the Semiconductor industry continues to change and evolve, requirements for test continue to extend from manufacturing into in-system as part of a growing SLM strategy. The growing need to increase the quality of in-system testing capabilities is driving a shift in technology.
Thanks to new innovation, it is now possible … Read More
Processor trace gives software developers access to critical insights and forensic capabilities to manage the risk of building embedded systems. In this presentation, Siemens and Lauterbach will give an overview of how processor trace can be used to improve embedded software and applications. We will explain the RISC-V Efficient
Join Keysight for a comprehensive session focused on enhancing device reliability and preventing costly silicon respins through innovative noise and binning modeling technologies.
Enhancing Reliability with Accurate Noise Measurement and Modeling
Accurately accounting for noise is essential for ensuring reliability… Read More
SDEP™ provides robust APIs for creating automated reusable modeling flows significantly reducing turnaround time while preserving essential device modeling knowledge.
The platform integrates Primarius‘ latest technologies for data analysis, parameter extraction, and model quality checking. With its flexible GUI and… Read More
ME-Pro™ is a unified tool for designers, process developers, modeling engineers, and PDK engineer providing robust simulation and analysis capabilities for semiconductor device model verification and evaluation.
This comprehensive platform supports evaluation across device, circuit, and process domains enabling interactive… Read More
Primarius NanoSpice™ Series boosts SRAM design accuracy and performance with its powerful suite of tools. Featuring competitive performance, a circuit-type-driven intuitive usage model, and comprehensive capabilities. These solutions deliver high-precision simulations for SRAM blocks, critical paths, and full macro… Read More
A successful multi-die design begins at the architecture exploration level. However, the architecture challenges are exacerbated for multi-die designs as performance and power need to be optimized across multiple heterogeneous and homogeneous dies. Disaggregating IPs based on workload demands, selecting the… Read More
Wednesday, September 18, 2024 | 10 a.m. PDT
Migrating analog designs across process nodes can be a complex and time-consuming challenge. In this webinar, Credo will share its experience using Synopsys ASO.ai, part of the Synopsys.ai™ EDA suite, to streamline and accelerate the design migration of analog circuits. With its automated
Join us for an exclusive 1-hour webinar designed for HR and Learning & Development professionals in the US semiconductor industry. This event will delve into the pressing workforce challenges faced by the semiconductor industry and explore innovative solutions for training and development.
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