Data rates have doubled, but validation methods have not kept pace. As PCIe, DDR, and multi-terabit optical interconnects evolve, engineers are encountering signal integrity challenges much earlier in the design process.
Join Niels Fache, Senior Vice President and General Manager of Design Engineering Software at Keysight,… Read More
In this webinar, Marvell will present how its team accelerates passive interposer routing for advanced 2.5D/3.5D multi die designs by bringing early, physics based signal integrity feedback into each routing iteration. Rather than relying on repeated, compute intensive 3D FEM cycles during development, Marvell uses a Method… Read More
As semiconductors continue to scale, designers are turning to 3DIC architectures to meet increasing demands for performance, energy efficiency, and functional density in data centers and edge AI applications. However, stacking multiple dies introduces new multiphysics challenges including electrical, structural, and… Read More
Wednesday, March 11 – 8:00 AM Pacific
Design and verification teams consistently tell us that compute subsystems require software bring up much earlier than ever before. They need UEFI and Linux to run in simulation, they need protocol accuracy from day one, and they need a predictable path to signoff while integration … Read More
The upcoming webinar “Intelligent Networks: Power, Reliability, and Maintenance in Telecom” will focus on how telecommunications networks are adapting to growing demands for efficiency, resilience, and scalability. As telecom operators expand 5G deployments, integrate cloud-native architectures, and prepare for AI-driven… Read More
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As global connectivity demands surge, network infrastructure hardware is under unprecedented pressure to deliver higher performance, lower latency, and greater energy efficiency, while remaining cost-effective and reliable. This challenge is compounded with the explosive growth of AI applications, emerging 5G… Read More
The explosive growth of AI and accelerated computing is placing unprecedented demands on system-on-chip (SoC) design. Modern AI workloads require extremely high bandwidth, ultra-low latency, and energy-efficient data movement across increasingly heterogeneous architectures. As SoCs scale to incorporate clusters of… Read More
