Webinar: Trained Eyes on 64G UCIe: Scale Chiplet Integration for AI

Webinar: Trained Eyes on 64G UCIe: Scale Chiplet Integration for AI
by Admin on 11-20-2025 at 3:10 am

Join us to hear firsthand from the innovators at Siemens and Alphawave Semi and learn proven practices to enhance your UCIe-enabled AI system performance!

The semiconductor industry is shifting rapidly from monolithic SoC design to chiplet-based systems. At the same time, AI compute workloads have pushed into petaflop-class

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Webinar: 5 Expectations for the Manufacturing Market in 2026

Webinar: 5 Expectations for the Manufacturing Market in 2026
by Admin on 09-30-2025 at 12:02 am

Discover the 5 Critical Manufacturing Market Trends Reshaping Semiconductors in 2026

AI-driven investments, sustainability, and advanced materials—what’s next for semiconductor manufacturing.

The semiconductor manufacturing industry is undergoing a transformative period as AI-driven investments accelerate, sustainability… Read More


Webinar: 5 Expectations for the Mobile Market in 2026

Webinar: 5 Expectations for the Mobile Market in 2026
by Admin on 09-30-2025 at 12:00 am

January 5, 2026 – 11:00 AM EST   

January 6, 2026 – 10:00 AM JST/KST

Discover the 5 Critical Mobile Market Trends Reshaping Semiconductors in 2026

Mobile AI, shifting supply chains, and new form factors—what’s next for the mobile semiconductor industry.

The mobile semiconductor market faces an inflection point in 2026. While… Read More


Webinar: 5 Expectations for the Consumer Electronics Market in 2026

Webinar: 5 Expectations for the Consumer Electronics Market in 2026
by Admin on 09-29-2025 at 11:58 pm

December 16, 2025 – 11:00 AM EST   

December 17, 2025 – 10:00 AM JST/KST

Discover the 5 Critical Consumer Electronics Market Trends Reshaping Semiconductors in 2026

AI, tariffs, smart home, and display innovations—what’s next for consumer electronics.

The consumer electronics market is poised for transformation in 2026,… Read More


Webinar Preview – Addressing Functional ECOs for Mixed-Signal ASICs

Webinar Preview – Addressing Functional ECOs for Mixed-Signal ASICs
by Mike Gianfagna on 09-11-2025 at 10:00 am

Webinar Preview – Addressing Functional ECOs for Mixed Signal ASICs

An engineering change order, or ECO in the context of ASIC design is a way to modify or patch a design after layout without needing to re-implement the design from its starting point. There are many reasons to use an ECO strategy. Some examples include correcting errors that are found in post-synthesis verification, optimizing … Read More


WEBINAR: Functional ECO Solution for Mixed-Signal ASIC Design

WEBINAR: Functional ECO Solution for Mixed-Signal ASIC Design
by Daniel Nenni on 09-04-2025 at 8:00 am

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This webinar, in partnership with Easy-Logic Technology, is to address the complexities and challenges associated with functional ECO (Engineering Change Order) in ASIC design, with a particular focus on mixed-signal designs.

The webinar begins by highlighting the critical role of mixed-signal chips in modern applications,… Read More


WEBINAR: Edge AI Optimization: How to Design Future-Proof Architectures for Next-Gen Intelligent Devices

WEBINAR: Edge AI Optimization: How to Design Future-Proof Architectures for Next-Gen Intelligent Devices
by Daniel Nenni on 07-03-2025 at 10:00 am

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Edge AI is rapidly transforming how intelligent solutions are designed, from smart home devices to autonomous vehicles, healthcare gadgets, and industrial IoT. Yet, architects, chip designers, and product managers frequently grapple with a common and daunting challenge: creating efficient, high-performance AI solutions… Read More


WEBINAR Unpacking System Performance: Supercharge Your Systems with Lossless Compression IPs

WEBINAR Unpacking System Performance: Supercharge Your Systems with Lossless Compression IPs
by Daniel Nenni on 07-03-2025 at 6:00 am

CAST Compression IP Webinar 400x400

In today’s data-driven systems—from cloud storage and AI accelerators to automotive logging and edge computing—every byte counts. The exponential growth in data volumes, real-time processing demands, and constrained bandwidth has made efficient, lossless data compression a mission-critical requirement. Software-based… Read More


Essential Debugging Techniques Workshop

Essential Debugging Techniques Workshop
by Admin on 06-12-2025 at 1:48 pm

Essential Debugging Techniques Workshop

This workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the Vivado Design Suite. The features and capabilities of the Vivado

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Upcoming Webinar: Accelerating Semiconductor Design with Generative AI and High-Level Abstraction

Upcoming Webinar: Accelerating Semiconductor Design with Generative AI and High-Level Abstraction
by Daniel Nenni on 03-27-2025 at 10:00 am

RDA SemiWikiblog graphic

We have been hearing so much lately about the power of AI and the potential of technologies like agentic AI to address the productivity gap and complexities of semiconductor designs of today and tomorrow.  Currently, however, the semiconductor industry has been slow to adopt generative and agentic AI for RTL design code.   There… Read More