Tag: verification

Webinar: Verifying Chiplet-based Systems

Webinar: Verifying Chiplet-based Systems
by Admin on 05-27-2025 at 11:15 am

Verifying Chiplet-based Systems (online)

As the semiconductor industry increasingly embraces chiplet-based architectures, the complexity of system integration and verification has grown exponentially. Verifying these modular systems demands new approaches, tools, and collaboration across design and verification… Read More

Accellera at the 62nd Design Automation Conference – Luncheon Panel

Accellera at the 62nd Design Automation Conference – Luncheon Panel
by Admin on 05-12-2025 at 5:47 pm

“Can AI Cut Costs in Electronic Design & Verification While Accelerating Time-To-Market?”

Industry leaders will discuss the transformative role of AI in semiconductor design and verification. As AI rapidly evolves, its potential to reduce costs, shorten time-to-market and address impending talent shortages is becoming… Read More

Webinar: Streamlining Requirements Traceability Using Questa Verification IQ Testplan Author

Webinar: Streamlining Requirements Traceability Using Questa Verification IQ Testplan Author
by Admin on 05-08-2025 at 12:23 am

Wednesday, May 28 – 8:00 AM Pacific

Managing traceability across multiple disconnected tools and data is a challenge that often leads to inefficiencies, missed coverage, and increased risk in safety-critical designs.

In this webinar, discover how Questa Verification IQ Testplan Author seamlessly integrates with

… Read More

Webinar: Solving the Semiconductor Verification Crisis: From Problem to Productivity

Webinar: Solving the Semiconductor Verification Crisis: From Problem to Productivity
by Admin on 05-08-2025 at 12:21 am

Wednesday, May 21 – 8:00 AM Pacific

The semiconductor industry faces a critical Verification Productivity Gap 2.0, driven by increasingly complex technologies including 3DICs, chiplet-based designs, and software-defined architectures.

This challenge is compounded by demands for Enhanced security, Reduced power

… Read More

Webinar: Boost Verification Efficiency with VC Execution Manager: Harnessing AI/ML for Superior Regression Management

Webinar: Boost Verification Efficiency with VC Execution Manager: Harnessing AI/ML for Superior Regression Management
by Admin on 04-18-2025 at 9:48 am

Featured Speakers:

  • Gopinath Lakshmi Narasimhan, Sr. Architect Applications Engineer
  • Robert Ruiz, Sr. Director, Product Management

Why You Should Attend:

  • Discover the innovative capabilities of Synopsys VC Execution Manager for streamlined verification processes.
  • Learn about the seamless integration of advanced AI/ML
… Read More

Webinar: Verifying AI Designs – Solving the Challenge of Quadrillions of Verification Cycles

Webinar: Verifying AI Designs – Solving the Challenge of Quadrillions of Verification Cycles
by Admin on 03-28-2025 at 12:31 pm

Today’s AI designs stress verification teams to an unprecedented extent. The compound complexity from software, hardware, interfaces, and architecture options leads to the challenge of running quadrillions of verification cycles across IP, sub-systems, SoCs, and Multi-die designs. Learn how leaders from AMD, Arm, Nvidia,

… Read More

Webinar: Simplifying Interface Protocol Verification with Veloce Transactor Library

Webinar: Simplifying Interface Protocol Verification with Veloce Transactor Library
by Admin on 03-27-2025 at 1:04 pm

As hyperscaler chiplet and SoCs grow in complexity, integrating and validating multiple high-speed and low-speed interface protocols—such as PCIe, CXL, UCIe, AMBA, AXI, AHB, CHI, CSI2, and DSI2, can be a significant challenge. Design Verification Engineers and Technical Managers must ensure seamless protocol compliance

… Read More
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AlphaDesign AI Experts Wade into Design and Verification

AlphaDesign AI Experts Wade into Design and Verification
by Bernard Murphy on 03-06-2025 at 6:00 am
Categories: AI, ChipAgents AI, EDA

DVCon 2025 talk min

I mentioned in an earlier blog that multiple presentations at DVCon 2025 went all-in on AI-assisted design and verification. The presentation was one such example, looking very much at top-down AI-expert application of agentic flows to design and verification. AlphaDesign is a new startup out of UC Santa Barbara headed by William… Read More

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Automating Reset Domain Crossing (RDC) Verification with Advanced Data Analytics

Automating Reset Domain Crossing (RDC) Verification with Advanced Data Analytics
by Kalar Rajendiran on 09-26-2024 at 10:00 am
Categories: Analytics, EDA, Siemens EDA

RDC Verification using Data Analysis Techniques

The complexity of System-on-Chip (SoC) designs continues to rise at an accelerated rate, with design complexity doubling approximately every two years. This increasing complexity makes verification a more difficult and time-consuming task for design engineers. Among the key verification challenges is managing reset domain… Read More