Tag: verification

Webinar: Efficient and Robust Memory Verification in Modern SoCs Using Formal Equivalence Checker

Webinar: Efficient and Robust Memory Verification in Modern SoCs Using Formal Equivalence Checker
by Admin on 11-05-2024 at 5:51 pm

With the increasing complexity and importance of memories in modern ICs, there is a clear need for specialized tools and techniques for the design and verification of embedded memory blocks. Traditional methods like SPICE simulation and cell-based formal verification have limitations; SPICE offers circuit-level accuracy

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Webinar: Efficient and Robust Memory Verification in Modern SoCs Using Formal Equivalence Checker

Webinar: Efficient and Robust Memory Verification in Modern SoCs Using Formal Equivalence Checker
by Admin on 10-20-2024 at 6:05 pm

With the increasing complexity and importance of memories in modern ICs, there is a clear need for specialized tools and techniques for the design and verification of embedded memory blocks. Traditional methods like SPICE simulation and cell-based formal verification have limitations; SPICE offers circuit-level accuracy

… Read More

Webinar: Hardware Verification using VirtuaLAB

Webinar: Hardware Verification using VirtuaLAB
by Admin on 10-09-2024 at 10:19 am

VirtuaLAB protocol solutions offer a full-stack testing environment with seamless connectivity and stimulus traffic generation for designs under test. It operates autonomously, adapting to scenarios without requiring protocol knowledge from the user. VirtuaLAB significantly reduces test and compliance suite regression… Read More

Discover the Future of HyperLynx Technology: Lunch and Learn

Discover the Future of HyperLynx Technology: Lunch and Learn
by Admin on 10-07-2024 at 8:37 am

Discover the Future of HyperLynx Technology: Lunch and Learn

Join us to be among the first to explore HyperLynx breakthrough technologies designed to redefine user experience and boost design productivity. Released in September 2024, these innovations are tailored to address the most pressing challenges faced by design engineers,… Read More

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Automating Reset Domain Crossing (RDC) Verification with Advanced Data Analytics

Automating Reset Domain Crossing (RDC) Verification with Advanced Data Analytics
by Kalar Rajendiran on 09-26-2024 at 10:00 am
Categories: Analytics, EDA, Siemens EDA

RDC Verification using Data Analysis Techniques

The complexity of System-on-Chip (SoC) designs continues to rise at an accelerated rate, with design complexity doubling approximately every two years. This increasing complexity makes verification a more difficult and time-consuming task for design engineers. Among the key verification challenges is managing reset domain… Read More

Webinar: Interactive SPICE Model Verification Platform ME-Pro

Webinar: Interactive SPICE Model Verification Platform ME-Pro
by Admin on 09-20-2024 at 1:28 pm

ME-Pro™ is a unified tool for designers, process developers, modeling engineers, and PDK engineer providing robust simulation and analysis capabilities for semiconductor device model verification and evaluation.

This comprehensive platform supports evaluation across device, circuit, and process domains enabling interactive… Read More

Webinar: Simplify Design Verification and Compliance with Standards-Driven EDA Workflows

Webinar: Simplify Design Verification and Compliance with Standards-Driven EDA Workflows
by Admin on 06-25-2024 at 2:16 pm

About this event

As electronics grow denser and interconnects more intricate, the design process becomes increasingly challenging. Designers need increased automation and cross-functional collaboration to adhere to stringent industry standards. This webinar introduces the 2024 additions to Keysight EDA: Chiplet PHY

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