DVCON U.S. 2026by Admin on 08-27-2025 at 10:06 pm
DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is the usage of specialized design and verification languages such as SystemVerilog, Verilog, VHDL, PSS, SystemC and e, as well… Read More
Speaker: Hong-Cheang Quek, AE Director
10:00am~11:00am iPegasus Verification System for Virtuoso Studio
11:00am~11:15am Q&A
Description: Today’s complex SoC designs significantly increase layout creation and verification time, especially at advanced nodes. To meet overall demand for faster design cycle… Read More
DVCon Taiwan 2025by Admin on 07-18-2025 at 10:22 am
About DVCON
DVCon Taiwan is the premier conference for design and verification engineers, researchers, and managers in Taiwan’s semiconductor and EDA industries. Now in its third year, DVCon Taiwan 2025 continues its mission to bring together the local and international community to exchange ideas, explore the latest… Read More
In the race to deliver ever-larger SoCs under shrinking schedules, simulation is becoming a bottleneck. With debug cycles constrained by long iteration times—even for minor code changes—teams are finding traditional flows too rigid and slow. The problem is further magnified in continuous integration and continuous deployment… Read More
Verifying Chiplet-based Systems (online)
As the semiconductor industry increasingly embraces chiplet-based architectures, the complexity of system integration and verification has grown exponentially. Verifying these modular systems demands new approaches, tools, and collaboration across design and verification… Read More
“Can AI Cut Costs in Electronic Design & Verification While Accelerating Time-To-Market?”
Industry leaders will discuss the transformative role of AI in semiconductor design and verification. As AI rapidly evolves, its potential to reduce costs, shorten time-to-market and address impending talent shortages is becoming… Read More
I mentioned in an earlier blog that multiple presentations at DVCon 2025 went all-in on AI-assisted design and verification. The presentation was one such example, looking very much at top-down AI-expert application of agentic flows to design and verification. AlphaDesign is a new startup out of UC Santa Barbara headed by William… Read More
The complexity of System-on-Chip (SoC) designs continues to rise at an accelerated rate, with design complexity doubling approximately every two years. This increasing complexity makes verification a more difficult and time-consuming task for design engineers. Among the key verification challenges is managing reset domain… Read More
