Attendees will gain access to cutting-edge technical content and expert presentations in:
Rising semiconductor complexity—driven by multi-die architectures, the move towards more advanced technology nodes, and more stringent reliability targets, is dramatically increasing the volume of verification required to achieve DFT verification sign-off.
Come learn how the Questa One DFT Verification solution, combined
Wednesday, June 4 – 8:00 AM Pacific
In today’s automotive electronics, ensuring functional safety is paramount for meeting stringent industry standards. This webinar introduces Questa One Sim FX, a cutting-edge fault simulation platform designed specifically for complex automotive designs. We’ll
As the semiconductor industry increasingly embraces chiplet-based architectures, the complexity of system integration and verification has grown exponentially. Verifying these modular systems demands new approaches, tools, and collaboration across design and verification… Read More
Industry leaders will discuss the transformative role of AI in semiconductor design and verification. As AI rapidly evolves, its potential to reduce costs, shorten time-to-market and address impending talent shortages is becoming… Read More
Wednesday, May 28 – 8:00 AM Pacific
Managing traceability across multiple disconnected tools and data is a challenge that often leads to inefficiencies, missed coverage, and increased risk in safety-critical designs.
In this webinar, discover how Questa Verification IQ Testplan Author seamlessly integrates with
Wednesday, May 21 – 8:00 AM Pacific
The semiconductor industry faces a critical Verification Productivity Gap 2.0, driven by increasingly complex technologies including 3DICs, chiplet-based designs, and software-defined architectures.
This challenge is compounded by demands for Enhanced security, Reduced power
Featured Speakers:
Why You Should Attend:
Today’s AI designs stress verification teams to an unprecedented extent. The compound complexity from software, hardware, interfaces, and architecture options leads to the challenge of running quadrillions of verification cycles across IP, sub-systems, SoCs, and Multi-die designs. Learn how leaders from AMD, Arm, Nvidia,
As hyperscaler chiplet and SoCs grow in complexity, integrating and validating multiple high-speed and low-speed interface protocols—such as PCIe, CXL, UCIe, AMBA, AXI, AHB, CHI, CSI2, and DSI2, can be a significant challenge. Design Verification Engineers and Technical Managers must ensure seamless protocol compliance
