DVCON U.S. 2026by Admin on 08-27-2025 at 10:06 pm
DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is the usage of specialized design and verification languages such as SystemVerilog, Verilog, VHDL, PSS, SystemC and e, as well… Read More
Hardware designers have been using RTL and hardware description languages since the 1980s, yet many attempts at moving beyond RTL have tried to gain a foothold. At the #62DAC event I spent some time with Mike Fingeroff, the Chief High-Level Synthesis Technologist to understand what his company Rise Design Automation is up to. … Read More
On July 9, 2025, a DACtv session illuminated the transformative role of artificial intelligence (AI) in chip design, as presented by Ankur Gupta of Siemens EDA in the YouTube video. The speaker explored how AI is revolutionizing electronic design automation (EDA), addressing the semiconductor industry’s challenges in managing… Read More
In a DACtv session on July 9, 2025, Abhi Kolpekwar, Vice-President & General Manager at Siemens EDA, illuminated the transformative role of artificial intelligence (AI) in addressing the escalating challenges of semiconductor design verification. The presentation underscored the limitations of traditional methods… Read More
LLMs are already simplifying assertion generation but still depend on human-generated natural language prompts. Can LLMs go further, drawing semantic guidance from the RTL and domain-specific training? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO… Read More
We have been hearing so much lately about the power of AI and the potential of technologies like agentic AI to address the productivity gap and complexities of semiconductor designs of today and tomorrow. Currently, however, the semiconductor industry has been slow to adopt generative and agentic AI for RTL design code. There… Read More
Badru Agarwala is the CEO and Co-Founder of Rise Design Automation (RDA), an EDA startup with a mission to drive a fundamental shift-left in semiconductor design, verification, and implementation by raising abstraction beyond RTL With over 40 years of experience in EDA, Badru served as General Manager of the CSD division at… Read More
Tell us a little bit about yourself and your company, AMIQ EDA.
We are an EDA company providing software tools targeting both chip design and chip verification. Our tools enable engineers to increase the speed and quality of new code development, simplify debugging and legacy code maintenance, accelerate language and methodology… Read More
You begin writing some UVM code and there are parts of the code that aren’t done yet, so you begin to use uvm_objection, guarding that code. Rich Edelman, a product engineer at Siemens doing verification debug and analysis, wrote a paper on this topic, which I just read. This blog covers the topic of objections and provides some different… Read More
