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With the increasing complexity and importance of memories in modern ICs, there is a clear need for specialized tools and techniques for the design and verification of embedded memory blocks. Traditional methods like SPICE simulation and cell-based formal verification have limitations; SPICE offers circuit-level accuracy
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Synopsys made significant announcements during the recent TSMC OIP Ecosystem Forum, showcasing a range of cutting-edge solutions designed to address the growing complexities in semiconductor design. With a strong emphasis on enabling next-generation chip architectures, Synopsys introduced both new technologies and … Read More
Part 2 of this 4-part series reviews the role of virtual prototypes as stand-alone tools and their use in hybrid emulation for early software validation, a practice known as the “shift-left” methodology. It assesses the differences among these approaches, focusing on their pros and cons.
The Immensity of Software Development… Read More
As the demand for higher performance computing solutions grows, so does the need for faster, more efficient data communication between components in complex multi-die system-on-chip (SoC) designs. In response to these needs, Synopsys has introduced the world’s fastest UCIe-based IP solution, capable of operating at a groundbreaking… Read More
Accellera invited me to attend their #61DAC panel discussion about the new Portable Stimulus Standard (PSS) v3.0, and the formal press release was also just announced. The big idea with PSS is to enable seamless reuse of stimulus across simulation, emulation and post-silicon debug and prototyping.
Tom Fitzpatrick from Siemens… Read More
Now that live events are filling up there are even more live events especially here in Silicon Valley. Synopsys, the #1 full IP provider, will host a processor summit here in Santa Clara next month. Given the popularity of anything RISC-V, I would expect this event to be very well attended so be sure and register in advance.
The networking… Read More
Dan is joined by Dr. Mark Han, Vice President of R&D Engineering for Circuit Simulation at Synopsys. Mark leads a team of over 300 engineers in developing cutting-edge advanced circuit simulation and transistor-level sign-off products, including characterization and static timing analysis. With 27 years of industry … Read More
During a recent LinkedIn webcast, Dr. Ian Cutress, Chief Analyst at More than Moore and Host at TechTechPotato, and Priyank Shukla, Principal Product Manager at Synopsys, shared their thoughts regarding the industry drivers, design considerations, and critical advancements in compute interconnects enabling data center… Read More
Dan is joined by Robert Ruiz, a product management director responsible for strategy and business growth of several verification products at Synopsys. Robert has held various marketing and technical positions for leading functional verification and test automation products at various companies including Synopsys, Novas… Read More
Part 1 of this 4-part series introduces the complexities of developing and bringing up the entire software stack on a System on Chip (SoC) or Multi-die system. It explores various approaches to deployment, highlighting their specific objectives and the unique challenges they address.
Introduction
As the saying goes, it’s… Read More
