Last week, Synopsys announced an expansion of their Hardware-Assisted Verification (HAV) portfolio to accelerate semiconductor design innovations. These advancements are designed to meet the increasing demands of semiconductor complexity, enabling faster and more efficient verification across software and hardware… Read More
Tag: synopsys
Webinar: Synopsys Collaboration Framework to Boost SoC/Chiplet Architecture Performance Analysis and Optimization
Date: March, 13 – 9 a.m. PST
Using virtual prototypes alongside early accessible performance models of new SoC or Chiplet architectures has become the de facto standard for early architecture performance modeling, exploration, and analysis. However, as designs and tools become increasingly complex, these virtual
Will 50% of New High Performance Computing (HPC) Chip Designs be Multi-Die in 2025?
Predictions in technology adoption often hinge on a delicate balance between technical feasibility and market dynamics. While business considerations play a pivotal role, the technical category reasons for the success or failure of a prediction are more tangible and often easier to identify—if scrutinized with care. However,… Read More
Webinar: Trends in Semiconductor System Design
About this event
Thank you to our sponsors, Synopsys and Cadence
The Trends in System Design event, hosted by DESN in Reading on February 6th, will be open to both members and non-members. We will examine emerging trends in semiconductor system design, with a particular focus on how AI/ML is being used in product design and the design… Read More
A Deep Dive into SoC Performance Analysis: Optimizing SoC Design Performance Via Hardware-Assisted Verification Platforms
Part 2 of 2 – Performance Validation Across Hardware Blocks and Firmware in SoC Designs
Part 2 explores the performance validation process across hardware blocks and firmware in System-on-Chip (SoC) designs, emphasizing the critical role of Hardware-Assisted Verification (HAV) platforms. It outlines the validation workflow… Read More
A Deep Dive into SoC Performance Analysis: What, Why, and How
Part 1 of 2 – Essential Performance Metrics to Validate SoC Performance Analysis
Part 1 provides an overview of the key performance metrics across three foundational blocks of System-on-Chip (SoC) designs that are vital for success in the rapidly evolving semiconductor industry and presents a holistic approach to optimize… Read More
SNUG Silicon Valley 2025
Connecting the Synopsys User Community
SNUG conferences have connected Synopsys global users for more than three decades. SNUG 2025 will once again provide a place where users and technical experts can meet, network, and share ideas about chip and system design.
Enhancing System Reliability with Digital Twins and Silicon Lifecycle Management (SLM)
As industries become more reliant on advanced technologies, the importance of ensuring the reliability and longevity of critical systems grows. Failures in components, whether in autonomous vehicles, high performance computing (HPC), healthcare devices, or industrial automation, can have far-reaching consequences.… Read More
SystemReady Certified: Ensuring Effortless Out-of-the-Box Arm Processor Deployments
When contemplating the Lego-like hardware and software structure of a leading system-on-chip (SoC) design, a mathematically inclined mind might marvel at the tantalizing array of combinatorial possibilities among its hardware and software components. In contrast, the engineering team tasked with its validation may have… Read More
Synopsys-Ansys 2.5D/3D Multi-Die Design Update: Learning from the Early Adopters
The demand for high-performance computing (HPC), data centers, and AI-driven applications has fueled the rise of 2.5D and 3D multi-die designs, offering superior performance, power efficiency, and packaging density. However, these benefits come with myriads of challenges, such as multi-physics, which need to be addressed.… Read More