While web browsing I constantly glance for the padlock symbol to indicate that the site is encrypting any of my form data by using the https prefix, which means that an SSL (Secure Sockets Layer) certificate is being used by the web hosting company. I have peace of mind knowing that my credit card information cannot be easily stolen… Read More
Tag: synopsys
Chiplet Interconnect Challenges and Standards
For decades now I’ve watched the incredible growth of SoCs in terms of die size, transistor count, frequency and complexity. Instead of placing all of the system complexity into a single, monolithic chip, there are now compelling reasons to use a multi-chip approach, like when the maximum die size limit is reached, or it’s… Read More
Driving the Future of HPC Through 224G Ethernet IP
The need for speed is a never-ending story when it comes to data communications. Currently there are a number of trends such as cloud computing, artificial intelligence, Internet of Things (IoT), multimedia applications and consumer expectations driving this demand. All of these trends are accelerating the growth in high-performance-computing… Read More
Chiplet Q&A with John Lee of Ansys
At the recent Synopsys Users Group Meeting (SNUG) I had the honor of leading a panel of experts on the topic of chiplets. One of those panelists was John Lee, Head of Electronics, Semiconductors and Optics at Ansys.
How is the signoff flow evolving and what is being done to help mitigate the growing signoff complexity challenge?
With… Read More
Curvilinear Mask Patterning for Maximizing Lithography Capability
Masks have always been an essential part of the lithography process in the semiconductor industry. With the smallest printed features already being subwavelength for both DUV and EUV cases at the bleeding edge, mask patterns play a more crucial role than ever. Moreover, in the case of EUV lithography, throughput is a concern, … Read More
Chiplet Q&A with Henry Sheng of Synopsys
At the recent Synopsys Users Group Meeting (SNUG) I had the honor of leading a panel of experts on the topic of chiplets. One of those panelists was the very personable Dr. Henry Sheng, Group Director of R&D in the EDA Group at Synopsys. Henry currently leads engineering for 3DIC, advanced technology and visualization.
Are we
… Read MorePodcast EP157: The Differentiated Role Andes Plays in the US with Charlie Cheng
Dan is joined by Charlie Cheng, Managing Director of Polyhedron. Prior to that, Charlie was the CEO of Kilopass Technology, where he grew the core memory business into a successful acquisition by Synopsys. Before that, Charlie was an Entrepreneur in Residence at US Venture Partners and a Corporate VP at Faraday Technology, a Taiwanese… Read More
Synopsys Accelerates First-Pass Silicon Success for Banias Labs’ Networking SoC
Banias Labs is a semiconductor company that develops infrastructure solutions for next-generation communications. Its target market is the high-performance computing infrastructure market including hyperscale data center, networking, AI, optical module, and Ethernet switch SoCs for emerging high-performance computing… Read More
Podcast EP156: A Chat With Shankar Krishnamoorthy About Strategy and Outlook for EDA Development at SNUG
This is another special edition of our podcast series. SemiWiki staff writer Kalar Rajendiran spoke with Shankar Krishnamoorthy, General Manager, Electronic Design Automation Group for Synopsys at the recent SNUG meeting,
Shankar discusses how Synopsys is focusing on hyperconvergence and implementation of AI across the… Read More
Podcast EP152: An Informal Conversation with Aart de Geus on AI and Multi-Die at SNUG
This is a special edition of our podcast series. At the recent Synopsys SNUG User Group, SemiWiki staff writer Kalar Rajendiran got the opportunity to conduct an informal interview with Aart de Geus, Chairman and CEO of Synopsys.
What follows are some of Aart’s thoughts on the deployment of AI across the semiconductor … Read More