As power levels rise and systems scale, high-power testing becomes more complex and time-consuming. This hands-on Power Solutions Seminar focuses on practical test strategies for batteries, fuel cells, green energy, and power conversion.
You will experience expert-led technical sessions with hands-on,
Satellite communications and design present complex challenges — from phased arrays to 5G non-terrestrial networks (NTNs). Are you equipped with the latest solutions to ensure mission success?
Join Keysight and CesiumAstro’s Vice President of Engineering, James Carwell, at our action-packed SpaceTech Symposium… Read More
Start the new year off right with fresh insights and sharp skills. Join Keysight experts in Calgary for an all-day Advanced Measurements Seminar and cocktail reception. This hands-on technical event features live demonstrations with the latest RF and high-speed digital technologies.
Gain practical,
Join Suren Singh, Application Engineer for Emerging Technologies, and fellow Keysight experts for a hands-on seminar that will help you do what you couldn’t before in RF measurement. Whether you’re looking to advance your expertise or stay ahead of emerging technologies, this hands-on seminar will equip you with the … Read More
What: Better IP Test with IJTAG
When: 26 March, 2013, 10:30am-1:30pm
Where: Mentor Graphics, 46871 Bayside Parkway, Fremont, CA 94538
If you are involved in IC test*, you’ve probably heard about the IEEE P1687 standard, called IJTAG for ‘internal’ JTAG. IJTAG defines a standard for embedded IP that includes simple… Read More
Last week I attended the Ansys/Apache seminars on “Dimensions of Electronic Design.” The two big challenges as we go down to 28nm and 20nm and below are keeping power manageable and keeping reliability up.
The big challenge with power is that we can put so much stuff on a die and clock it so fast that the power is exceeding… Read More
If you are involved in testing memory or logic of ARM-based designs, you’ll want to attend this free seminar on July 17, 2012 in Santa Clara. Mentor Graphics and ARM have a long standing partnership, and have optimized the Mentor test products (a.k.a Tessent) for the ARM processors and memory IP.
The lunch seminar runs from 10:30-1:00… Read More
Jasper has three seminars coming up in May in Hsinchu (Taiwan), Beijing and Shanghai. These are full-day seminars on how to solve critical verification challenges using state-of-the-art formal technology. Breakfast and lunch will be served.
This full-day tutorial will be given by technical experts for verification experts… Read More
Atrenta has four seminars coming up on SoC realization. More and more design is actually about finding IP and integrating it together at the block level, and then handing it off to a standard RTL to GDSII flow. The three focus areas are:
