As RF systems continue to evolve with wider bandwidths and higher frequencies, engineers are navigating faster plays, tighter margins, and more complex signals than ever before. The challenge is no longer capturing signals, it is turning those measurements into meaningful insights that accelerate design and validation.… Read More
Complex Signals. Clear Insights.
As RF systems continue to evolve with wider bandwidths and higher frequencies, engineers are collecting more measurement data than ever before. The challenge is no longer capturing signals, it is turning those measurements into meaningful insights that accelerate design and validation.… Read More
Skate Past Signal Complexity. Score Clearer Insights.
As RF systems continue to evolve with wider bandwidths and higher frequencies, engineers are navigating faster plays, tighter margins, and more complex signals than ever before. The challenge is no longer capturing signals, it is turning those measurements into meaningful… Read More
As RF systems continue to evolve with wider bandwidths and higher frequencies, engineers are navigating faster plays, tighter margins, and more complex signals than ever before. The challenge is no longer capturing signals, it is turning those measurements into meaningful insights that accelerate design and validation.… Read More
Hosted in collaboration with Professor Slim Boumaiza, Director of the Centre for Intelligent Antenna and Radio Systems (CIARS) at the University of Waterloo.
As RF systems continue to evolve with wider bandwidths and higher frequencies, engineers are navigating faster plays, tighter margins, and more complex signals than… Read More
IJTAG for IP Test: a free seminarby Beth Martin on 03-14-2013 at 1:53 pmCategories: EDA, Siemens EDA
What: Better IP Test with IJTAG
When: 26 March, 2013, 10:30am-1:30pm
Where: Mentor Graphics, 46871 Bayside Parkway, Fremont, CA 94538
If you are involved in IC test*, you’ve probably heard about the IEEE P1687 standard, called IJTAG for ‘internal’ JTAG. IJTAG defines a standard for embedded IP that includes simple… Read More
Last week I attended the Ansys/Apache seminars on “Dimensions of Electronic Design.” The two big challenges as we go down to 28nm and 20nm and below are keeping power manageable and keeping reliability up.
The big challenge with power is that we can put so much stuff on a die and clock it so fast that the power is exceeding… Read More