The Samsung Smart, Connected Lifestyle event was last night at the Bently Reserve in San Francisco. Getting into San Francisco was no picnic with all of the roadwork and new building construction. We even saw people drive up on the sidewalk to get around car clogs. It really was crazy but definitely worth it after seeing the first … Read More
Tag: semiconductor design
Realize the Genius of Your Design!
I think we can all agree that no matter what you are designing, FPGA prototyping can help. The challenge is getting the most out of the leading edge FPGA prototyping solutions and that requires a detailed understanding of how this technology works and what FPGA prototyping solutions match your design and verification requirements.… Read More
The Future of Chip Design in the Internet Age
Huge designs, spectacular design costs, astronomical capital expenditure. Welcome to the present day semiconductor industry. As discussed in my prior post, the days of democratized silicon access have been replaced by an elite market. Custom chips are once again a rich person’s game. Does it have to stay this way? I personally… Read More
ClioSoft Celebrates 2014 with 30% Revenue Growth!
One of the first companies we worked with when SemiWiki went live in 2011 was ClioSoft. They had a problem with a competitor spreading misinformation which is certainly not unheard of in EDA. When a company cannot compete technically sometimes they resort to dirty tricks or legal distractions. The first ClioSoft article we published… Read More
Chip Design – Coming of Age in the Computer Age
Previously, I examined chip design in the late 1970s and early 1980s. It was a nostalgic ride – thanks to all those who shared their stories. I enjoyed reading all of them. I drew two basic conclusions in the prior post:
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Beware of Parameter Variability in Clock Domain Crossings
How should we assess the risk of harmful metastability in a clock domain crossing (CDC) when the semiconductor process has significant parameter variability? One possibility is to determine the MTBF of a synchronizer at the worst-case corner of the CDC. But that approach has some conflicting complications:
- Synchronizer failures
Feed Your Mind and Body at 52nd DAC!
My beautiful wife and I attend the Design Automation Conference together whenever possible. More so now that she is the co-founder and CFO of SemiWiki. It is really nice for her to put a face to the invoices and personally thank our subscribers. Her first DAC was 1985 in Las Vegas. We were married for less than a year so it was like a second… Read More
Chip Design Problems Remain the Same, More or Less
For those who may not know me, here is a brief introduction. I started in the semiconductor business when RCA was still making vacuum tubes and I wrote EDA software before there was an EDA industry. I’ve designed and sold chips and developed, sold and used EDA tools at companies as big as General Electric and as small as seven people.… Read More
The 2015 DAC Designer and IP Track
What an exciting year for DAC with record submissions in nearly every category. Most impressive is the increase in Designer and IP Track submissions, content that is helping to continue to evolve and improve the show. If you haven’t already registered, why not do so now?
A brief bit of background about the conference: DAC’s roots… Read More
SecurCore: Modern Hardware Security Approach
The increasing number of interconnected devices grows day by day and has slowly begun expansion into other consumer products. The need for safe, efficient, and reliable systems that meet modern user expectations has become increasingly important as a result. SoC engineers addressing these challenges must consider design … Read More