Enabling Edge AI Vision with RISC-V and a Silicon Platform

Enabling Edge AI Vision with RISC-V and a Silicon Platform
by Tom Simon on 03-15-2021 at 10:00 am

AI Chipset Market

AI vision processing moving to the edge is an undeniable industry trend. OpenFive, the custom silicon business unit of SiFive, discusses this trend with compelling facts in their recent paper titled “Enabling AI Vision at the Edge.” AI vision is being deployed in many applications, such as autonomous vehicles, smart cities, … Read More


CEO Interview: Dr. Shafy Eltoukhy of OpenFive 

CEO Interview: Dr. Shafy Eltoukhy of OpenFive 
by Daniel Nenni on 03-05-2021 at 6:00 am

Shafy Eltoukhy

Dr. Shafy Eltoukhy has over 35 years of experience in the semiconductor industry. He served as VP and BU manager of the Analog Mixed Signal Group at Microsemi. He was the VP of Operations and Technology Development at Open-Silicon. He was the VP of Technology at Lightspeed Semiconductor where he joined the founding team that invented… Read More


Automatic End-to-End Formal Verification of RISC-V Processors

Automatic End-to-End Formal Verification of RISC-V Processors
by Admin on 02-24-2021 at 8:38 am

Overview

Processor verification has always been a significant challenge. With the open-source RISC-V® ISA, we see an emerging revolution for processor design with lots of new commercial-grade processors for a wide range of applications ranging from embedded, storage, automotive, AI/ML, 5G, to IoT. While power, performance,

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SiFive Expands RISC-V Technology and its Ecosystem at the Fall Linley Processor Conference

SiFive Expands RISC-V Technology and its Ecosystem at the Fall Linley Processor Conference
by Mike Gianfagna on 11-11-2020 at 10:00 am

SiFive Expands RISC V Technology and its Ecosystem at the Fall Linley Processor Conference

 

As the Linley Fall Processor Conference winds down, there are certain presenting companies that left a lasting impression.  SiFive is one of those companies. On October 21, SiFive introduced the newest member of the SiFive Intelligence family of processor coresSiFive Intelligence family of processor cores, based on… Read More


Nvidia Arm Acquisition Talking Points

Nvidia Arm Acquisition Talking Points
by Daniel Nenni on 10-30-2020 at 10:00 am

Nvidia Arm Acquisition 2020

Before founding SemiWiki I competed with Arm on many different levels throughout my career and I have had various business dealings with them since. SemiWiki also published the definitive book on Arm: “Mobile Unleashed” which goes deep into the history of Arm and the top SoC companies (Qualcomm, Apple, and Samsung).… Read More


Webinar: Static Verification for RISC-V Cores and SoCs

Webinar: Static Verification for RISC-V Cores and SoCs
by Daniel Nenni on 09-28-2020 at 6:00 am

Aldec RISC V Webinar SemiWiki 1

RISC-V has been trending ever since it landed on SemiWiki in 2016.  Even more so now that Arm is in flux with the Nvidia acquisition. Verification is a fast growing EDA challenge with the number of verification engineers steadily outpacing design, so this webinar is a best case scenario for SemiWiki traffic, absolutely.

Two thingsRead More


WEBINAR: UVM RISC-V and DV

WEBINAR: UVM RISC-V and DV
by Daniel Payne on 09-21-2020 at 10:00 am

UVM Testbench RISC-V

Oh, our semiconductor industry just loves acronyms, and the title of my blog packs three of the most popular acronyms together at once. I attended a webinar hosted by Aldec last week on this topic, “UVM Simulation-based environment for Ibex RISC-V CPU core with Google RISC-V DV“. Verification engineers have been … Read More


CORE-V HW and SW in the FPGA environment

CORE-V HW and SW in the FPGA environment
by Daniel Nenni on 08-13-2020 at 9:01 am

Episode 3 of OpenHW TV will air live on 20th August at 11am EST / 4pm BST / 8am PST and will give a detailed update of work in our HW and SW Task Groups, as well as featuring guest member Ashling.

You will hear from the Chairs of the groups about the work of the SW and HW Task Groups to date, including an outlook to future roadmaps. We look

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