Last week I attended the Ansys/Apache seminars on “Dimensions of Electronic Design.” The two big challenges as we go down to 28nm and 20nm and below are keeping power manageable and keeping reliability up.
The big challenge with power is that we can put so much stuff on a die and clock it so fast that the power is exceeding… Read More
In one of those odd coincidences, I was having dinner with a friend last week and somehow the Carrington Event came up. Then I read a a piece in EETimesabout whether electrical storms could cause problems in the near future. Even that piece didn’t mention the Carrington Event so I guess George Leopold, the author, hasn’t… Read More
Analyzing the operation of a modern SoC, especially analyzing its power distribution network (PDN) is getting more and more complex. Today’s SoCs no longer operate on a continuous basis, instead functional blocks on the IC are only powered up to execute the operation that is required and then they go into a standby mode, … Read More
3D IC design and what has come to be known as 2½D IC design, with active die on a silicon interposer, require new approaches to verification since the through silicon vias (TSVs) and the fact that several different semiconductor processes may be involved create a new set of design challenges
The power delivery network is a challenge… Read More
The Totem webinar will be at 11am on Tuesday 2nd August. This session will be conducted by Karan Sahni, Senior Applications Engineer at Apache Design Solutions. Karan has been with Apache since 2008, supporting the Redhawk, Totem, Sentinel product lines. He received his MS in Electrical Engineering from the Syracuse University… Read More
