Best Verifiable QoR – A Formal Equivalence Checking Yardstick

Best Verifiable QoR – A Formal Equivalence Checking Yardstick
by Daniel Nenni on 09-08-2020 at 10:00 am

sathappanpalaniappan

To achieve maximal QoR, Broadcom wanted to take advantage of all the advanced optimizations that Design Compiler offers. These optimizations, however, are of little value if they cannot be verified through Formal Equivalence Checking.

This presentation details how Formality Equivalence Checking gave Broadcom the confidence… Read More


Webinar: Optimizing QoR for FPGA Design

Webinar: Optimizing QoR for FPGA Design
by Bernard Murphy on 10-22-2017 at 12:00 pm

You might wonder why, in FPGA design, you would go beyond simply using the design tools provided by the FPGA vendor (e.g. Xilinx, Intel/Altera and Microsemi). After all, they know their hardware platform better than anyone else, and they’re pretty good at design software too. But there’s one thing none of these providers want to… Read More


The fixed and the finite: QoR in FPGAs

The fixed and the finite: QoR in FPGAs
by Don Dingee on 07-22-2013 at 1:00 pm

There is an intriguingly amorphous term in FPGA design circles lately: Quality of Results, or QoR. Fitting a design in an FPGA is just the start – is a design optimal in real estate, throughput, power consumption, and IP reuse? Paradoxically, as FPGAs get bigger and take on bigger signal processing problems, QoR has become a larger… Read More