Breakthrough Gains in RTL Productivity and Quality of Results with Cadence Joules RTL Design Studio

Breakthrough Gains in RTL Productivity and Quality of Results with Cadence Joules RTL Design Studio
by Kalar Rajendiran on 08-08-2023 at 10:00 am

Joules RTL Design Studio Benefits

Register Transfer Level (RTL) is a crucial and valuable concept in digital hardware design. Over the years, it has played a fundamental role in enabling design of complex digital chips. By abstracting away implementation details and providing a clear description of digital behavior, RTL has contributed significantly to the… Read More


Webinar: Optimize Test QoR & TTM with AI-Driven Technology

Webinar: Optimize Test QoR & TTM with AI-Driven Technology
by Admin on 07-07-2023 at 2:22 pm

Synopsys Webinar | Wednesday, August 23, 2023 | 10:00 a.m. PDT

Continuously increasing semiconductor design sizes and complexity have resulted in increased test costs. Today’s competitive environment and critical market windows are pushing companies to adopt aggressive design schedules. The traditional method of manual

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Webinar: Achieving the Best Verifiable QoR using Formal Equivalence Verification for PPA-Centric Designs

Webinar: Achieving the Best Verifiable QoR using Formal Equivalence Verification for PPA-Centric Designs
by Admin on 09-14-2022 at 1:57 pm

Synopsys Webinar | Tuesday, September 20, 2022 | 10 a.m. Pacific

Synopsys Fusion Compiler offers advanced optimizations to achieve the best PPA (power, performance, area) on today’s high-performance cores and interconnect designs. However, advanced transformation techniques available in synthesis such as retiming, multi-bit

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Best Verifiable QoR – A Formal Equivalence Checking Yardstick

Best Verifiable QoR – A Formal Equivalence Checking Yardstick
by Daniel Nenni on 08-18-2020 at 8:18 am

To achieve maximal QoR, Broadcom wanted to take advantage of all the advanced optimizations that Design Compiler offers. These optimizations, however, are of little value if they cannot be verified through Formal Equivalence Checking.

This presentation details how Formality Equivalence Checking gave Broadcom the confidence… Read More


Webinar: Optimizing QoR for FPGA Design

Webinar: Optimizing QoR for FPGA Design
by Bernard Murphy on 10-22-2017 at 12:00 pm

You might wonder why, in FPGA design, you would go beyond simply using the design tools provided by the FPGA vendor (e.g. Xilinx, Intel/Altera and Microsemi). After all, they know their hardware platform better than anyone else, and they’re pretty good at design software too. But there’s one thing none of these providers want to… Read More


The fixed and the finite: QoR in FPGAs

The fixed and the finite: QoR in FPGAs
by Don Dingee on 07-22-2013 at 1:00 pm

There is an intriguingly amorphous term in FPGA design circles lately: Quality of Results, or QoR. Fitting a design in an FPGA is just the start – is a design optimal in real estate, throughput, power consumption, and IP reuse? Paradoxically, as FPGAs get bigger and take on bigger signal processing problems, QoR has become a larger… Read More