Webinar: Accelerate IC Layout Parasitic Analysis with ParagonX

Webinar: Accelerate IC Layout Parasitic Analysis with ParagonX
by Admin on 12-19-2025 at 12:45 pm

We are pleased to offer two webinar sessions for your convenience. Please choose the time that best fits your schedule:

10:00AM – 12:00PM CET (session #1 for EMEA/APAC)
10:00AM – 12:00PM PST (session #2 for NA)

Featured Speakers:

  • Kopal Kulshreshtha, Principal Product Specialist, Synopsys
  • Rob Dohanyos, Principal Product
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Gate Resistance in IC design flow

Gate Resistance in IC design flow
by Maxim Ershov on 05-03-2023 at 6:00 am

Figure1 9

MOSFET gate resistance is a very important parameter, determining many characteristics of MOSFETs and CMOS circuits, such as:

• Switching speed
• RC delay
• Fmax – maximum frequency of oscillations
• Gate (thermal) noise
• Series resistance and quality factor in MOS capacitors and varactors
• Switching speed and uniformity… Read More


CEO Interview: Maxim Ershov of Diakopto

CEO Interview: Maxim Ershov of Diakopto
by Daniel Nenni on 09-24-2021 at 4:00 am

Maxim Ershov

Maxim is a scientist, engineer, and entrepreneur. His expertise is in physics, mathematics, semiconductor devices, and EDA. Prior to co-founding Diakopto, Maxim worked at Apple’s SEG (Silicon Engineering Group), where he was responsible for parasitic extraction. Before Apple, he was CTO of Silicon Frontline Technology,… Read More