embARC for a Free Ride

embARC for a Free Ride
by Eric Esteve on 03-30-2015 at 3:27 am

It’s probably the first time that Synopsys is offering such a direct access to free and open source software. The goal is to support customers developing application code for IoT and embedded devices based on ARC IP core family. The designer can select the Real Time Operating System (RTOS) which best meet the system requirements,… Read More


Vlang – Opportunities Galore for Productivity & Performance

Vlang – Opportunities Galore for Productivity & Performance
by Pawan Fangaria on 08-19-2014 at 2:01 pm

Yes, verification technologies are open to innovation for improved productivity and performance in the face of ever growing SoC/IP design sizes and complexities. There is not much scope left in processor speed to improve, other than multi-core processors in servers which again need software properly architected to be thread-able… Read More


Open Source Verilog

Open Source Verilog
by Paul McLellan on 08-03-2014 at 8:01 am

Over the years there have been various open source EDA projects but none that has realized a full industrial strength design tool that has broad adoption and is strong enough to compete with similar products from the EDA industry.

Open source is clearly a great way to develop software. Lots of people can see all the source code and … Read More


Then, Python walked in for verification

Then, Python walked in for verification
by Don Dingee on 07-31-2014 at 12:00 am

Go ahead – type “open source” into the SemiWiki search box. Lots of recent articles on the IoT, not so many on EDA tools. Change takes a while. It has only been about five years since the Big Three plus Aldec sat down at the same table to work on UVM. Since then, Aldec has also gotten behind OS-VVM, and is now linked to a relatively new open… Read More


Chip side of the Open Interconnect Consortium

Chip side of the Open Interconnect Consortium
by Don Dingee on 07-09-2014 at 9:00 pm

Maybe it’s my competitive analysis gene, or too many years spent hanging out with consortium types, but I’m always both curious and skeptical when a new consortium arises – especially in a crowded field of interest. The dynamics of who aligns with a new initiative, and how they plan to go to market compared to other entities, prompts… Read More


Atmel and the Arduino Zero

Atmel and the Arduino Zero
by Paul McLellan on 05-15-2014 at 7:00 am

As I wrote about last month, this weekend is the Maker Faire in San Mateo. If you are interested in the cutting edge of what people are getting up to outside of the corporate world, this is the place to go. You will see stuff that you will not hear about for a year or two when it finally goes mainstream.

Increasingly, there is a lot of electronics… Read More


You didn’t say it has to work

You didn’t say it has to work
by Don Dingee on 04-22-2014 at 8:00 pm

“Failure to plan is planning to fail.” If that is true – and it has been quoted verbatim or slightly modified so many times throughout modern history, there has to be some truth – why does most of the engineering community seem to detest planning so much?

Engineering planning doesn’t mean whipping out a block diagram or pseudo code,… Read More


Galileo, not a barber, but an Intel maker module

Galileo, not a barber, but an Intel maker module
by Don Dingee on 03-13-2014 at 3:00 pm

Words often have much deeper meaning than first meets the ear. The story behind a lyric, or a name, reveals origins, philosophical themes, and ideas beyond the obvious. A new effort from Intel conjures up just such an example – a deep reference to makers everywhere.

In a familiar refrain from Queen “Bohemian Rhapsody,” we hear two… Read More


IoT begets silicon, interoperability, and standards

IoT begets silicon, interoperability, and standards
by Don Dingee on 11-19-2013 at 5:00 pm

The Internet of Things is on every technology mind these days, but what does it mean for the EDA community? Dennis Brophy of Mentor Graphics says the billions of things we are hearing about will not happen unless we find a way to build a lot more things, efficient things, and connected things. He has more thoughts in our recent interview.… Read More


A random walk down OS-VVM

A random walk down OS-VVM
by Don Dingee on 05-13-2013 at 11:14 am

Unlike one prevailing theory of financial markets, digital designs definitely don’t function or evolve randomly. But many engineers have bought into the theory that designs can be completely tested randomly. Certainly there is value to randomness, exercising all combinations of inputs, including unexpected ones a designer… Read More