A song of optimization and reuse

A song of optimization and reuse
by Don Dingee on 07-01-2014 at 10:00 am

If you hang around engineers for any time at all, the word optimization is bound to come up. The very definition of engineer is to contrive or devise a solution. With that anointing, most engineers are beholden to the idea that their job is creating, synthesizing, and perfecting a solution specifically for the needs of a unique situation.… Read More


Sensor clusters at edge call for NoCs nearby

Sensor clusters at edge call for NoCs nearby
by Don Dingee on 04-17-2014 at 6:30 pm

In his recent blog on EETimes, Kurt Shuler of Arteris took a whimsical look at the hype surrounding the IoT, questioning the overall absence of practicality and a seemingly misplaced focus on use cases at the expense of a coherent architecture. I don’t think it is all that bleak, but when it comes to architecture, Kurt is right, and… Read More


The (re)making of Arteris, 1-2-3

The (re)making of Arteris, 1-2-3
by Don Dingee on 03-06-2014 at 6:00 pm

Success in a business with extended design-in cycles may look easy. In reality, there is a delicate balance between many factors. Some come to mind immediately: developing and releasing a good product in the first place; winning and keeping the right customers, not too few or too many; balancing investment between support and … Read More


Compositions allow NoCs to connect easier

Compositions allow NoCs to connect easier
by Don Dingee on 01-27-2014 at 6:00 pm

I blame it on Henry Ford, William Levitt, and the NY State Board of Regents, among others. We went through a phase with this irresistible urge to stamp out blocks of sameness, creating mass produced clones of everything from cars to houses to students.

Thank goodness, that’s pretty much over. The thinking of simplifying system design… Read More


5 Rules of Power Management Using NoCs

5 Rules of Power Management Using NoCs
by Paul McLellan on 11-18-2013 at 4:30 pm

If it has escaped your notice that power management on SoCs is important then you need to get out more. Increasingly, the complexity of the interconnect between the various processors, memories, offload processors, devices, interfaces and other blocks means that the best way to implement it is to use a network on chip (NoC). But… Read More


Qualcomm and Arteris: the CEO Speaks

Qualcomm and Arteris: the CEO Speaks
by Paul McLellan on 10-31-2013 at 5:25 pm

Arteris finally announced this morning, as rumored, that Qualcomm is acquiring “certain technology assets” and hired personnel formerly employed by Arteris. The financial terms were not disclosed.

I talked to Charlie Janac, the CEO, today. The first thing I asked him is why such a convoluted deal, I’ve never… Read More


Qualcomm Arteris deal

Qualcomm Arteris deal
by Eric Esteve on 10-31-2013 at 10:32 am

Is it really a surprise if Qualcomm, the undisputed leader of Application Processor (AP) and BaseBand (BB) IC for wireless mobile, already one of the Arteris investors (with ARM, Synopsys, Docomo Capital and a bunch of VC), eventually acquires the best NoC IP technology (the technology, the engineering team and the rights, but… Read More


Open Letter from Sonics to Arteris

Open Letter from Sonics to Arteris
by Paul McLellan on 10-27-2013 at 2:00 pm

I don’t remember seeing an open letter from one EDA or IP company to another until today. Sonics have published an open letter to Charlie Janac, the CEO of Arteris. What seems to have happened is that Arteris have sold their assets to Qualcomm and the development team (which is based in France) and several AEs are already Qualcomm… Read More


History of SoC Interconnect Fabric

History of SoC Interconnect Fabric
by Eric Esteve on 10-14-2013 at 4:18 am

I just read this very interesting article posted by Kurt Shuler from Arteris, describing the “History of SoC Interconnect Fabric” and explaining why the SC industry needs an advanced approach, named the “fourth phase of the Interconnect Fabric history” in the article. Kurt’s point of view is that in the past the SoC interconnect… Read More


How to reduce routing congestion in large Application Processor SoC?

How to reduce routing congestion in large Application Processor SoC?
by Eric Esteve on 07-14-2013 at 10:22 am

Application Processor SoC integrates more and more functions, generation after generation, challenging performance, cost, power efficiency, reliability, and time-to-market. But the maximum die size can’t increase, at least because of the constraints linked with wafer production, manufacturability, yield and finally… Read More