Complete RTL to GDSII Flow for “Analog on Top” Designs
Overview
Mentor will highlight our Tanner Digital Implementer (TDI) tool, powered by the Oasys Digital Synthesis and Nitro Place and Route engines, and
Tag: mentor
Valor Process Preparation Webinar – Process Prep Overview
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Online – Jun 24, 2020
11:00 AM – 11:30 AM US/Pacific
11:00 AM – 11:30 AM US/Pacific
Overview
Valor Process Preparation is the most complete solution for preparing manufacturing collateral on the market today. Learn about the latest released capability that has been delivered in the latest version as well
Tessent SiliconInsight ATE-Connect: Bending the bring up schedule curve in your favor
Overview
With the number of IP blocks and complexity of designs increasing, how do you improve your TTM for debug of a test program to production? Teradyne
Error Reduction in the Design Definition Phase
Overview
Schematic entry sounds like a simple task. But the simple and often obvious errors are the ones that cause major delays: wrong or forgotten voltages,
Introduction to Visualizer for the Verilog Users
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Online – Jun 16, 2020
8:00 AM – 9:00 AM US/Pacific
8:00 AM – 9:00 AM US/Pacific
Overview
Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines,
Introducing ODB++Process
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Online – Jun 11, 2020
11:00 AM – 12:00 PM Etc/GMT+3
11:00 AM – 12:00 PM Etc/GMT+3
Overview
Siemens introduces its newest data exchange format for electronic manufacturing equipment vendors, ODB++Process (formally known as OPM). ODB++Process (ODB++P) enables the exchange of intelligent assembly
Questa Clock/Reset Domain Crossing Verification / Mentor Functional Safety Compliance – What’s New in Functional Verification from Mentor: Session 5
This is the fifth of a 5-part series on “What’s New in Functional Verification from Mentor.” Each session will be presented twice at the times shown above
Machine Learning to Accelerate Electronic Design
Overview
The Golden Age of machine learning is upon EDA. Over the last few years, we have seen companies grow their ML teams and strategies, and ML research projects
Tessent Safety – Entering the Safety Ecosystem: a reference flow for automotive IC test
Overview
Industry-leading innovations in automotive electronics has immensely contributed in the development of advanced safety mechanism resulting
Taking SystemVerilog Arrays to the Next Dimension
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Online – Jun 5, 2020
8:15 AM – 8:45 AM US/Pacific
8:15 AM – 8:45 AM US/Pacific
Overview
Chris Spear, Principle Instructor, presents a detailed description of the various array types in the SystemVerilog language, and how to pick the right ones for your testbench. SystemVerilog has many dynamic data types,