You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please,
join our community today!
By Vikash Kumar, Senior Verification Architect | Arm | IEEE Senior Member.
The Problem Every Verification Engineer Recognizes
You ask an LLM to generate a UVM testbench. It produces 25 files. Everything compiles. You run the simulation — and nothing happens. The scoreboard reports zero checks. The slave driver stops after 10… Read More
I’ve blogged about Methodics before they were acquired by Perforce back in 2020, so I wanted to get an update on Perforce IPLM (IP Lifecycle Management) by attending their recent webinar. Hassan Ali Shah, Senior Product Manager and Rien Gahlsdor, Perforce IPLM Product Owner were the two webinar presenters. Their IPLM enables … Read More
This isn’t a deep article. I only want to help head off possible confusion over this term. I have recently seen “vibe coding” pop up in discussions around AI for code generation. The name is media-friendly giving it some stickiness in the larger non-technical world, always a concern when it comes to anything AI. The original intent… Read More
On July 9, 2025, a DACtv session illuminated the transformative role of artificial intelligence (AI) in chip design, as presented by Ankur Gupta of Siemens EDA in the YouTube video. The speaker explored how AI is revolutionizing electronic design automation (EDA), addressing the semiconductor industry’s challenges in managing… Read More
On July 9, 2025, a DACtv session by Dr. Peter Levin explored the transformative impact of artificial intelligence (AI) on chip design, as presented in the YouTube video. The speaker, an industry expert, delved into how AI is reshaping electronic design automation (EDA), addressing the escalating complexity of modern chips and… Read More
We have a shortage of reference designs to test detection of security vulnerabilities. An LLM-based method demonstrates how to fix that problem with structured prompt engineering. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford,… Read More
Whatever software engineering teams are considering around leveraging AI in their development cycles should be of interest to us in hardware engineering. Not in every respect perhaps but there should be significant commonalities. I found a recent paper on the Future of AI-Driven Software Engineering from the University of … Read More
AI has changed a lot in the last ten years. In 2012, convolutional neural networks (CNNs) were the state of the art for computer vision. Then around 2020 vison transformers (ViTs) redefined machine learning. Now, Vision-Language Models (VLMs) are changing the game again—blending image and text understanding to power everything… Read More
And just like that, the AI PC arrived. It will be hard to miss high-profile advertising campaigns like the one just launched by Microsoft touting them. Gartner said this September that AI PCs will be 43% of all PC shipments in 2025 (with 114M units projected) and that by 2026, AI PCs will be the only choice for business laptop users. … Read More
Many of you are already familiar with Silicon Catalyst and the value it brings to semiconductor startups, the industry and the electronics industry at large. Silicon Catalyst is an organization that supports early-stage semiconductor startups with an ecosystem that provides tools and resources needed to design, create, and… Read More