Tag: intel

Podcast EP205: A Multi-Decade View of Process and Device Innovation at Intel with Paul Fischer

Podcast EP205: A Multi-Decade View of Process and Device Innovation at Intel with Paul Fischer
by Daniel Nenni on 01-26-2024 at 10:00 am
2 Comments

Dan is joined by Paul Fischer. Paul is the director of Chip Mesoscale Processing in Intel’s Components Research. He and his team are currently working on Gallium Nitride for energy efficient power delivery and RF communications, and technologies for heterogeneous monolithic integration.

Paul discusses the innovations… Read More

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IEDM 2023 – Imec CFET

IEDM 2023 – Imec CFET
by Scotten Jones on 01-17-2024 at 6:00 am
Categories: Events, Semiconductor Services, TechInsights
6 Comments

29 1 Wed Horiguchi 3 final Page 04

At IEDM 2023, Naoto Horiguchi presented on CFETs and Middle of Line integration. I had a chance to speak with Naoto about this work and this write up is based on his presentation at IEDM and our follow up discussion. I always enjoy talking to Naoto, he is one of the leaders in logic technology development, explains the technology in … Read More

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How Disruptive will Chiplets be for Intel and TSMC?

How Disruptive will Chiplets be for Intel and TSMC?
by Daniel Nenni on 01-15-2024 at 10:00 am
Categories: Chiplet, Foundries, Intel, TSMC
7 Comments

UCIe Consortium

Chiplets (die stacking) is not new. The origins are deeply rooted in the semiconductor industry and represent a modular approach to designing and manufacturing integrated circuits. The concept of chiplets has been energized as a response to the recent challenges posed by the increasing complexity of semiconductor design. … Read More

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IEDM: What Comes After Silicon?

IEDM: What Comes After Silicon?
by Paul McLellan on 01-09-2024 at 10:00 am
Categories: Events, Foundries, GAA, Intel

Screen Shot 2024 01 05 at 8.50.58 AM

The annual International Electron Devices Meeting (IEDM) took place last month. One of the presentations on the short course was by Matthew Metz of Intel titled New Materials Systems for Moore’s Law Continuation. In essence this was a look at some of the possibilities for what comes after silicon runs out of steam.

Matthew started… Read More

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IEDM 2023 – Modeling 300mm Wafer Fab Carbon Emissions

IEDM 2023 – Modeling 300mm Wafer Fab Carbon Emissions
by Scotten Jones on 01-09-2024 at 6:00 am
Categories: Events, Semiconductor Services, TechInsights
5 Comments

Figure 1

For the first time ever, IEDM held a sustainability session at the 2023 conference. I was one of the authors who presented an invited paper, the following is a summary of my presentation.

Call to Action

From the United Nations [1]:

“Climate Change is the defining issue of our time, and we are at a defining moment.”

“Without drastic … Read More

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Is Intel cornering the market in ASML High NA tools? Not repeating EUV mistake

Is Intel cornering the market in ASML High NA tools? Not repeating EUV mistake
by Robert Maire on 12-24-2023 at 9:00 am
Categories: Lithography, Semiconductor Advisors, Semiconductor Services
10 Comments

High NA EUV
  • Reports suggest Intel will get 6 of 10 ASML High NA tools in 2024
  • Would give Intel a huge head start over TSMC & Samsung
  • A big gamble but a potentially huge pay off
  • Does this mean $4B in High NA tool sales for ASML in 2024?

News suggests Intel will get 6 of first 10 High NA tools made by ASML in 2024

An industry news source, Trendforce, reports… Read More

Podcast EP198: How Lightmatter Creates the Foundation for the Next Moore’s Law with Ritesh Jain

Podcast EP198: How Lightmatter Creates the Foundation for the Next Moore’s Law with Ritesh Jain
by Daniel Nenni on 12-15-2023 at 10:00 am

Dan is joined by Ritesh Jain. Ritesh is the senior vice president of engineering and operations for Lightmatter. Prior to joining Lightmatter, Ritesh was a vice president in Intel’s Data Center and AI group where he directed the hardware development across silicon packaging, power integrity, signal integrity, mechanical &… Read More

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UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem

UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem
by Kalar Rajendiran on 12-11-2023 at 6:00 am
Categories: Chiplet, EDA, IP, Synopsys

Pike Creek UCIe Test chip

Intel recently made headlines when CEO Pat Gelsinger unveiled the world’s first UCIe interoperability test chip demo at Innovation 2023. The test chip built using advanced packaging technology is codenamed Pike Creek and is used to demonstrate interoperability across chiplets designed by Intel and Synopsys. More details … Read More

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Predicting Stochastic Defectivity from Intel’s EUV Resist Electron Scattering Model

Predicting Stochastic Defectivity from Intel’s EUV Resist Electron Scattering Model
by Fred Chen on 11-22-2023 at 6:00 am
Categories: Intel, Lithography

Predicting Stochastic Defectivity from Intel's EUV Resist Electron Scattering Model

The release and scattering of photoelectrons and secondary electrons in EUV resists has often been glossed over in most studies in EUV lithography, despite being a fundamental factor in the image formation. Fortunately, Intel has provided us with a laboriously simulated electron release and scattering model, using the GEANT4… Read More