Analog IC layout is a demanding endeavor as it entails conforming to complex layout design rules, interpreting design intentions from the schematics and understanding arcane topics like transistor matching, noise tolerance, parasitics and latch up. These skills are often handed down from one generation to the next, one on … Read More
Dan is joined by Ciaran Whyte, one of the founding members of IC Mask Design. As Chief Technical Officer he is responsible for all technical activity and the development and administration of all training courses. Cíaran has been training layout engineers for over 25 years and has completed layout training with over 600 engineers… Read More
A major challenge in the field of layout design lies in the post-layout parasitic extraction process, which often introduces delays and the potential for significant modifications in the layout. This paper introduces a novel approach to address this challenge, providing real-time parasitic estimations using Width Spacing… Read More
The custom physical implementation of circuit designs is a critical component of the integrated circuit (IC) process. Unfortunately, this step has been known to be one of the most time-consuming and prone to human error. Therefore, the need for a methodology that allows for faster, more accurate, and less error-prone work is … Read More
Power and Ground design can be problematic to implement, especially in lower metals. Layout can end up being very crowded and result in a compromise between routing and power structure. Power grid can be time and labor intensive for implementation largely due to the fact that often signal routing is done first and Power Grid is added… Read More
