The GSA European Executive Forum, GSA’s premier event in Europe, will unfold over two exciting days, bringing together over 250 senior executives, influential speakers, and esteemed exhibitors from around the globe. This prestigious gathering will further solidify its reputation as the ultimate executive event for the semiconductor… Read More
The RISC-V Summit Europe is the premier event that connects the European movers and shakers – from industry, government, research, academia and ecosystem support – that are building the future of innovation on RISC-V.
RISC-V, the open standard instruction set architecture (ISA), is enabling a range of new applications and… Read More
Joining forces
The Pan-European Electronics Design Conference is jointly hosted and organized by FED and IPC – two associations representing more than 3,700 companies from the electronics industry.
PEDC in a nutshell
The 1st Pan-European Electronics Design Conference (PEDC) is a one of a kind Pan-European conference with … Read More
Where your digital transformation gets real. Fast.
Join us at Realize LIVE Europe 2025 and experience the energetic general sessions, the engaging Solutions Center and the insightful workshops.
See firsthand the Siemens Software community event and witness again where your digital transformation gets real. Fast.
Why you
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DVClub Europe: Edinburghby Admin on 01-08-2025 at 10:14 pm
Theme: Mixed Signal Verification
Analog mixed signal chips continue to grow in both demand and complexity, and a consistent efficient verification approach remains a key topic for concern. This DVClub will be held at the Futures Institute at the University of Edinburgh and the university students will be attending. The first… Read More
Pratik Mahajan, Synopsys VC Formal R&D Group Director, kicked off an absorbing event featuring talks from multiple customers in Europe. He spent some time on formal signoff, an important topic that I’m still not sure is fully understood. Answering the questions “OK, we did a bunch of formal checking but how does that affect… Read More
I just read Daniel Nenni’s blog titled “Is Silicon Valley Gridlock a Good Sign for Semiconductors?” Dan, there is no definitive answer to this, I mean in terms of semiconductors. Let me call it Semiconductor Gridlock in Silicon Valley. Yes it’s good because Silicon Valley promotes research, brings up innovative technology and… Read More
Jasper at DVCon and EJUGby Paul McLellan on 03-13-2014 at 7:05 pmCategories: EDA
The Jasper European User Group meeting (EJUG) is coming up in a couple of weeks. It will be held in the Munich Hilton (which I have stayed in many times, the S-bahn from the airport pretty much stops in the basement) on April 2nd.
The schedule for the day is:
9:00 AM – Registration and continental breakfast
9:30 AM – Jasper… Read More
